CN214956854U

CN214956854U - Chip packaging structure

Info

Publication number: CN214956854U
Application number: CN202023318021.8U
Authority: CN
Inventors: 彭建军
Original assignee: Hefei Zuan Investment Partnership Enterprise
Current assignee: Hefei Zuan Investment Partnership Enterprise
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-11-30
Anticipated expiration: 2030-12-31

Abstract

The utility model provides a chip packaging structure provides a chip that has Bump metal Bump, electroplates the first metal level of one deck with the back of chip, electroplate one deck second metal level on at least one lateral wall of chip, first metal level with the second metal level is connected, carries out the plastic envelope to the good chip of electroplating and forms the plastic-sealed body to draw forth the pin, first pin is connected with Bump metal Bump, and the second pin is connected with the second metal level. In the packaging body space of the same size, the space utilization rate can be maximized, the second metal layer is arranged in a wall-attaching manner, the space waste can be greatly reduced, and therefore the chips with larger sizes can be packaged in the packaging body space of the same size. Otherwise, the same size chip adopts the utility model provides a packaging structure can dwindle the encapsulation size greatly. In addition, the first metal layer and the second metal layer are exposed outside, so that the heat dissipation efficiency of the chip can be improved, and the service life of the chip is prolonged.

Description

Chip packaging structure

Technical Field

The utility model relates to a semiconductor package technical field especially relates to chip package structure.

Background

The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures such as inspection, Test, packaging and the like, and finally warehousing and shipping.

When WB packages are performed, Bump bumps of a chip and positions of lead points on a frame are connected through metal wires, and this connection inevitably wastes a large space in packages of the same size, as shown in fig. 1, part a in the figure is a wasted space, so that the space utilization rate in packages of the same size is reduced, that is, the size of the chip in the packages is inevitably greatly reduced.

SUMMERY OF THE UTILITY MODEL

The utility model provides a chip packaging structure can increase the space utilization of packaging body greatly.

The utility model discloses the technical scheme who takes as follows:

the chip packaging structure comprises a chip with Bump metal bumps, wherein the surface of the chip with the Bump metal bumps is an active surface, the opposite surface of the chip is a back surface, a first metal layer is electroplated on the back surface of the chip, a second metal layer is electroplated on at least one side wall of the chip, the first metal layer is connected with the second metal layer, the electroplated chip is subjected to plastic packaging to form a plastic packaging body, a first pin and a second pin are led out, the first pin is connected with the Bump metal bumps, and the second pin is connected with the second metal layer.

Furthermore, an isolation layer is arranged between the second metal layer and the side wall.

Furthermore, the first metal layer and the second metal layer are made of the same or different materials, and can be electroplated simultaneously or at different time intervals.

Further, the first metal layer and the second metal layer are one of Cu, Ni, Sn, Ag, or Au.

Further, the first pin and the second pin are both located at the position of the active surface.

Further, the first metal layer and the second metal layer are exposed to the outside.

And further, the other side walls, which are not provided with the second metal layer, on the chip are plastically packaged by adopting a packaging material.

Compared with the prior art, the utility model, the beneficial effects are as follows: through electroplating a first metal layer on the back of the chip, electroplating a second metal layer on at least one side wall of the chip, connecting the first metal layer with the second metal layer, packaging the electroplated chip, leading out a first pin and a second pin, connecting the first pin with Bump metal bumps, connecting the second pin with the second metal layer, and in the same size of packaging body space, maximizing the space utilization rate, and adopting the wall-attaching type arrangement for the second metal layer, the waste of the space can be greatly reduced, thereby in the same size of packaging body space, packaging larger-size chips can be packaged. Otherwise, the same size chip adopts the utility model provides a packaging structure can dwindle the encapsulation size greatly.

In addition, the first metal layer and the second metal layer are exposed outside, so that the heat dissipation efficiency of the chip can be improved, and the service life of the chip is prolonged.

Drawings

Fig. 1 is a schematic structural diagram of a package proposed in the background art;

fig. 2 is a schematic structural diagram of the chip package structure of the present invention;

fig. 3 to 8 are process flow diagrams of the chip package structure of the present invention;

fig. 9 is a comparison diagram of the adherence processing and the non-adherence processing of the second metal layer in the chip package structure of the present invention.

Detailed Description

The present invention will now be described in connection with particular embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar function throughout.

The utility model discloses directional phrase mentioned, for example: upper, lower, left, right, front, rear, inner, outer, front, back, side, etc., are merely directions with reference to the drawings, and the embodiments described below by referring to the drawings and directional terms used are exemplary and are only used for explaining the present invention, and are not to be construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials that one of ordinary skill in the art would recognize for other processes and/or other materials to use.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package structure according to the present invention.

The chip packaging structure comprises a chip 10 with Bump metal bumps 11, wherein the surface of the chip 10 with the Bump metal bumps 11 is an active surface, the opposite surface is a back surface, a first metal layer 20 is electroplated on the back surface of the chip 10, a second metal layer 30 is electroplated on at least one side wall 10a of the chip 10, the first metal layer 20 is connected with the second metal layer 30, the electroplated chip 10 is subjected to plastic packaging to form a plastic packaging body 40, first pins a and second pins b are led out, the first pins a are connected with the Bump metal bumps 11, and the second pins b are connected with the second metal layer 30.

An isolation layer c is arranged between the second metal layer 30 and the side wall 10a, in another technical scheme, the isolation layer c may not be arranged, and the second metal layer 30 is directly arranged in a wall-attaching manner, preferably, the isolation layer c is made of a material with good heat conductivity and is made of a non-conductive material.

The first metal layer 20 and the second metal layer 30 are made of the same or different materials, the first metal layer 20 and the second metal layer 30 can be electroplated at the same time or electroplated at different time intervals, and when the materials are the same, electroplating can be directly and simultaneously carried out, so that the production efficiency is improved.

The first metal layer 20 and the second metal layer 30 are one of Cu, Ni, Sn, Ag, or Au.

The first pins a and the second pins b are located at the positions of the active surface, the first metal layer 20 and the second metal layer 30 are exposed outside, the heat dissipation performance of the chip 10 is improved, the other side walls 10a, which are not provided with the second metal layer 30, on the chip 10 are plastically packaged by using a packaging material, the sealing performance is improved, the chip 10 is protected, and the service life of the chip 10 is prolonged.

The process flow of the utility model is as follows:

please refer to fig. 3 to 9, wherein fig. 3 to 8 are process flow diagrams of the chip package structure of the present invention, and fig. 9 is a comparison diagram of the adherent treatment and the non-adherent treatment of the second metal layer in the chip package structure of the present invention.

The first step is as follows: as shown in fig. 3, the chip 10 with Bump metal bumps 11 is placed on a substrate d;

the second step is that: as shown in fig. 4, the chip 10 is subjected to plastic package to form a plastic package body 40;

the third step: as shown in fig. 5, the plastic package body 40 is ground or etched to expose the Bump metal Bump 11;

the fourth step: as shown in fig. 6, the substrate d is removed;

the fifth step: as shown in fig. 7, a first metal layer 20 is electroplated on the back surface of the chip 10, a second metal layer 30 is electroplated on at least one side wall 10a of the chip 10, and the first metal layer 20 is connected to the second metal layer 30, in this embodiment, the molding body 40 between the second metal layer 30 and the side wall 10a of the chip 10 is an isolation layer c, in other embodiments, the isolation layer c may be removed, and the second metal layer 30 is directly attached to the side wall 10a of the chip 10, so that the size of the packaged chip 10 is increased as much as possible in a space with the same size, as shown in fig. 9, it is obvious that in a package with the same size, the size of the chip where the second metal layer 30 is directly attached to the side wall 10a of the chip 10 is increased greatly.

And a sixth step: as shown in fig. 8, a first lead a and a second lead b made of copper are formed on the active surface of the chip 10 by electroplating, and are connected to the Bump metal Bump 11 and the second metal layer 30, respectively.

The utility model has the advantages as follows: through electroplating a first metal layer on the back of the chip, electroplating a second metal layer on at least one side wall of the chip, connecting the first metal layer with the second metal layer, packaging the electroplated chip, leading out a first pin a and a second pin b, connecting the first pin a with Bump metal bumps, connecting the second pin b with the second metal layer, in the same size of packaging body space, maximizing the space utilization rate, and arranging the second metal layer in a wall-attaching manner, so that the waste of the space can be greatly reduced, thereby packaging the chip with larger size in the same size of packaging body space. Otherwise, the same size chip adopts the utility model provides a packaging structure can dwindle the encapsulation size greatly.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. The chip packaging structure is characterized in that a chip (10) with Bump metal bumps (11) is provided, the surface, provided with the Bump metal bumps (11), on the chip (10) is an active surface, the opposite surface is a back surface, a first metal layer (20) is electroplated on the back surface of the chip (10), a second metal layer (30) is electroplated on at least one side wall (10a) of the chip (10), the first metal layer (20) is connected with the second metal layer (30), the electroplated chip (10) is subjected to plastic packaging to form a plastic packaging body (40), first pins (a) and second pins (b) are led out, the first pins (a) are connected with the Bump metal bumps (11), and the second pins (b) are connected with the second metal layer (30).

2. The chip packaging structure according to claim 1, wherein an isolation layer (c) is disposed between the second metal layer (30) and the sidewall (10 a).

3. The chip packaging structure according to claim 2, wherein the isolation layer (c) is directly a plastic package body (40) of the plastic package chip (10).

4. The chip packaging structure according to claim 1, wherein the first metal layer (20) and the second metal layer (30) are made of the same or different materials, and the first metal layer (20) and the second metal layer (30) can be plated at the same time or at different time intervals.

5. The chip package structure according to claim 1, wherein the first metal layer (20) and the second metal layer (30) are one of Cu, Ni, Sn, Ag, or Au.

6. The chip package structure according to claim 1, wherein the first pin (a) and the second pin (b) are both at a position of an active surface.

7. The chip packaging structure according to claim 1, wherein the first metal layer (20) and the second metal layer (30) are exposed.

8. The chip packaging structure according to claim 7, wherein other side walls (10a) of the chip (10) not provided with the second metal layer (30) are all plastically packaged by using a packaging material.