CN1855450A - High-heat loss rate semiconductor sealer and its production - Google Patents
High-heat loss rate semiconductor sealer and its production Download PDFInfo
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- CN1855450A CN1855450A CNA2005100662474A CN200510066247A CN1855450A CN 1855450 A CN1855450 A CN 1855450A CN A2005100662474 A CNA2005100662474 A CN A2005100662474A CN 200510066247 A CN200510066247 A CN 200510066247A CN 1855450 A CN1855450 A CN 1855450A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The package comprises: a baseboard; a semiconductor chip mounted on said baseboard and conductively connecting to said baseboard; a heat sink mounted on the semiconductor chip; a encapsulating colloid for use in encapsulating said chip and heat sink, exposing the top and sidewall of said heat sink, keeping flush with the side of said heat sink and having a size smaller than the one of baseboard. The invention can make the heat sink directly contact the semiconductor chip, while the chip can not be suffered pressure from an encapsulation module and a heat sink.
Description
Technical field
The invention relates to a kind of semiconductor package part and method for making thereof, particularly have fin to improve the semiconductor package part and the method for making thereof of radiating efficiency about a kind of.
Background technology
Along with requirement, dwindle integrated circuit (IC) and have high density and the semiconductor package part of multitube pin day by day becomes one of encapsulation main flow on the market such as ball grid array (BGA, Ball GridArray) is this to compactization of electronic product.Yet, because this semiconductor package part provides the electronic circuit (Electronic Circuits) and electronic component (ElectronicComponents) of higher density, so the heat that produces when operation is also higher; And this semiconductor package part is the packing colloid coating semiconductor chip with poor heat conduction, so often because of the not good performance that has influence on semiconductor chip of radiating efficiency.
In order to improve the radiating efficiency of semiconductor package part, in the technology of semiconductor package part, relevant technology is United States Patent (USP) the 5th for example to have a lot of people to propose to add fin (Heat Sink, Heat Slug, Heat Block), 216, No. 278, the 5th, 736, No. 785, the 5th, 977, No. 626, the 6th, 522, No. 428, the 6th, 528, No. 876, the 6th, 462, No. 405, the 6th, 429, No. 512, the 6th, 433, No. 420, the 6th, 444, No. 498 and the 6th, 458, cases such as No. 626.
See also Fig. 7, United States Patent (USP) the 5th, 977, No. 626 cases are a kind of semiconductor package parts with fin, this semiconductor package part is that fin 71 is placed on the substrate 73, and make the central spud 711 of this heat sink 71 touch semiconductor chip 70, and make these heat sink 71 end faces 710 expose outside packing colloid 74, the heat that produces when borrowing these fin 71 loss semiconductor chips 70 operations.
Yet there are some shortcomings in this semiconductor package part on making.At first, after this fin 71 and chip 70 are bonding, insert when carrying out the molding operation (Molding) of this packing colloid 74 in the die cavity of encapsulating mould, the end face 710 necessary contacts of this fin 71 are to the roof of die cavity, if the end face 710 of this fin 71 is failed the roof to die cavity of contact effectively, when forming the gap between the two, promptly having packing colloid 74 overflows, remain on the end face 710 of fin 71, in case be formed with excessive glue on the end face 710 of fin 71, except meeting influences the radiating efficiency of this fin 71, also can influence the outward appearance of manufactured goods, so the processing of must remove photoresist (Deflash); Yet the processing of removing photoresist is not only consuming time, increases packaging cost, and also can cause manufactured goods impaired.In addition, the strength of living the die cavity roof as if fin 71 contacts is excessive, then can make matter crisp chip 70 because of excessive pressure rhegma.
In addition, can just equal the degree of depth of mould die cavity to the distance of substrate 73 upper surfaces for the end face 710 that makes fin 71, fin 71 all must be controlled and be made with the thickness of the bonding and fin 71 of substrate 73 accurately with bonding, the chip 70 of chip 70, but the requirement on this precision, packaging cost is increased and the raising process complexity, so have big difficult in actual the enforcement.Other has United States Patent (USP) the 5th, 216, and 278 and 5,736, No. 785 etc. case also proposes similar semiconductor package part, but this semiconductor package part can face the problems referred to above too on processing procedure, so can reduce its industrial utilization.
Therefore, United States Patent (USP) the 6th, 522, No. 428, the 6th, 528, No. 876, the 6th, 462, No. 405, the 6th, 429, No. 512 and the 6th, 433, No. 420 etc. case provides the not semiconductor package part of contact semiconductor chip of a kind of fin.United States Patent (USP) the 6th as shown in Figure 8,462, No. 405 semiconductor package part with fin, it mainly is after semiconductor chip 80 is electrically connected to substrate 83 by bonding wire 82, connect at these chip 80 upper surfaces and to put for example lid 85 of defective chip, and on this substrate 83, connect the fin 81 that the top set face exposes outside packing colloid 84, and this fin 81 is formed with a recess 811, be contained in these fin 81 belows for chip 80 and do not contact, make matter crisp semiconductor chip 80 when preventing mold pressing because of excessive pressure rhegma with this fin 81.Yet, because of the direct contact chip 80 of fin 81, thereby can't rapid loss with the heat of its generation, cause the semiconductor chip reliability decrease, the demand that is unfavorable for the height integrated circuit, moreover, when it still can't solve molding operation, the excessive glue problem that fin 81 end faces produce, and fin 81 end faces must equal the die cavity degree of depth of mould etc., and precisely control and making require problem to the distance of substrate 83 upper surfaces.
In view of the above problems, United States Patent (USP) the 6th, 444, No. 498 and the 6th, 458, No. 626 etc. case then proposes a kind of technology that makes fin directly contact and can not cause the chip rhegma with semiconductor chip in molding operation.
See also Fig. 9 A to Fig. 9 C, it is a United States Patent (USP) the 6th, 444, a kind of semiconductor package part that No. 498 cases disclose, and fin can directly glue to be put on chip, can not produce crushing chip or excessive glue and be formed on problem on the fin exposed surface.This semiconductor package part is exposed at outside fin 91 on the surface in the atmosphere, form and the material layer 95 of the cementability difference of 91 of fin (for example polyimide resin make sheet adhesive), again this fin 91 is directly glued to place to connect and put on the chip 90 of full wafer substrate 93, then carry out the mold pressing processing procedure, coat this fin 91 and chip 90 fully with packing colloid 94, and packing colloid 94 is covered on the material layer 95 of fin 91 (shown in Fig. 9 A), like this, the mold pressing processing procedure uses the die cavity degree of depth of mould greater than the thickness sum of chip 90 with fin 91, so behind the mould matched moulds, mould can not touch fin 91, and chip 90 can pressurized and rhegma; Then, cut list (Singulation) program (shown in Fig. 9 B), and the packing colloid 94 of fin 91 tops is removed.Wherein, because of the cementability that is formed on 91 of material layer 95 on the fin 91 and fin cementability less than 94 of itself and packing colloids, after packing colloid 94 divested, this material layer 95 can stick to removes (shown in Fig. 9 C) thereupon on the packing colloid 94, so can not form excessive glue on this fin 91.
But the method for making of above-mentioned technology is only applicable to thin spherical grid array (TFBGA, Thin FineBGA) semiconductor package part, and in other words, promptly the size of packing colloid flushes with the size of substrate.Therefore, this method for making also is not suitable for the semiconductor package part such as PBGA, so limited its industrial utilization.
Therefore, how to overcome in the prior art, problem such as quality bad, industrial utilization low or not because of reliability that shortcoming causes such as semiconductor chip breakage, processing procedure difficulty and radiating efficiency be not good, effectively loose and remove semiconductor package part generation heat, become present urgency problem to be solved in fact.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof of high-cooling property, fin and chip can directly be engaged to improve radiating efficiency, and can in the mold pressing processing procedure, not cause the rhegma and the excessive glue problem of chip, and then improve the acceptance rate of manufactured goods.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof of high-cooling property, make fin and die bonding operation not need to carry out height control, can reduce packaging cost and improve acceptance rate.
Another purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof that improves the high-cooling property of industrial utilization.
For reaching above-mentioned and other purpose, the semiconductor package part of a kind of high-cooling property of the present invention and method for making thereof.The method for making of the semiconductor package part of this high-cooling property comprises: at least one semiconductor chip is connect put and be electrically connected on the chip carrier, and connect on this chip carrier and be equipped with the plate of taking in, be accommodated in to connect in this perforate for semiconductor chip and put on this chip carrier with corresponding chip position perforate; The surface is formed with the fin of interface layer, connects with its another relative surface and put on this semiconductor chip; Carry out molding operation, form and coat the packing colloid that this fin, semiconductor chip and part are taken in plate; Take in the plate tapping along this and cut, remove this and take in plate and cover packing colloid on it; And remove the packing colloid that remains on this fin interface layer.
This chip carrier can be BGA substrate or LGA substrate; Can bonding wire or flip chip electric connection between this semiconductor chip and this substrate.If this chip carrier is the BGA substrate, above-mentioned method for making also comprises: plant the ball operation, form a plurality of conductive components, make this semiconductor chip borrow itself and external device to electrically connect.In addition, this semiconductor package part can adopt a batch mode to make, and plants the ball operation and can be chosen in and carry out before or after cutting single job.
This size of taking in the plate perforate is roughly the packing colloid size after mold pressing and the cutting.The big I of this fin is taken in the size of plate perforate greater than this, will cut this fin edge simultaneously in processing procedure when this takes in plate perforate cutting, makes this fin side expose outside packing colloid; This fin can select to be provided with recess at edge, corresponding cut place, with this heat sink edge thickness attenuation, is convenient to carry out cutting operation; When cutting operation, the size of this residue packing colloid is equal to or less than this and takes in plate perforate size.This fin lower surface and packing colloid contact position are formed with bonding strengthening section, and this bonding strengthening section can be concaveconvex structure or become a kind of in the group through the structural group that roughening (Roughened), melanism (Black Oxide) are handled.
Cementability between this interface layer (as metal level) and fin can be greater than the cementability between itself and packing colloid, after packing colloid divested, this interface layer still remains on the fin, and because of the cementability between interface layer and packing colloid poor, packing colloid can not remain on the fin, so there is not the problem of the glue that overflows; Relatively, this cementability that is formed between interface layer on the fin (for example polyimide resin make sheet adhesive) and fin can be less than the cementability between itself and packing colloid, after packing colloid divested, this interface layer can stick on the packing colloid and remove thereupon, so also can not form excessive glue on this fin.
The semiconductor package part of this high-cooling property comprises: substrate; Semiconductor chip connects to put at this upper surface of base plate and with this substrate and electrically connects; Fin connects and puts on this semiconductor chip; And packing colloid, coat this semiconductor chip and heat sink, and expose outside the end face and the side of this fin, and the side of this packing colloid and this fin keeps flushing, and this packing colloid size is less than substrate size.
This substrate can be BGA substrate or LGA substrate, and its size is greater than this fin and this packing colloid size.This semiconductor chip can connect to put at this upper surface of base plate and with this substrate and electrically connect by wire bond or flip chip.Recess can be selected to be provided with in the edge of this fin, be convenient to carry out cutting operation, in addition this fin lower surface can select to be provided with bonding strengthening section with the packing colloid contact position, and this bonding strengthening section can be concaveconvex structure or become a kind of in the group through the structural group of roughening (Roughened), melanism (Black Oxide) processing.
This semiconductor package part also comprises the interface layer that is formed on this fin, and this interface layer is a metal level; This semiconductor package part also can comprise a plurality of conductive components, and this conductive component connects to be put at this base lower surface, makes this semiconductor chip borrow it to be connected with the external device conduction.This conductive component can for example be a soldered ball.
The present invention makes in the die cavity of encapsulating mould is included in this fin, and this die cavity can not touch this fin.Therefore, compared with prior art, the present invention can guarantee the direct contact semiconductor chip of fin, thereby can improve radiating efficiency, and can not make semiconductor chip be subjected to from the pressure of encapsulating mould or fin and rhegma.On this fin, also be covered with simultaneously interface layer, can not have the glue problem of overflowing for follow-up easy removal covering packing colloid thereon.Fin and die bonding operation do not need to carry out height control among the present invention, can reduce packaging cost and improve acceptance rate.The packing colloid of this semiconductor package part keeps flushing with the edge of fin in addition, and the size of this fin and packing colloid is less than this substrate.
In sum,, problems such as the not good and quality of the reliability that causes because of the chip rhegma in the prior art is bad can be solved, industrial utilization can be improved because that processing procedure of the present invention is implemented is simple.In addition, the present invention can be applicable to the semiconductor package part of different encapsulating structures, and therefore the non-TFBGA structure that is confined to can solve the restriction of prior art on industry is utilized, and has suitable manufacturing elasticity, further improves industrial utilization.
Description of drawings
Figure 1A to Fig. 1 G is the method for making schematic diagram of the semiconductor package part embodiment 1 of high-cooling property of the present invention;
Fig. 2 is the schematic diagram of the semiconductor package part embodiment 2 of high-cooling property of the present invention;
Fig. 3 is the schematic diagram of the semiconductor package part embodiment 3 of high-cooling property of the present invention;
Fig. 4 is the schematic diagram of the semiconductor package part embodiment 4 of high-cooling property of the present invention;
Fig. 5 is the schematic diagram of the semiconductor package part embodiment 5 of high-cooling property of the present invention;
Fig. 6 is the schematic diagram of the semiconductor package part embodiment 6 of high-cooling property of the present invention;
Fig. 7 is a United States Patent (USP) the 5th, 977, the semiconductor package part schematic diagram with fin of No. 626 case announcements;
Fig. 8 is a United States Patent (USP) the 6th, 462, the semiconductor package part schematic diagram with fin of No. 405 case announcements; And
Fig. 9 A to Fig. 9 C is a United States Patent (USP) the 6th, 444, the directly sticking semiconductor package part schematic diagram that places on the chip of Gong the fin of No. 498 case announcements.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention.
Figure 1A to Fig. 1 G is that the embodiment 1 according to the semiconductor package part of high-cooling property of the present invention and method for making thereof draws.Combine basic structure of the present invention only is described in a schematic way, therefore only show the formation relevant with the present invention, and shown formation is not, and number, shape and dimension scale when implementing with reality drawn, number, shape and dimension scale during actual enforcement is a kind of optionally design, and its formation arrangement form may be more complicated.
The method for producing semiconductor packaging part of high-cooling property of the present invention is: shown in Figure 1A, one chip carrier of substrate 11 (Chip Carrier) for example is provided, at least one semiconductor chip 15 connect put and be electrically connected on this substrate 11, and connect on this substrate 11 be equipped with have a corresponding chip position perforate 131 take in plate 13, semiconductor chip 15 is accommodated in this perforate 131, connects and put on this substrate 11.
This substrate 11 can for example be the BGA substrate.This takes in plate 13 can be sheet metal, the polyimides (PI that metallic copper material is made, Polyimide) film, Bismaleimide Triazine (BT, Bismaleimide triazine) substrate or other suitable material are made, take in plate 13 at this and be formed with at least one perforate (Cavity) 131, connect on the substrate of putting in this perforate 131 11 at least one semiconductor chip 15.In the present embodiment, the size of this perforate 131 approximately is the packaging part size after being shaped, and for example is S1.Then be to electrically connect between this semiconductor chip 15 and this substrate 11 with for example bonding wire 17.
It should be noted, can select on this substrate 11, to be provided with earlier this semiconductor chip 15, and with after these bonding wire 17 electric connections, again this is taken in plate 13 and be combined in this substrate 11, perhaps can select earlier after taking in plate 13 in conjunction with this on this substrate 11, and then this semiconductor chip 15 is set and with these bonding wire 17 electric connections in the corresponding perforate 131 of taking in plate 13 on this substrate 11.
Shown in Figure 1B, the surface is formed with the fin 3 of interface layer 31, connect with its another relative surface and put on this semiconductor chip 15.This fin 3 can for example be that copper, aluminium, copper alloy, aluminium alloy or the good material of other thermal conductivity are made.
In the present embodiment, this fin 3 is the structures that for example are T font section, and the size of this fin 3 for example is S2, and S2 is greater than S1, and promptly the size of this fin 3 is taken in the perforate 131 of plate 13 greater than this.This fin 3 has extended to form contact site 33 to these semiconductor chip 15 upper surfaces, puts on this semiconductor chip 15 for connecing, and makes this bonding wire 17 can not touch this fin 3 by this contact site 33 simultaneously.
This interface layer 31 can be gold-plated in advance earlier, the not good metal of cementability between chromium or other and packing colloid compound, also can paste the sticking film of making by polyimide resin at these fin 3 upper surfaces, perhaps be coated with coating of epoxy resin for example etc. at these fin 3 upper surfaces, the cementability that makes 3 of this this film or this coating etc. and this fin is less than the cementability between itself and potting compound, but easy removal remains in the potting compound on this interface layer 31 in successive process, does not have the glue problem of overflowing.
Shown in Fig. 1 C, this is combined with fin 3 inserts in the die cavity (not marking) of encapsulating mould with the substrate 11 of chip 15, and make between the roof of this die cavity and this fin 3 suitable distance is arranged, make the die cavity of this encapsulating mould be enough to this fin 3 is included, form this fin 3 of coating, substrate 11, semiconductor chip 15, bonding wire 17 and the local packing colloid 5 of taking in plate 13 by the potting compound that injects in this die cavity.Because the die cavity of this encapsulating mould does not touch this fin 3, this semiconductor chip 15 can not be subjected to the pressure from this encapsulating mould or this fin 3 behind matched moulds, has avoided the prior art chips that the problem of rhegma may take place.
Shown in Fig. 1 D and Fig. 1 E, take in plate 13 perforates 131 places along this and cut, remove this and take in plate 13 and cover packing colloid 5 on it.Can define cutting position 51 earlier, the distance that this cutting position is 51 is S3, and S3 can equal S1, make this cutting tool 100 pass this packing colloid 5, this fin 3 along this cutting position 51 respectively, and expose outside and take in plate 13, then, shown in Fig. 1 E, remove this and take in plate 13 and cover packing colloid 5 on it.
Shown in Fig. 1 F, remove the packing colloid 5 that remains on these fin 3 interface layers 31.The cementability that interface layer 31 on being formed on fin 3 (for example film of making for polyimide resin) and fin are 3 is during less than the cementability of 5 of itself and packing colloids, after packing colloid 5 divested, this interface layer 31 can stick on the packing colloid 5 and remove (shown in Fig. 1 F) thereupon, so also can not form excessive glue on this fin 3.The cementability that relatively also can utilize 3 of this interface layer 31 (for example Gold plated Layer) and fin is greater than the cementability of 5 of itself and packing colloids, after packing colloid 5 divested, this interface layer 31 still remains on the fin, but because of the cementability of 5 of interface layer 31 and packing colloids poor, packing colloid 5 can not remain in (shown in Fig. 1 F ') on the fin 3, so there is not the problem of the glue that overflows.
Shown in Fig. 1 G, when this substrate 11 is the BGA substrate, can plant the ball operation in these substrate 11 bottoms then, form a plurality of conductive components 6 as soldered ball, make this semiconductor chip 15 borrow it to be connected with the external device conduction, obtain the semiconductor package part of high-cooling property.Certainly, this semiconductor package part can a batch mode be made in a large number, and can plant the ball operation earlier and cut out the individual semiconductor package part along predetermined line of cut again, is not to exceed with described in the present embodiment.
See also Fig. 1 G, the present invention also discloses the semiconductor package part of high-cooling property, and this semiconductor package part comprises substrate 11, semiconductor chip 15, fin 3, packing colloid 5 and a plurality of conductive component 6.This substrate 11 has upper surface and with respect to the lower surface of this upper surface, and the size of this substrate 11 is greater than this fin 3 and this packing colloid 5, and can for example be the BGA substrate.This semiconductor chip 15 is bonding with this substrate 11 with for example adhesive (not marking), and electrically connects with this substrate 11 with for example bonding wire 17.This fin 3 is for example measured the structure of T font, and has the contact site 33 that extends and contact this semiconductor chip 15 to this semiconductor chip 15 upper surfaces.End face and side that this packing colloid 5 coats this semiconductor chip 15 and exposes outside this fin 3, and this packing colloid 5 keeps flushing with the side of this fin 3.This conductive component 6 connects the lower surface of putting at this substrate 11, makes this semiconductor chip 15 borrow it to be connected with the external device conduction.In the present embodiment, this conductive component 6 can be a soldered ball, but is not as limit.
Fig. 2 is the generalized section of high-cooling property method for producing semiconductor packaging part embodiment 2 of the present invention.Wherein, the assembly identical or approximate with embodiment 1 represent with identical or approximate element numbers, and be clearer understandable for the explanation that makes this case, omits the narration that exists together mutually in processing procedure and the structure.
As shown in Figure 2, its cutting position of definition extends to the direction of this semiconductor chip 15 along these perforate 131 edges of taking in plate 13 in the processing procedure of embodiment 2.
Fig. 3 is the generalized section of high-cooling property semiconductor package part embodiment 3 of the present invention.Wherein, same as the previously described embodiments or approximate assembly is represented with identical or approximate element numbers, and narration no longer in detail, for the feature that makes this case is clearer and more definite, difference only is described.
This recess 351 ' can select to be located at cutting position near in the foregoing description, make cutting tool only need the thin fin 3 of cutting thickness ', further improved cutting efficiency.
Embodiment 4
Fig. 4 is the generalized section of high-cooling property semiconductor package part embodiment 4 of the present invention.Wherein, same as the previously described embodiments or approximate assembly is represented with identical or approximate element numbers, and narration no longer in detail.
Embodiment 4 is that with embodiment 3 maximum differences the fin 3 among the embodiment 4 " is formed with bonding strengthening section 353 at its lower surface ".
In the present embodiment, this bonding strengthening section 353 " can to select for example be concaveconvex structure, it is " bonding with this packing colloid 5 well to make this fin 3.But will be appreciated that the present invention is not as limit, also can be by the cementability of 5 of " lower surface carries out improving this fin 3 such as roughening (Roughened), melanism (Black Oxide) or other equivalent process " and this packing colloids to this fin 3.
Fig. 5 is the generalized section of high-cooling property semiconductor package part embodiment 5 of the present invention.Wherein, same as the previously described embodiments or approximate assembly is to represent with identical or approximate element numbers, and narration no longer in detail.
It is to use wire bond formula substrate 11 that embodiment 5 is above-mentioned with the maximum difference of the foregoing description, 5 of embodiment be use chip upside-down mounting type (Flip Chip) substrate 11 '.
In the present embodiment, this substrate 11 ' upper surface be formed with a plurality of be the weld pad (Pads) 111 that array arranges ', for semiconductor chip 15 adopt flip chip by welding solder bump 113 ', with its active surface be electrically connected to this substrate 11 ' weld pad 111 ' on, and can directly connect and put on the non-active surface of this chip 15 for fin 3.
Embodiment 6
Fig. 6 is the generalized section of high-cooling property semiconductor package part embodiment 6 of the present invention.Wherein, same as the previously described embodiments or approximate assembly is represented with identical or approximate element numbers, and narration no longer in detail.
Embodiment 6 is that with the maximum difference of the foregoing description the said chip carrier is to use BGA substrate 11, on 6 of embodiment use LGA (LAND GRID ARRAY) substrate 11 " as the chip carrier of semiconductor chip 15; the non-active surface of semiconductor chip 15 connect put at this LGA substrate 11 ", and the active surface of this chip 15 is electrically connected to this LGA substrate 11 by bonding wire 17 ", is electrically connected to external device (ED) for follow-up via a plurality of these LGA substrates 11 " metallic contact 110 of bottom surface " that are arranged in.
Because the present invention can make fin directly contact with semiconductor chip and can not cause the chip rhegma in molding operation, so problem such as the reliability that can avoid prior art to cause because of shortcomings such as semiconductor chip breakage and radiating efficiency are not good is not good and quality is bad.Simultaneously, use the present invention and there is no difficulty on the processing procedure, and can be applicable on the dissimilar semiconductor package parts, so it is low or its industrial utilization is caused the shortcoming of restriction to solve industrial utilization that prior art causes.
Therefore, the present invention can provide a kind of semiconductor package part and method for making thereof of high-cooling property, has solved the various shortcoming of prior art, improves product reliability when improving radiating efficiency, and more can improve industrial utilization.
Claims (34)
1. the semiconductor package part of a high-cooling property is characterized in that, this semiconductor package part comprises:
Substrate;
Semiconductor chip connects to put at this upper surface of base plate and with this substrate and electrically connects;
Fin connects and puts on this semiconductor chip; And
Packing colloid coats this semiconductor chip and heat sink, and exposes outside the end face and the side of this fin, and the side of this packing colloid and this fin keeps flushing, and this packing colloid size is less than substrate size.
2. semiconductor package part as claimed in claim 1 is characterized in that, this substrate is ball grid array or LGA substrate.
3. semiconductor package part as claimed in claim 1 is characterized in that, this semiconductor chip is to be electrically connected to this substrate by the wire bond mode by many bonding wires.
4. semiconductor package part as claimed in claim 1 is characterized in that, this fin extends to form contact site to this semiconductor chip upper surface, puts on this semiconductor chip for connecing, and prevents that by this contact site this bonding wire from touching this fin simultaneously.
5. semiconductor package part as claimed in claim 1 is characterized in that, this semiconductor chip is to be electrically connected to this substrate with flip chip.
6. semiconductor package part as claimed in claim 1 is characterized in that, this fin lower surface edge is formed with recess.
7. semiconductor package part as claimed in claim 1 is characterized in that, this fin lower surface and packing colloid contact portion are provided with bonding strengthening section.
8. semiconductor package part as claimed in claim 7 is characterized in that, this bonding strengthening section is by concaveconvex structure or a kind of in the group that the structure that roughening, melanism are handled is formed.
9. semiconductor package part as claimed in claim 1 is characterized in that this packaging part also comprises a plurality of conductive components, and this conductive component connects to be put at this base lower surface, makes this semiconductor chip borrow it to be connected with the external device conduction.
10. semiconductor package part as claimed in claim 9 is characterized in that this conductive component is a soldered ball.
11. semiconductor package part as claimed in claim 1 is characterized in that, this packaging part also comprises the interface layer that is formed on this heat sink top surface.
12. semiconductor package part as claimed in claim 11 is characterized in that, this interface layer be and packing colloid between the not good metal of cementability.
13. semiconductor package part as claimed in claim 12 is characterized in that, the material of this interface layer is gold or chromium metal.
14. the method for making of the semiconductor package part of a high-cooling property is characterized in that, this method for making comprises:
At least one semiconductor chip connect put and be electrically connected on the chip carrier, and connect on this chip carrier and be equipped with the plate of taking in, be accommodated in to connect in this perforate for semiconductor chip and put on this chip carrier with corresponding chip position perforate;
The surface is formed with the fin of interface layer, connects with its another relative surface and put on this semiconductor chip;
Carry out molding operation, form and coat the packing colloid that this fin, semiconductor chip and part are taken in plate;
Take in the plate tapping along this and cut, remove this and take in plate and cover packing colloid on it; And
Remove the packing colloid that remains on this fin interface layer.
15. method for making as claimed in claim 14 is characterized in that, this method for making also is included in this chip carrier lower surface and forms a plurality of conductive components, makes this semiconductor chip borrow it to be connected with the external device conduction.
16. method for making as claimed in claim 14 is characterized in that, this semiconductor package part is to make in a batch mode, cuts simple form after finishing for encapsulation and becomes a plurality of encapsulation units.
17. method for making as claimed in claim 16 is characterized in that, this method for making is before cutting single job, forms a plurality of conductive components at the chip carrier lower surface.
18. method for making as claimed in claim 16 is characterized in that, this method for making is after cutting single job, forms a plurality of conductive components at the chip carrier lower surface.
19. method for making as claimed in claim 14 is characterized in that, this semiconductor chip is to be electrically connected to this substrate in the wire bond mode by many bonding wires.
20. method for making as claimed in claim 14 is characterized in that, this fin has extended to form contact site to this semiconductor chip upper surface, puts on this semiconductor chip for connecing, and prevents that by this contact site this bonding wire from touching this fin simultaneously.
21. method for making as claimed in claim 14 is characterized in that, this semiconductor chip is to be electrically connected to this substrate with flip chip.
22. method for making as claimed in claim 14 is characterized in that, this chip carrier is ball grid array or LGA substrate.
23. method for making as claimed in claim 14 is characterized in that, this size of taking in the plate perforate is roughly the size of the packing colloid after the shaping.
24. method for making as claimed in claim 14 is characterized in that, this heat sink sizes is taken in the plate bore size greater than this.
25. method for making as claimed in claim 14 is characterized in that, this fin lower surface and packing colloid contact portion are formed with bonding strengthening section.
26. method for making as claimed in claim 25 is characterized in that, this bonding strengthening section is to become a kind of in the group by concaveconvex structure or through the structural group that roughening, melanism are handled.
27. method for making as claimed in claim 14 is characterized in that, this fin lower surface edge is provided with recess, so that carry out cutting operation.
28. method for making as claimed in claim 14 is characterized in that, the packing colloid size after this cutting is taken in the plate bore size less than this.
29. method for making as claimed in claim 14 is characterized in that, the packing colloid size after this cutting equals this and takes in the plate bore size.
30. method for making as claimed in claim 14 is characterized in that, the cementability between this interface layer and fin is greater than the cementability between itself and packing colloid, and after the packing colloid on this interface layer was divested, this interface layer still remained on the fin.
31. method for making as claimed in claim 30 is characterized in that, the material of this interface layer is gold or chromium metal.
32. method for making as claimed in claim 14 is characterized in that, the cementability between this interface layer and fin is less than the cementability between itself and packing colloid, and after the packing colloid on this interface layer was divested, this interface layer can stick on the packing colloid and remove thereupon.
33. method for making as claimed in claim 32 is characterized in that, this interface layer is the film that polyimide resin is made.
34. method for making as claimed in claim 32 is characterized in that, this interface layer is the coating of epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100662474A CN1855450A (en) | 2005-04-25 | 2005-04-25 | High-heat loss rate semiconductor sealer and its production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100662474A CN1855450A (en) | 2005-04-25 | 2005-04-25 | High-heat loss rate semiconductor sealer and its production |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1855450A true CN1855450A (en) | 2006-11-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100662474A Pending CN1855450A (en) | 2005-04-25 | 2005-04-25 | High-heat loss rate semiconductor sealer and its production |
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| Country | Link |
|---|---|
| CN (1) | CN1855450A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980359A (en) * | 2010-09-07 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN102412219A (en) * | 2010-09-22 | 2012-04-11 | 星科金朋有限公司 | Integrated circuit packaging system with active surface heat removal and method of manufacture thereof |
| CN104064532A (en) * | 2014-06-25 | 2014-09-24 | 中国科学院微电子研究所 | Device package structure with heat radiating structure and manufacturing method thereof |
| CN106298549A (en) * | 2015-06-29 | 2017-01-04 | 台湾积体电路制造股份有限公司 | Flip-Chip Using |
| CN106298695A (en) * | 2015-06-05 | 2017-01-04 | 台达电子工业股份有限公司 | Encapsulation module, encapsulation module stacked structure and preparation method thereof |
| CN109390297A (en) * | 2017-08-08 | 2019-02-26 | 现代自动车株式会社 | Power module and power conversion system comprising the power module |
| US11289401B2 (en) | 2019-05-15 | 2022-03-29 | Powertech Technology Inc. | Semiconductor package |
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2005
- 2005-04-25 CN CNA2005100662474A patent/CN1855450A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980359A (en) * | 2010-09-07 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN102412219A (en) * | 2010-09-22 | 2012-04-11 | 星科金朋有限公司 | Integrated circuit packaging system with active surface heat removal and method of manufacture thereof |
| CN104064532A (en) * | 2014-06-25 | 2014-09-24 | 中国科学院微电子研究所 | Device package structure with heat radiating structure and manufacturing method thereof |
| CN106298695A (en) * | 2015-06-05 | 2017-01-04 | 台达电子工业股份有限公司 | Encapsulation module, encapsulation module stacked structure and preparation method thereof |
| CN106298695B (en) * | 2015-06-05 | 2019-05-10 | 台达电子工业股份有限公司 | Encapsulation module, encapsulation module stacked structure and preparation method thereof |
| CN106298549A (en) * | 2015-06-29 | 2017-01-04 | 台湾积体电路制造股份有限公司 | Flip-Chip Using |
| CN109390297A (en) * | 2017-08-08 | 2019-02-26 | 现代自动车株式会社 | Power module and power conversion system comprising the power module |
| US11289401B2 (en) | 2019-05-15 | 2022-03-29 | Powertech Technology Inc. | Semiconductor package |
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