CN102751204B - Fanout type wafer level chip packaging method - Google Patents
Fanout type wafer level chip packaging method Download PDFInfo
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- CN102751204B CN102751204B CN201210243958.4A CN201210243958A CN102751204B CN 102751204 B CN102751204 B CN 102751204B CN 201210243958 A CN201210243958 A CN 201210243958A CN 102751204 B CN102751204 B CN 102751204B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
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- Micromachines (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a fanout type wafer level chip packaging method, belonging to the field of semiconductor chip packaging technology. A fanout type wafer level chip packaging structure comprises a chip (1), a metal microstructure (2), a high-density wiring layer (4), a silicon cavity body (5), a bonding layer (6) and a solder ball salient point (7), wherein the metal microstructure (2) is formed on the chip (1) through sputtering, photoetching, electroplating and other techniques, the chip (1) is invertedly arranged on the high-density wiring layer (4), a depression silicon body (511) is formed on the silicon cavity (5) by using an optical mask, etching and other methods, the chip (1) is buckled in the silicon cavity (511) by the silicon cavity (5), the high-density wiring layer (4) and the silicon cavity body (5) are bonded by the bonding layer (6), and a packaging layer (52) and the bonding layer (6) are cured and formed through heating. The method is low in packaging cost, firm in supporting strength of the fanout structure, high in packaging yield, and applicable to packaging of the fanout type wafer level chips with thin structures.
Description
Technical field
The present invention relates to a kind of wafer level chip packaging method, belong to semiconductor die package technical field.
Background technology
In current semicon industry, Electronic Packaging has become an importance of industry development.The development of the encapsulation technology of decades, makes high density, undersized encapsulation requirement become the main flow direction of encapsulation.
Along with electronic product to thinner, gentlier, the development of higher pin density, more low-cost aspect, adopt single chips encapsulation technology cannot meet industry demand gradually, the Packaging Industry that appears as of a kind of new encapsulation technology---Wafer-Level Packaging Technology provides opportunity to low-cost package development.Simultaneously, restricting encapsulation technology is this working ability in tiny electrode pitch aspect of substrate technology to the another one major reason of high density future development, must pass through carrier, as the ceramic monolith in the organic substrate carrier in plastic base array package (PBGA) and ceramic tape ball grid array (CBGA), the amplification of pair array pitch completes encapsulation process.
Wafer level fan-out (Fanout) structure, the mode that it connects up by reconstruct disk and wafer level again, realizes the plastic packaging of chip fan-out structure, finally cuts into single packaging body.But still there is following deficiency in it:
1), chip outside overmolded plastic package material, plastic packaging material is epoxylite material, its low strength makes the support strength of fan-out (Fanout) structure inadequate, is difficult to application in thin encapsulation;
2), fan-out (Fanout) structure is because reconstruct wafer thermal coefficient of expansion is much larger compared with silicon chip in packaging technology, technical process warpage is larger, equipment is can working ability lower, yield loss is larger;
3), existing technique is to meet low thermal coefficient of expansion, encapsulating resin is comparatively expensive, is unfavorable for the cost degradation of product.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, the fan-out-type wafer level chip-packaging structure that a kind of packaging cost is low, the support strength of fan-out (Fanout) structure is high, encapsulation yield is high, be applicable to thin type structure is provided.
The object of the present invention is achieved like this: a kind of fan-out-type wafer level chip packaging method, and it comprises following technical process:
Step 1, preparation carrier disk;
Step 2, at the upper surface of carrier disk, cover dielectric layer, on described dielectric layer, form the litho pattern opening of design;
Step 3, the mode by plating, chemical plating or sputter realize metal electrode I, single or multiple lift wiring metal cabling and metal electrode II again at figure opening and the upper surface thereof of described dielectric layer;
Step 4, get the IC disk with chip electrode, on chip electrode, by techniques such as sputter, photoetching, plating, realize the metal dimpling point on metal column and metal column top, and complete metal micro structure array and arrange;
Step 5, by above-mentioned IC Wafer Thinning and cut into the chip of single;
Step 6, by said chip upside-down mounting in the metal electrode I of step 3, by backflow, form reliable connection;
Step 7, to completing the chip of upside-down mounting, with inserts, between metal micro structure and metal micro structure and the periphery of metal micro structure is filled, fill the space between full chip and high-density wiring layer, form the packaging body with chip;
Step 8, get silicon wafer, on silicon body, by methods such as optical mask, etchings, complete recessed silicon chamber, form the silicon cavity with silicon chamber;
Step 9, at the upper surface of above-mentioned silicon body, cover bonded layer, liquid envelope glue on the mid point of silicon chamber, forms and seals the bed of material;
Step 10, the packaging body with chip of step 7 is spun upside down to 180 degree and the above-mentioned silicon cavity bonding with silicon chamber, extruding encapsulating material and bonded layer, heating, makes encapsulating material and bonded layer solidified forming;
Step 11, the method by attenuate etching are removed carrier disk;
Step 12, in above-mentioned metal electrode II, plant ball and reflux, form solder bumps array;
Step 13, the disk of above-mentioned reconstruct is carried out to attenuate, cutting, form the wafer level fan-out chip thin encapsulation structure of single.
The vertical section in described silicon chamber is trapezoidal, rectangle or square.
Described dielectric layer is the resin with lithographic features.
Described metal electrode I, wiring metal cabling, metal electrode II are single or multiple lift metal again.
Described single or multiple lift metal is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.
Described metal dimpling point is tin/ashbury metal.
The material of described metal column is copper or nickel.
Described encapsulating material is liquid envelope glue.
Described bonded layer material is chip bonding glue.
The invention has the beneficial effects as follows:
Feature of the present invention is that the skin at chip is not only coated with encapsulating resin, and also has a silicon body with silicon chamber, chip buckles in the silicon chamber with encapsulating resin, scleroid silicon body firmly supports to fan-out (Fanout) structure one, is conducive to the propelling of the thin encapsulation in wafer level packaging.
Silicon body replaces most of encapsulating resin of original structure, only stays sub-fraction to be filled between chip and silicon body, has overcome the bad warpage that fan-out (Fanout) structure produces due to reconstruct wafer in packaging technology, has improved the yield of product.
Meanwhile, the silicon of low thermal coefficient of expansion replaces the major part of comparatively expensive encapsulating resin, is conducive to reduce production cost, is applicable to the growth requirement of modern industry.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of fan-out-type wafer level of the present invention chip-packaging structure.
Fig. 2～Figure 20 is a kind of fan-out-type wafer level of the present invention chip packaging method schematic diagram.
In figure:
IC wafer A 1
Chip 1
Chip body 11
Chip electrode 111
Metal micro structure 2
Metal column 21
Metal dimpling point 22
Inserts 3
High-density wiring layer 4
Dielectric layer 41
Figure opening 411
Wiring metal cabling 42 again
Metal electrode I 421
Metal electrode II 422
Silicon cavity 5
Silicon body 51
Silicon chamber 511
Seal the bed of material 52
Bonded layer 6
Solder bumps 7
Carrier disk 8.
Embodiment
Referring to Fig. 1, a kind of fan-out-type wafer level chip-packaging structure, it comprises chip 1, metal micro structure 2, inserts 3, high-density wiring layer 4, silicon cavity 5, bonded layer 6 and solder bumps 7.Described chip 1 comprises chip body 11, and the upper surface of described chip body 11 arranges several chip electrodes 111.Described high-density wiring layer 4 comprises dielectric layer 41 and wiring metal cabling 42 again, and the two ends of the described cabling of wiring metal again 42 arrange respectively metal electrode I 421 and metal electrode II 422.Described metal micro structure 2 comprises metal column 21 and the metal dimpling point 22 that is arranged on metal column 21 one end, and described metal column 21 other ends are connected with chip electrode 111.2 one-tenth array arrangements of described metal micro structure.The upper surface of described metal electrode I 421 is connected with metal dimpling point 22, and the lower surface of described metal electrode II 422 is connected with solder bumps 7, and described chip 1 passes through metal micro structure 2 upside-down mountings in the metal electrode I 421 of high-density wiring layer 4 upper surface.Described inserts 3 is arranged between metal micro structure 2 and metal micro structure 2 and the peripheral space of metal micro structure 2, is full of the space between chip 1 and high-density wiring layer 4.
Described silicon cavity 5 comprises silicon body 51, and described silicon body 51 is provided with silicon chamber 511.Described silicon cavity 5 buckles chip 1 in silicon chamber 511, and described high-density wiring layer 4 is with silicon cavity 5 by bonded layer 6 bondings, and described bonded layer 6 is bonding glue.
Between described chip 1 and silicon chamber 511, arrange and seal the bed of material 52.
A fan-out-type wafer level chip packaging method, it comprises following technical process:
Step 1, preparation carrier disk 8.As Fig. 2.
Step 2, at the upper surface of carrier disk 8, cover dielectric layer 41, described dielectric layer 41, for having the resin of lithographic features, forms the litho pattern opening 411 of design on described dielectric layer 41.As Fig. 3.
Step 3, the mode by plating, chemical plating or sputter realize metal electrode I 221, single or multiple lift wiring metal cabling 42 and metal electrode II 422 again at figure opening 411 and the upper surface thereof of described dielectric layer 41, described metal electrode I 221, wiring metal cabling 42, metal electrode II 422 are single or multiple lift metal again, and described single or multiple lift metal is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.As Fig. 4.
Step 4, get the IC wafer A 1 with chip electrode 111, on chip electrode 111, by techniques such as sputter, photoetching, plating, realize the metal dimpling point 22 on metal column 21 and metal column 21 tops, and complete metal micro structure 2 array arrangements.The material of described metal column 21 is copper or nickel, and described metal dimpling point 22 is tin/ashbury metal.As Fig. 5, Fig. 6, Fig. 7.
Step 5, by above-mentioned IC wafer A 1 attenuate and cut into the chip 1 of single.As Fig. 8, Fig. 9.
Step 6, by said chip 1 upside-down mounting in the metal electrode I 221 of step 3, by backflow, form reliable connection.As Figure 10.
Step 7, to completing between 3 pairs of metal micro structures 2 of chip 1 use inserts of upside-down mounting and metal micro structure 2 and fill the periphery of metal micro structure 2, fill the space between full chip 1 and high-density wiring layer 4, form the packaging body with chip 1.As Figure 11.
Step 8, get silicon wafer, on silicon body 51, by methods such as optical mask, etchings, complete recessed silicon chamber 511, the vertical section in described silicon chamber 511 is trapezoidal, rectangle or square, forms the silicon cavity 5 with silicon chamber 511.As Figure 12, Figure 13.
Step 9, at the upper surface of above-mentioned silicon body 51, cover bonded layer 6, liquid envelope glue on 511 mid points of silicon chamber, forms and seals the bed of material 52.As Figure 14.
Step 10, the packaging body with chip 1 of step 7 is spun upside down to 180 degree and above-mentioned silicon cavity 5 bondings with silicon chamber 511, the bed of material 52 and bonded layer 6 are sealed in extruding, and heating, makes to seal the bed of material 52 and bonded layer 6 solidified formings.As Figure 15.
Step 11, the method by attenuate etching are removed carrier disk 8.As Figure 16.
Step 12, in above-mentioned metal electrode II 422, plant ball and reflux, form solder bumps 7 arrays.As Figure 17.
Step 13, the disk of above-mentioned reconstruct is carried out to attenuate, cutting, form the fan-out-type wafer level chip-packaging structure of single.As Figure 18, Figure 19, Figure 20.
Claims (9)
1. a fan-out-type wafer level chip packaging method, is characterized in that described method comprises following technical process:
Step 1, preparation carrier disk (8);
Step 2, at the upper surface of carrier disk (8), cover dielectric layer (41), at the upper litho pattern opening (411) that forms design of described dielectric layer (41);
Step 3, the mode by plating, chemical plating or sputter realize metal electrode I (421), single or multiple lift wiring metal cabling (42) and metal electrode II (422) again at figure opening (411) and the upper surface thereof of described dielectric layer (41);
Step 4, get the IC disk (A1) with chip electrode (111), at chip electrode (111), above by techniques such as sputter, photoetching, plating, realize the metal dimpling point (22) on metal column (21) and metal column (21) top, and complete metal micro structure (2) array arrangement;
Step 5, by above-mentioned IC disk (A1) attenuate and cut into the chip (1) of single;
Step 6, said chip (1) upside-down mounting is upper in the metal electrode I (421) of step 3, forms reliable connection by backflow;
Step 7, to completing the chip (1) of upside-down mounting, with inserts (3), between metal micro structure (2) and metal micro structure (2) and the periphery of metal micro structure (2) is filled, fill the space between full chip (1) and high-density wiring layer (4), form the packaging body with chip (1);
Step 8, get silicon wafer, complete recessed silicon chamber (511) silicon body (51) is upper with methods such as optical mask, etchings, formation is with the silicon cavity (5) of silicon chamber (511);
Step 9, at the upper surface of above-mentioned silicon body (51), cover bonded layer (6), liquid envelope glue on the mid point of silicon chamber (511), forms and seals the bed of material (52);
Step 10, the packaging body with chip (1) of step 7 is spun upside down to 180 degree and above-mentioned silicon cavity (5) bonding with silicon chamber (511), the bed of material (52) and bonded layer (6) are sealed in extruding, heating, makes to seal the bed of material (52) and bonded layer (6) solidified forming;
Step 11, the method by attenuate etching are removed carrier disk (8);
Step 12, in above-mentioned metal electrode II (422), plant ball and reflux, form solder bumps (7) array;
Step 13, the disk of above-mentioned reconstruct is carried out to attenuate, cutting, form the fan-out-type wafer level chip-packaging structure of single.
2. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: the vertical section in described silicon chamber (511) is trapezoidal, rectangle or square.
3. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: described dielectric layer (41) is for having the resin of lithographic features.
4. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: described metal electrode I (421), wiring metal cabling (42), metal electrode II (422) are single or multiple lift metal again.
5. a kind of fan-out-type wafer level chip packaging method according to claim 4, is characterized in that: described single or multiple lift metal is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.
6. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: described metal dimpling point (22) is tin or ashbury metal.
7. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: the material of described metal column (21) is copper or copper/nickel clad.
8. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: described in to seal the bed of material (52) be liquid envelope glue.
9. a kind of fan-out-type wafer level chip packaging method according to claim 1, is characterized in that: described bonded layer (6) material is chip bonding glue.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210243958.4A CN102751204B (en) | 2012-07-16 | 2012-07-16 | Fanout type wafer level chip packaging method |
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| CN201210243958.4A CN102751204B (en) | 2012-07-16 | 2012-07-16 | Fanout type wafer level chip packaging method |
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| CN102751204A CN102751204A (en) | 2012-10-24 |
| CN102751204B true CN102751204B (en) | 2014-10-15 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103354224B (en) * | 2013-05-29 | 2016-04-13 | 南通富士通微电子股份有限公司 | Semiconductor device fan-out flip chip packaging structure |
| CN104037133B (en) * | 2014-06-26 | 2017-01-11 | 江阴长电先进封装有限公司 | Fan-out packaging method and packaging structure of wafer-level chip |
| CN106098664A (en) * | 2016-06-12 | 2016-11-09 | 华天科技（昆山）电子有限公司 | A kind of embedded type semiconductor chip fan-out package structure and preparation method thereof |
| CN106373939B (en) * | 2016-11-18 | 2019-04-19 | 江阴长电先进封装有限公司 | A kind of structure and its packaging method of package substrate |
| US20180374717A1 (en) * | 2017-06-23 | 2018-12-27 | Powertech Technology Inc. | Semiconductor package and method of forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1352804A (en) * | 1999-05-18 | 2002-06-05 | 阿梅拉西亚国际技术公司 | High-density electronic package and method for making same |
| CN101604638A (en) * | 2009-06-26 | 2009-12-16 | 江阴长电先进封装有限公司 | Wafer level fan-out chip packaging method |
| CN101976662A (en) * | 2010-09-27 | 2011-02-16 | 清华大学 | Output-end fan-out type flip-chip packaging structure without baseplate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04314337A (en) * | 1991-04-12 | 1992-11-05 | Fuji Electric Co Ltd | Semiconductor device and its manufacture |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1352804A (en) * | 1999-05-18 | 2002-06-05 | 阿梅拉西亚国际技术公司 | High-density electronic package and method for making same |
| CN101604638A (en) * | 2009-06-26 | 2009-12-16 | 江阴长电先进封装有限公司 | Wafer level fan-out chip packaging method |
| CN101976662A (en) * | 2010-09-27 | 2011-02-16 | 清华大学 | Output-end fan-out type flip-chip packaging structure without baseplate |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平4-314337A 1992.11.05 |
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