CN102751204A - Fanout type wafer level chip packaging method - Google Patents

Fanout type wafer level chip packaging method Download PDF

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Publication number
CN102751204A
CN102751204A CN2012102439584A CN201210243958A CN102751204A CN 102751204 A CN102751204 A CN 102751204A CN 2012102439584 A CN2012102439584 A CN 2012102439584A CN 201210243958 A CN201210243958 A CN 201210243958A CN 102751204 A CN102751204 A CN 102751204A
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China
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metal
chip
wafer level
silicon
type wafer
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CN2012102439584A
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Chinese (zh)
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CN102751204B (en
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张黎
陈栋
赖志明
陈锦辉
徐虹
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

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  • Micromachines (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to a fanout type wafer level chip packaging method, belonging to the field of semiconductor chip packaging technology. A fanout type wafer level chip packaging structure comprises a chip (1), a metal microstructure (2), a high-density wiring layer (4), a silicon cavity body (5), a bonding layer (6) and a solder ball salient point (7), wherein the metal microstructure (2) is formed on the chip (1) through sputtering, photoetching, electroplating and other techniques, the chip (1) is invertedly arranged on the high-density wiring layer (4), a depression silicon body (511) is formed on the silicon cavity (5) by using an optical mask, etching and other methods, the chip (1) is buckled in the silicon cavity (511) by the silicon cavity (5), the high-density wiring layer (4) and the silicon cavity body (5) are bonded by the bonding layer (6), and a packaging layer (52) and the bonding layer (6) are cured and formed through heating. The method is low in packaging cost, firm in supporting strength of the fanout structure, high in packaging yield, and applicable to packaging of the fanout type wafer level chips with thin structures.

Description

A kind of fan-out type wafer level chip packaging method
Technical field
The present invention relates to a kind of wafer level chip packaging method, belong to the semiconductor die package technical field.
Background technology
In current semicon industry, Electronic Packaging has become an importance of industry development.The Development of Packaging Technology of decades makes high density, undersized encapsulation requirement become the main flow direction of encapsulation.
Along with electronic product to thinner, gentlier, higher pin density, the development of more low-cost aspect; Adopt single chips encapsulation technology can't satisfy industry demand gradually, the Packaging Industry that appears as of a kind of new encapsulation technology---Wafer-Level Packaging Technology provides opportunity to the low-cost package development.Simultaneously; Restricting the another one major reason that encapsulation technology develops to the high density direction is this working ability in tiny electrode pitch aspect of substrate technology; Must pass through carrier; Like the ceramic monolith in organic substrate carrier in the plastic base array package (PBGA) and the ceramic tape ball grid array (CBGA), encapsulation process is accomplished in the amplification of array pitch.
Wafer level fan-out (Fanout) structure, the mode that it connects up through reconstruct disk and wafer level again, the plastic packaging of realization chip fan-out structure finally cuts into single packaging body.But still there is following deficiency in it:
1), chip outside overmolded plastic package material, plastic packaging material is the epoxylite material, its intensity is on the low side, makes the support strength of fan-out (Fanout) structure not enough, in slim encapsulation, is difficult to use;
2), fan-out (Fanout) structure in packaging technology since reconstruct wafer thermal coefficient of expansion a lot of greatly than silicon chip, the technical process warpage is bigger, but the equipment working ability is lower, yield loss is bigger;
3), existing technology is to satisfy low thermal coefficient of expansion, encapsulating resin is comparatively expensive, is unfavorable for the cost degradation of product.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, the fan-out type wafer level chip-packaging structure that a kind of packaging cost is low, the support strength of fan-out (Fanout) structure high, packaging yield is high, be applicable to thin type structure is provided.
The objective of the invention is to realize like this: a kind of fan-out type wafer level chip packaging method, it comprises following technical process:
Step 1, preparation carrier disk;
Step 2, cover dielectric layer, on said dielectric layer, form the litho pattern opening of design at the upper surface of carrier disk;
Step 3, the mode through plating, chemical plating or sputter realize metal electrode I, single or multiple lift wiring metal cabling and metal electrode II again at the figure opening and the upper surface thereof of said dielectric layer;
Step 4, get the IC disk that has chip electrode, on chip electrode, realize the metal dimpling point on metal column and metal column top, and accomplish metal micro structure array and arrange through technologies such as sputter, photoetching, plating;
Step 5, with above-mentioned IC disk attenuate and cut into single chip;
Step 6, with the said chip upside-down mounting on the metal electrode I of step 3, through reflux forming reliable the connection;
Step 7, the chip of accomplishing upside-down mounting is filled between metal micro structure and the metal micro structure and the periphery of metal micro structure with inserts, fill the space between full chip and the high-density wiring layer, form the packaging body that has chip;
Step 8, get silicon wafer, on silicon body, accomplish recessed silicon chamber, form the silicon cavity that has the silicon chamber with methods such as optical mask, etchings;
Step 9, cover bonded layer at the upper surface of above-mentioned silicon body, liquid envelope glue on the mid point of silicon chamber forms and seals the bed of material;
Step 10, the packaging body that has chip of step 7 is spun upside down 180 degree and the above-mentioned silicon cavity bondings that have the silicon chamber, material and bonded layer are sealed in extruding, and heating makes and seals material and bonded layer solidified forming;
Step 11, the method through the attenuate etching are removed the carrier disk;
Step 12, on above-mentioned metal electrode II, plant ball and reflux, form the solder bumps array;
Step 13, the disk of above-mentioned reconstruct is carried out attenuate, cutting, form single the slim encapsulating structure of wafer level fan-out chip.
The vertical section in said silicon chamber is trapezoidal, rectangle or square.
Said dielectric layer is the resin with lithographic features.
Said metal electrode I, wiring metal cabling, metal electrode II are the single or multiple lift metal again.
Said single or multiple lift metal is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.
Said metal dimpling point is tin/ashbury metal.
The material of said metal column is copper or nickel.
The said material of sealing is liquid envelope glue.
Said bonded layer material is a chip bonding glue.
The invention has the beneficial effects as follows:
Characteristics of the present invention are that the skin at chip not only is coated with encapsulating resin; And also have one have a silicon chamber silicon body; Chip buckles in having the silicon chamber of encapsulating resin; Scleroid silicon body gives fan-out (Fanout) structure one firm support, helps the propelling of the slim encapsulation in the wafer level packaging.
Silicon body replaces most of encapsulating resin of original structure, only stays sub-fraction to be filled between chip and the silicon body, has overcome the bad warpage that fan-out (Fanout) structure produces owing to the reconstruct wafer in packaging technology, has improved the yield of product.
Simultaneously, the silicon of low thermal coefficient of expansion replaces the major part of comparatively expensive encapsulating resin, helps reducing the production cost, is fit to the growth requirement of modern industry.
Description of drawings
Fig. 1 is the sketch map of a kind of fan-out type of the present invention wafer level chip-packaging structure.
Fig. 2～Figure 20 is a kind of fan-out type of the present invention wafer level chip packaging method sketch map.
Among the figure:
IC wafer A 1
Chip 1
Chip body 11
Chip electrode 111
Metal micro structure 2
Metal column 21
Metal dimpling point 22
Inserts 3
High-density wiring layer 4
Dielectric layer 41
Figure opening 411
The wiring metal cabling 42 again
Metal electrode I 421
Metal electrode II 422
Silicon cavity 5
Silicon body 51
Silicon chamber 511
Seal the bed of material 52
Bonded layer 6
Solder bumps 7
Carrier disk 8.
Embodiment
Referring to Fig. 1, a kind of fan-out type wafer level chip-packaging structure, it comprises chip 1, metal micro structure 2, inserts 3, high-density wiring layer 4, silicon cavity 5, bonded layer 6 and solder bumps 7.Said chip 1 comprises chip body 11, and the upper surface of said chip body 11 is provided with several chip electrodes 111.Said high-density wiring layer 4 comprises dielectric layer 41 and wiring metal cabling 42 again, and the two ends of the said cabling of wiring metal again 42 are provided with metal electrode I 421 and metal electrode II 422 respectively.Said metal micro structure 2 comprises metal column 21 and the metal dimpling point 22 that is arranged on metal column 21 1 ends, and said metal column 21 other ends are connected with chip electrode 111.2 one-tenth array arrangements of said metal micro structure.The upper surface of said metal electrode I 421 is connected with metal dimpling point 22, and the lower surface of said metal electrode II 422 is connected with solder bumps 7, and said chip 1 passes through metal micro structure 2 upside-down mountings on the metal electrode I 421 of high-density wiring layer 4 upper surface.Said inserts 3 is arranged between metal micro structure 2 and the metal micro structure 2 and the peripheral space of metal micro structure 2, is full of the space between chip 1 and the high-density wiring layer 4.
Said silicon cavity 5 comprises silicon body 51, and said silicon body 51 is provided with silicon chamber 511.Said silicon cavity 5 buckles chip 1 in silicon chamber 511, and said high-density wiring layer 4 passes through bonded layer 6 bondings with silicon cavity 5, and said bonded layer 6 is a bonding glue.
Be provided with between said chip 1 and the silicon chamber 511 and seal the bed of material 52.
A kind of fan-out type wafer level chip packaging method, it comprises following technical process:
Step 1, preparation carrier disk 8.Like Fig. 2.
Step 2, cover dielectric layer 41 at the upper surface of carrier disk 8, said dielectric layer 41 forms the litho pattern opening 411 of design for having the resin of lithographic features on said dielectric layer 41.Like Fig. 3.
Step 3, the mode through plating, chemical plating or sputter realize metal electrode I 221, single or multiple lift wiring metal cabling 42 and metal electrode II 422 again at the figure opening 411 and the upper surface thereof of said dielectric layer 41; Said metal electrode I 221, wiring metal cabling 42, metal electrode II 422 are the single or multiple lift metal again, and said single or multiple lift metal is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.Like Fig. 4.
Step 4, get the IC wafer A 1 that has chip electrode 111, on chip electrode 111, realize the metal dimpling point 22 on metal column 21 and metal column 21 tops through technologies such as sputter, photoetching, plating, and completion metal micro structure 2 array arrangements.The material of said metal column 21 is copper or nickel, and said metal dimpling point 22 is tin/ashbury metal.Like Fig. 5, Fig. 6, Fig. 7.
Step 5, with above-mentioned IC wafer A 1 attenuate and cut into single chip 1.Like Fig. 8, Fig. 9.
Step 6, with said chip 1 upside-down mounting on the metal electrode I 221 of step 3, through reflux forming reliable the connection.Like Figure 10.
Step 7, between the 3 pairs of metal micro structures 2 of chip 1 usefulness inserts of accomplishing upside-down mounting and the metal micro structure 2 and periphery of metal micro structure 2 is filled, fill the space between full chip 1 and the high-density wiring layer 4, formation has the packaging body of chip 1.Like Figure 11.
Step 8, get silicon wafer, on silicon body 51, accomplish recessed silicon chamber 511 with methods such as optical mask, etchings, the vertical section in said silicon chamber 511 is trapezoidal, rectangle or square, forms the silicon cavity 5 that has silicon chamber 511.Like Figure 12, Figure 13.
Step 9, cover bonded layer 6 at the upper surface of above-mentioned silicon body 51, liquid envelope glue on 511 mid points of silicon chamber forms and seals the bed of material 52.Like Figure 14.
Step 10, the packaging body that has chip 1 of step 7 is spun upside down 180 degree and above-mentioned silicon cavity 5 bondings that have silicon chamber 511, the bed of material 52 and bonded layer 6 are sealed in extruding, and heating makes and seals the bed of material 52 and bonded layer 6 solidified formings.Like Figure 15.
Step 11, the method through the attenuate etching are removed carrier disk 8.Like Figure 16.
Step 12, on above-mentioned metal electrode II 422, plant ball and reflux, form solder bumps 7 arrays.Like Figure 17.
Step 13, the disk of above-mentioned reconstruct is carried out attenuate, cutting, form single fan-out type wafer level chip-packaging structure.Like Figure 18, Figure 19, Figure 20.

Claims (9)

1. fan-out type wafer level chip packaging method is characterized in that said method comprises following technical process:
Step 1, preparation carrier disk (8);
Step 2, cover dielectric layer (41), go up the litho pattern opening (411) that forms design at said dielectric layer (41) at the upper surface of carrier disk (8);
Step 3, the mode through plating, chemical plating or sputter realize metal electrode I (421), single or multiple lift wiring metal cabling (42) and metal electrode II (422) again at the figure opening (411) and the upper surface thereof of said dielectric layer (41);
Step 4, get the IC disk (A1) that has chip electrode (111); Go up the metal dimpling point (22) of realizing metal column (21) and metal column (21) top through technologies such as sputter, photoetching, plating at chip electrode (111), and accomplish metal micro structure (2) array arrangement;
Step 5, with above-mentioned IC disk (A1) attenuate and cut into single chip (1);
Step 6, with said chip (1) upside-down mounting on the metal electrode I (421) of step 3, through reflux forming reliable the connection;
Step 7, the chip (1) of accomplishing upside-down mounting is filled between metal micro structure (2) and the metal micro structure (2) and the periphery of metal micro structure (2) with inserts (3); Fill the space between full chip (1) and the high-density wiring layer (4), form the packaging body that has chip (1);
Step 8, get silicon wafer, go up with methods such as optical mask, etchings at silicon body (51) and accomplish recessed silicon chamber (511), formation has the silicon cavity (5) in silicon chamber (511);
Step 9, cover bonded layer (6) at the upper surface of above-mentioned silicon body (51), liquid envelope glue on the mid point of silicon chamber (511) forms and seals the bed of material (52);
Step 10, the packaging body that has chip (1) of step 7 is spun upside down 180 degree and above-mentioned silicon cavity (5) bondings that have silicon chamber (511); The bed of material (52) and bonded layer (6) are sealed in extruding; Heating makes and seals the bed of material (52) and bonded layer (6) solidified forming;
Step 11, the method through the attenuate etching are removed carrier disk (8);
Step 12, on above-mentioned metal electrode II (422), plant ball and reflux, form solder bumps (7) array;
Step 13, the disk of above-mentioned reconstruct is carried out attenuate, cutting, form single fan-out type wafer level chip-packaging structure.
2. a kind of fan-out type wafer level chip packaging method according to claim 1 is characterized in that: the vertical section in said silicon chamber (511) is trapezoidal, rectangle or square.
3. a kind of fan-out type wafer level chip packaging method according to claim 1 is characterized in that: said dielectric layer (41) is for having the resin of lithographic features.
4. a kind of fan-out type wafer level chip packaging method according to claim 1 is characterized in that: said metal electrode I (421), wiring metal cabling (42), metal electrode II (422) are the single or multiple lift metal again.
5. a kind of fan-out type wafer level chip packaging method according to claim 4, it is characterized in that: said single or multiple lift metal is metallic copper, titanium/copper, titanium tungsten/copper, aluminium/nickel/gold or aluminium/nickel/palladium/gold.
6. a kind of fan-out type wafer level chip packaging method according to claim 1, it is characterized in that: said metal dimpling point (22) is tin or ashbury metal.
7. a kind of fan-out type wafer level chip packaging method according to claim 1, it is characterized in that: the material of said metal column (21) is copper or copper/nickel clad.
8. a kind of fan-out type wafer level chip packaging method according to claim 1 is characterized in that: the said bed of material (52) of sealing is a liquid envelope glue.
9. a kind of fan-out type wafer level chip packaging method according to claim 1, it is characterized in that: said bonded layer (6) material is a chip bonding glue.
CN201210243958.4A 2012-07-16 2012-07-16 Fanout type wafer level chip packaging method Active CN102751204B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103354224A (en) * 2013-05-29 2013-10-16 南通富士通微电子股份有限公司 Semiconductor device fan-out flip-chip packaging structure
CN106098664A (en) * 2016-06-12 2016-11-09 华天科技（昆山）电子有限公司 A kind of embedded type semiconductor chip fan-out package structure and preparation method thereof
CN104037133B (en) * 2014-06-26 2017-01-11 江阴长电先进封装有限公司 Fan-out packaging method and packaging structure of wafer-level chip
CN106373939A (en) * 2016-11-18 2017-02-01 江阴长电先进封装有限公司 Structure of package substrate and packaging method thereof
CN109119344A (en) * 2017-06-23 2019-01-01 力成科技股份有限公司 The method of manufacturing technology of semiconductor packages and semiconductor packages

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Publication number Priority date Publication date Assignee Title
JPH04314337A (en) * 1991-04-12 1992-11-05 Fuji Electric Co Ltd Semiconductor device and its manufacture
CN1352804A (en) * 1999-05-18 2002-06-05 阿梅拉西亚国际技术公司 High-density electronic package and method for making same
CN101604638A (en) * 2009-06-26 2009-12-16 江阴长电先进封装有限公司 Wafer level fan-out chip packaging method
CN101976662A (en) * 2010-09-27 2011-02-16 清华大学 Output-end fan-out type flip-chip packaging structure without baseplate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04314337A (en) * 1991-04-12 1992-11-05 Fuji Electric Co Ltd Semiconductor device and its manufacture
CN1352804A (en) * 1999-05-18 2002-06-05 阿梅拉西亚国际技术公司 High-density electronic package and method for making same
CN101604638A (en) * 2009-06-26 2009-12-16 江阴长电先进封装有限公司 Wafer level fan-out chip packaging method
CN101976662A (en) * 2010-09-27 2011-02-16 清华大学 Output-end fan-out type flip-chip packaging structure without baseplate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103354224A (en) * 2013-05-29 2013-10-16 南通富士通微电子股份有限公司 Semiconductor device fan-out flip-chip packaging structure
CN103354224B (en) * 2013-05-29 2016-04-13 南通富士通微电子股份有限公司 Semiconductor device fan-out flip chip packaging structure
CN104037133B (en) * 2014-06-26 2017-01-11 江阴长电先进封装有限公司 Fan-out packaging method and packaging structure of wafer-level chip
CN106098664A (en) * 2016-06-12 2016-11-09 华天科技（昆山）电子有限公司 A kind of embedded type semiconductor chip fan-out package structure and preparation method thereof
CN106373939A (en) * 2016-11-18 2017-02-01 江阴长电先进封装有限公司 Structure of package substrate and packaging method thereof
CN106373939B (en) * 2016-11-18 2019-04-19 江阴长电先进封装有限公司 A kind of structure and its packaging method of package substrate
CN109119344A (en) * 2017-06-23 2019-01-01 力成科技股份有限公司 The method of manufacturing technology of semiconductor packages and semiconductor packages

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