CN100362639C - Semiconductor packer and production for godown chip - Google Patents
Semiconductor packer and production for godown chip Download PDFInfo
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- CN100362639C CN100362639C CNB2005100076177A CN200510007617A CN100362639C CN 100362639 C CN100362639 C CN 100362639C CN B2005100076177 A CNB2005100076177 A CN B2005100076177A CN 200510007617 A CN200510007617 A CN 200510007617A CN 100362639 C CN100362639 C CN 100362639C
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor packer and a manufacturing method thereof for godown chips. The semiconductor packer comprises a chip carrier, a first chip, heat radiation sheets, a second chip and a pack colloid, wherein the first chip is electrically connected to the chip carrier; a plurality of through openings are formed on the heat radiation sheets which are connected to the first chip and contacted with the chip carrier. The second chip which is arranged on the heat radiation sheets is electrically connected to the chip carrier by conductor wires; the conductor wires pass through the through openings of the heat radiation sheets; the pack colloid is formed on the chip carrier; the first chip, the second chip, the conductor wires and the heat radiation sheets are coated by the pack colloid. The present invention which integrates a heat radiation structure has the advantages that the heat radiation efficiency of the chip is enhanced, and the chip is combined with the heat radiation structure in a batch mode to lower packing cost and enhance packing efficiency.
Description
Technical field
The invention relates to a kind of semiconductor package part and method for making thereof of stack chip, particularly about a kind of semiconductor package part and method for making thereof of integrating heat sink and stack chip.
Background technology
Flourish along with electronic industry, electronic product also develops to multi-functional, high performance direction gradually, to satisfy the package requirements of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization).For performance and the capacity that improves single semiconductor package part, meet the trend of miniaturization of electronic products, big capacity and high speed, existing product is with multi-chip module (Multi Chip Module mostly with semiconductor package part; MCM) form presents.This packaging part can reduce overall package part volume and improve electrical functionality, therefore becomes a kind of main flow of encapsulation.It is to connect to put at least two semiconductor chips (semiconductor chip) on the chip carrier of single packaging part, and all is that mode with vertical stack (stack) connects and puts between each chip and chip carrier (chip carrier).
A kind of stacking-type multi-chip structure that uses in the prior art is to utilize flip chip technology (fct) (Flip Chip) to be electrically connected to substrate (substrate) lower floor's chip, and utilizes wire bond technology (Wire Bonding) to be electrically connected to substrate the upper strata chip.Below cooperate Fig. 1 and Fig. 2, to United States Patent (USP) the 5th, 815, No. 372 cases and the 6th, 462, No. 405 cases describe.
Fig. 1 is existing stacking-type ball grid array type chip-packaging structure.As shown in the figure, this chip-packaging structure comprises: substrate 100 has positive 100a and back side 100b; First chip 110 has active face 110a and non-active face 110b, and active face 110a utilizes solder projection 111 to be electrically connected to the positive 100a of substrate 100 by flip chip technology (fct); Second chip 120 has active face 120a and non-active face 120b, and non-active face 120b is the non-active face 110b that pastes first chip 110 by adhesive-layer 121; Many leads 140, the positive 100a from the downward routing of active face 120a of second chip 120 to substrate 100 is electrically connected to substrate 100 with second chip 120; Packing colloid 150, the chip 110,120 of two storehouses of coating; And ball grid array (ball grid array) 160, be to plant to put, as the outside electrically tie point on this encapsulation unit at the back side of substrate 100 100b.
Yet a shortcoming of above-mentioned stacking-type ball grid array type chip-packaging structure is, the Highgrade integration semiconductor chip is when operation, can produce a large amount of heats, the packing colloid that coats semiconductor chip is the only bad heat transfer resin material formation of 0.8w/m-k of conductive coefficient, make the loss efficient of heat not good, the performance of this entail dangers to semiconductor chip and useful life.Just because wherein packaged chip 110,120 is not provided with radiator structure, the heat that chip 110,120 is produced when practical operation can be accumulated between two chips 110,120.In addition, the heat that produces because of lower floor's chip 110 can be transmitted to upper strata chip 120, makes the upper strata chip 120 easier destructions that are subjected to thermal stress.
Fig. 2 is existing stacking-type ball grid array type chip-packaging structure with radiating efficiency.As shown in the figure, this chip-packaging structure and shown in Figure 1 roughly the same, main difference is that it has increased the radiating efficiency of encapsulating structure, installs radiating block 230 exactly on substrate 100 additional.This radiating block 230 has support portion 231 and top 232, and its support portion 231 is supported on the positive 100a of substrate 100 232 tops that place upper strata chip 120, top.The heat that this facility produces when making 110,120 practical operations of two chips at first can be transmitted on the potting resin of 230 of second chip 120 and radiating blocks, then diffuses to surrounding environment via radiating block 230 again.Therefore encapsulating structure shown in Figure 2 has higher radiating efficiency than Fig. 1.
Yet during encapsulating structure practical application shown in Figure 2, directly do not touch non-active face 120a, the 120b of two chips 110,120 because of this radiating block 230, the heat that chip produces is transmitted on the radiating block 230 more indirectly via the high resin of thermal resistance value, so its radiating efficiency raising is very limited.
See also Fig. 3, at the shortcoming of above-mentioned prior art, United States Patent (USP) the 6th, 472, No. 741 case has disclosed a kind of stacking-type ball grid array type chip-packaging structure with high cooling efficiency, and it mainly comprises: the substrate 300 with positive 300a and back side 300b; First chip 310 with active face 310a and non-active face 310b, and active face 310a is electrically connected to the positive 300a of this substrate 300 by flip chip technology (fct); Radiating block 338 with support portion 330 and top 337 and bottom 339, and top 337 is formed with at least one through wires hole 336, the support portion 330 of this radiating block 338 is placed on the positive 300a of this substrate 300, and 339 of bottoms meet the non-active face 310b that puts to this first chip 310 with thermal conductivity; Second chip 320 with active face 320a and non-active face 320b, and non-active face 320b connects with thermal conductivity and puts on the top 337 of this radiating block 338; Many leads 340 pass through wires hole 336 on these radiating block 338 tops 337 from the active face 320a of this second chip 320, and routing is electrically connected to this substrate 300 with this second chip 320 to the positive 300a of this substrate 300; Packing colloid 350 coats positive 300a, first chip 310, radiating block 338, second chip 320 and the lead 340 of this substrate 300; And a plurality of soldered balls of putting at this substrate 300 back side 300b 360 that connect.Directly touch non-active face 310b, the 320b of two chips 310,320 by the top 337 of this radiating block 338, so the radiating efficiency higher than prior art shown in Figure 2 can be provided.
But for meeting the light of electronic product, thin, short, little, H.D requirement, relatively the dimensional requirement of semiconductor package is more and more littler, therefore, wafer-level package (Chip ScalePackage, SP) structure, for example the demand of thin spherical grid array encapsulation (TFBGA) is promptly more and more, but because the semiconductor package part of this wafer-level package (CSP) emphasizes that substrate size is suitable with die size, and the zone that supplies the chip wire bonds only can be formed on for chip is sticking and put zone (Die-Attaching Area) to the position between the substrate edges, the space of taking in the radiating block support portion can't be provided, so above-mentioned United States Patent (USP) the 6th, 472, the radiating block with support portion that No. 741 case disclosed promptly can not have redundant space because of the substrate in this CSP structure can be for connecing the support portion of putting radiating block, and make this radiating block can't be applied in the CSP encapsulating structure or have on the substrate of high-density wiring, moreover in this technology, also can cause puzzlement on the substrate manufacture for the setting that cooperates this radiating block support portion.
In addition, United States Patent (USP) the 6th, 472, the support portion of soldered ball (solder ball) as this radiating block is set at end place, substrate angle for No. 743, but this technology will relate to the change of board structure, and is simultaneously wayward because of this ball height, causes connecing the radiating block of putting on it and produce deflection, even touch the chip signal lead and be short-circuited, cause the decline of technologic inconvenience, reliability and the increase of expense.And in this technology,, can cause the puzzlement on the substrate manufacture equally for cooperating the setting of this radiating block support portion.
Moreover, above-mentioned these semiconductor package parts, because the bonding of radiating block and chip must accurately control avoiding the generation of tilt problem, the encapsulation of this semiconductor package part can't be with batch mode of (Batch-type) bond chip and radiating block; Just radiating block must be bonding one by one with corresponding chip, increased the complexity of overall package technology and required time-histories, so the raising of the reduction of unfavorable packaging cost and packaging efficiency.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof of stack chip, can integrate radiator structure effectively in the semiconductor package part of this multicore sheet, and then improves its radiating efficiency.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof of stack chip, it is not subjected to the area constraints of wafer-level package (CSP) structure, integrates radiator structure effectively in the semiconductor package part of this multicore sheet.
Another purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof of stack chip, can improve the heat radiation and the electrical quality of the semiconductor package part of multicore sheet.
A further object of the present invention is to provide a kind of semiconductor package part and method for making thereof of stack chip, in that heat sink is supported under the situation of substrate, integrates radiator structure in packaging part.
An also purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof of stack chip, can the run-off the straight problem when making heat sink be incorporated into semiconductor package part, and then improve the acceptance rate of manufactured goods.
An also purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof of stack chip, can simplify the complexity of overall package technology and required time-histories, and then the mode that adopts batch (Batch-type) reduces packaging cost and improves packaging efficiency in conjunction with chip and radiator structure.
For reaching above-mentioned and other purpose, the method for making of the semiconductor package part of stack chip of the present invention comprises: preparation comprises the chip carrier module sheet of a plurality of chip carriers unit, connect at the predeterminated position of this chip carrier unit respectively and to put first chip, make this first chip be electrically connected to this chip carrier unit; The heat sink module that includes a plurality of heat sinks unit sheet is provided, the size of this heat sink unit is corresponding to the size of this chip carrier unit, and respectively be formed with a plurality of openings that run through around this heat sink unit, this heat sink unit correspondence connect put on this first chip respectively; On this heat sink unit respectively, connect and put second chip, and make this second chip be electrically connected to this chip carrier unit by passing the lead that this heat sink module sheet runs through opening; Carry out the Encapsulation Moulds compression technology, make the complete coating of packing colloid be positioned at first, second chip and heat sink module sheet on this chip carrier module sheet; And cut single job, and run through opening cutting around this chip carrier unit respectively and around the heat sink unit, make the semiconductor package part of the stack chip that is integrated with heat sink.
This first chip is to connect with its active face with flip chip to put and be electrically connected to this chip carrier, directly connects for this heat sink and puts on this chip non-active face; This first chip also can its non-active face connects to be put behind chip carrier, electrically connects in the routing mode again, and this heat sink buffering spacer at interval connects to put on this first chip active face and do not influence the routing zone; The type of this chip carrier is a substrate; This heat sink surface can carry out melanism with the packing colloid contact portion or brown is handled, so as to increasing the adhesion between heat sink and packing colloid.
By above-mentioned technology, the present invention also provides a kind of semiconductor package part of stack chip, and this semiconductor package part comprises: chip carrier; Connect first chip of putting and being electrically connected on this chip carrier; Be formed with a plurality of heat sinks that run through opening, connect and put on this first chip and do not touch this chip carrier; Connect second chip of putting on this heat sink, and this second chip is electrically connected to this chip carrier by passing the lead that this heat sink runs through opening; And be formed on packing colloid on this chip carrier, coat this first, second chip, lead and heat sink.This heat sink part side open goes out this packing colloid.Wherein this first chip can flip-chip or the routing mode be electrically connected to this chip carrier; When adopting flip chip to electrically connect first chip and chip carrier, this heat sink directly can be connect the non-active face of putting at this first chip, relatively when adopting the routing mode to electrically connect first chip and chip carrier, can not influencing the lead placement earlier on this first chip active face connects and puts and chip thermal coefficient of expansion (CTE, Coefficient of Thermal Expansion) behind the suitable buffering spacer (Buffer Pad), on this buffering spacer, connect again and put this heat sink, avoid the direct bonding meeting of the heat sink and first chip to touch, can reduce simultaneously under both directly bonding situations that do not coexist of heat sink and chip thermal coefficient of expansion heat sink the thermal stress of chip generation to lead.
In an embodiment of the present invention, this chip carrier is thin spherical grid array encapsulation (TFBGA) substrate, and plants on this substrate bottom surface and be connected to a plurality of soldered balls as the medium of chip with the external device electric connection.
This chip carrier can also be LGA (LAND GRID ARRAY) substrate, is electrically connected to external device (ED) for chip via a plurality of metallic contacts that are arranged in this substrate bottom surface.
Should be specifically noted that at this, in semiconductor package part of the present invention and the method for making thereof, the electric connection mode of using between the selection of this chip carrier and chip and chip carrier is under spirit of the present invention and category, combination and variation in addition, and all are features that the present invention is contained.
In sum, the semiconductor package part of stack chip of the present invention and method for making thereof can directly connect heat sink and put on first chip by adhesion coating, can in the semiconductor package part of this multicore sheet, integrate radiator structure effectively, improve the radiating efficiency of semiconductor package part; The present invention is not subjected to the area constraints of wafer-level package (CSP) structure, can integrate radiator structure effectively in the semiconductor package part of this multicore sheet, thereby has improved the radiating efficiency and the electrical quality of the semiconductor package part of multicore sheet.The present invention integrates radiator structure in that heat sink is supported under the situation of substrate in packaging part, can the run-off the straight problem when making heat sink be incorporated into semiconductor package part, and then improve the acceptance rate of manufactured goods.Therefore the present invention can simplify the complexity of overall package technology and required time-histories, and then the mode that adopts batch (Batch-type) reduces packaging cost and improves packaging efficiency in conjunction with chip and radiator structure.
Description of drawings
Fig. 1 is the generalized section of existing stacking-type ball grid array type chip-packaging structure;
Fig. 2 is existing generalized section with stacking-type ball grid array type chip-packaging structure of radiator structure;
Fig. 3 is a United States Patent (USP) the 6th, 472, the semiconductor package part generalized section of No. 741 cases;
Fig. 4 A to Fig. 4 H is the generalized section of the method for producing semiconductor packaging part embodiment 1 of stack chip of the present invention;
Fig. 4 E ' is the vertical view of corresponding diagram 4E, shows that connect second chip put on the heat sink unit is electrically connected to base board unit by passing the lead that heat sink module sheet runs through opening;
Fig. 5 A to Fig. 5 C is the heat sink module sheet schematic diagram that can be incorporated in the semiconductor package part of stack chip of the present invention;
Fig. 6 is the generalized section of the semiconductor package part embodiment 2 of stack chip of the present invention;
Fig. 7 is the generalized section of the semiconductor package part embodiment 3 of stack chip of the present invention; And
Fig. 8 is the generalized section of the semiconductor package part embodiment 4 of stack chip of the present invention.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention.
Embodiment 1
Semiconductor package part of the present invention comprises: chip carrier; Connect first chip 41 of putting and being electrically connected on this chip carrier; Be formed with a plurality of heat sinks 43 that run through opening, connect and put on this first chip 41 and do not touch this chip carrier; Connect second chip of putting on this heat sink 42, and this second chip 42 is electrically connected to this chip carrier by passing the lead that this heat sink 43 runs through opening 430; And be formed on packing colloid 45 on this chip carrier, coat this first chip 41, second chip 42, lead and heat sink 43.Wherein, this chip carrier is a base board unit 40.
See also Fig. 4 A to Fig. 4 H, it is the process schematic representation of the method for producing semiconductor packaging part embodiment 1 of stack chip of the present invention.
Shown in Fig. 4 A and 4B figure, at first, one substrate module sheet 40A is provided, this substrate module sheet 40A is arranged with array way by a plurality of base board units 40 to constitute, this base board unit 40 have first surface 401 and with the corresponding second surface 402 of this first surface, these base board unit 40 first surfaces 401 are provided with a plurality of first weld pads 403 and second weld pad 404, this first weld pad 403 concentrates on this base board unit 40 first surfaces 401 central authorities, supplying first chip 41 to connect by flip chip puts and electrically connects, this second weld pad 404 be distributed in these base board unit 40 first surfaces 401 around, electrically connect by lead technology for follow-up second chip.Wherein, this first chip 41 has active face 411 and non-active face 412, and this first chip 41 is electrically connected to flip chip on first weld pad 403 of these base board unit 40 first surfaces 400 by its active face 411 and by electric conducting material 410.The process conditions permission is noted that this base board unit 40 also can the vertical bar mode be arranged except arranging with array way, if also can adopt the mode of single base board unit to carry out.
Shown in Fig. 4 C and Fig. 4 D, the heat sink module sheet that includes a plurality of heat sinks unit 43 43A is provided, the size of this heat sink unit 43 is corresponding to the size of this base board unit 40, and respectively be formed with a plurality of openings 430 that run through around this heat sink unit 43, this heat sink unit 43 respectively connect by heat conduction adhesion coating (not marking) correspondence put on the non-active face 412 of this first chip 41 respectively.Also can carry out melanism or brown processing, so as to good conjugation between follow-up this heat sink unit 43 and packing colloid is provided to this heat sink module sheet 43A; And respectively the opening 430 that runs through of this adjacent heat sink unit 43 communicates with each other, and respectively during this heat sink unit, reduces the consume of cutting tool for later separation.
Shown in Fig. 4 E, on this heat sink unit 43 respectively, connect and put second chip 42, and make this second chip 42 be electrically connected to this base board unit 40 by passing the lead 44 that this heat sink module sheet 43A runs through opening 430.This second chip 42 has active face 421 and non-active face 422, this second chip 42 is to connect with non-active face 422 to put in this heat sink unit 43, and pass the lead 44 that this heat sink module sheet 43A runs through opening 430, this second chip 42 is electrically connected to second weld pad 404 on these base board unit 40 first surfaces 401.
Other sees also Fig. 4 E ', and it is the vertical view of corresponding diagram 4E, shows that second chip 42 connects to put on this heat sink unit 43, and to pass the lead 44 that this heat sink module sheet 43A runs through opening 430, is electrically connected to second weld pad 404 on this base board unit 40.
Shown in Fig. 4 F, carry out the Encapsulation Moulds compression technology, make packing colloid 45 complete coatings be positioned at first, second chip 41,42 and heat sink module sheet 43A on this chip carrier module sheet 40A.The structure that just this is combined with heat sink module sheet 43A, first chip 41, second chip 42 and substrate module sheet 40A is inserted in the die cavity (not marking) of encapsulating mould, carry out molding operation, be formed for coating the packing colloid 45 of this heat sink module sheet 43A, first, second chip 41,42 and lead 44.
Shown in Fig. 4 G, cut single job, along this chip carrier unit 40 respectively and 43 edges, heat sink unit cut, form a plurality of stack chip semiconductor package parts (shown in Fig. 4 H) that are integrated with heat sink.Because in cutting single technology, cutting tool mainly be by this heat sink module sheet 43A run through opening 430, so its suffered consume is less, and is difficult for producing the burr problem, help the carrying out and the cost control of cutting technique, help a large amount of productions of encapsulating structure simultaneously.In addition, also can on the second surface 402 of each base board unit 40 of this substrate module sheet 40A, plant the conductive component 46 that connects a plurality of for example soldered balls, for this chip 41,42 and external device formation electrical connection.This is cut list and plants the technology of ball, is will plant semi-finished product vacuum suction that ball finishes on packing colloid 45 with jig (not marking), and when cutting single job and carry out and after finishing, each semi-finished product through cutting after single still can be adsorbed on the jig; Certainly, this for example the setting of the conductive component 46 of soldered ball also can carry out again after base board unit is cut single technology follow-up finishing.
The stack chip packaging part that is integrated with heat sink by above-mentioned explained hereafter, can be by the heat of this heat sink 43 loss chips generation, simultaneously, respectively this heat sink 43 carries out with engaging in batch mode of first and second chip 41,42, so can simplify technology, reduce consuming time and reduce cost.
Other sees also Fig. 5 A and Fig. 5 B, it is that another kind can be incorporated into the heat sink module sheet 43B in the semiconductor package part of stack chip of the present invention, except respectively forming for running through the opening 430 that the second chip lead passes through around this heat sink unit 43, the angle end that also joins in this heat sink unit 43 respectively forms cutting groove (Slots) 431, or expansion runs through opening 430 sizes, the cutter wearing and tearing when further single job is cut in minimizing; Shown in Fig. 5 C, in this heat sink module sheet 43C, if cut the permission of single technology and for enlarging the area of dissipation of heat sink, can make and run through opening 430 non-common linking together around this heat sink unit 43 respectively, still can keep more area of dissipation after single cutting in the heat sink unit.
See also Fig. 6, it is the generalized section with reference to the made semiconductor package part embodiment 2 of the method for producing semiconductor packaging part of the above-mentioned stack chip of the present invention.This semiconductor package part of the present invention is by making similar in appearance to the method for preparing embodiment 1, difference is in the semiconductor package part of present embodiment 2, when carrying out the routing operation of second chip 52, utilize this heat sink 53 as ground plane, second chip 52 is electrically connected to this heat sink 53 by earth lead 540, so as to improving the electrical functionality of this semiconductor package part.Wherein on this heat sink 53 in order to improve the connection effect of this earth lead (gold thread), silver-plated for the lead link position on this heat sink, improved zygosity.
See also Fig. 7, it is the generalized section of the semiconductor package embodiment 3 that makes with reference to the method for producing semiconductor packaging part of the above-mentioned stack chip of the present invention.This semiconductor package of the present invention is by making similar in appearance to the method for the semiconductor structure for preparing embodiment 1, difference is, the chip carrier that present embodiment uses is LGA (LAND GRID ARRAY) substrate 60, makes first and second chip 61,62 be electrically connected to external device (ED) via a plurality of metallic contact 60a that are arranged in these LGA substrate 60 bottom surfaces.
Embodiment 4
See also Fig. 8, it is the generalized section of the semiconductor package embodiment 4 that makes with reference to the method for producing semiconductor packaging part of the above-mentioned stack chip of the present invention.This semiconductor package of the present invention is by making similar in appearance to the method for semiconductor structure of preparation embodiment 1, and difference is that first chip 71 of present embodiment is to be electrically connected to this base board unit 70 in the routing mode.The non-active face 712 of this first chip 71 connects to be put on this base board unit 70, and be electrically connected to this base board unit 70 by lead 77, on the active face 711 of this chip 71, do not influence lead 77 placements in addition, can connect and put the buffering spacer 78 suitable with the thermal coefficient of expansion of this first chip 71, and setting is formed with the heat sink 73 that runs through opening 730 on this buffering spacer 78, on this heat sink 73, connect and put second chip 72, and make this second chip 72 be electrically connected to this base board unit 70 by passing this lead that runs through opening 730 74.
The size of this buffering spacer 78 is limited in the scope that can not interfere with lead 77, and its thickness must be a little more than the summit of lead 77 banks, on this buffering spacer 78, connect when putting heat sink 73, this heat sink 73 can not touch lead 77, simultaneously, this buffering spacer 78 can clear up the thermal stress that under hot environment heat sink 73 produces this first and second chip 71,72 because of the difference of thermal coefficient of expansion, and the heat that makes first and second chip 71,72 produce is delivered to this heat sink 73 by this buffering spacer 78.This buffering spacer 78 can be the chip of discarding (Dummydie), if the material permission also can be adopted metal materials such as copper, aluminium.
Should be specifically noted that at this, in the semiconductor package part and method for making thereof of above-mentioned each embodiment of the present invention, the electric connection mode of using between the selection of this chip carrier and chip and the chip carrier, under spirit of the present invention and category, combination and variation in addition, and it all is features that the present invention is contained.
Therefore, the semiconductor package part of stack chip of the present invention and method for making thereof are heat sink directly to be connect put on first chip, need not in addition the support portion to be set on this heat sink and the usage space that occupies substrate, so can be fit to make chip grade packaging structure.And the present invention can correspondingly adopt a large amount of production technologies of modularization, the heat sink module sheet that the chip carrier module sheet that comprises a plurality of chip carriers unit is provided and includes a plurality of heat sinks unit, and be formed with the common opening that runs through around in this adjacent heat sink unit, on this chip carrier module sheet, connect successively and put first chip, the heat sink module sheet and second chip, and make this second chip be electrically connected to this chip carrier module sheet by the lead that passes this heat sink module sheet and run through opening, can be after finishing the Encapsulation Moulds compression technology along respectively single job is cut in this chip carrier unit and heat sink unit, and this cutting tool is the opening that runs through by this heat sink module sheet, the a plurality of stack chip packaging parts that are integrated with heat sink of a large amount of formation, and because of this cutting tool is the opening that runs through by this heat sink module sheet, can avoid the cutting tool excessive wear like this, help the carrying out and cutting cost control of cutting technique, be convenient to this packaging part of volume production simultaneously.
In addition, be to produce among the present invention in a batch mode, can simplify technology, reduce the consuming time of encapsulation and reduce cost, after in mould pressing process, making this heat sink of the complete coating of packing colloid and chip, cut single job again, avoid heat sink in the existing semiconductor packaging process must with the bonding one by one complexity of corresponding chip and expensive.
Claims (18)
1. the method for producing semiconductor packaging part of a stack chip is characterized in that, this method for making comprises:
Preparation comprises the chip carrier module sheet of a plurality of chip carriers unit, connects at the predeterminated position of this chip carrier unit respectively and puts first chip, makes this first chip be electrically connected to this chip carrier unit;
The heat sink module that includes a plurality of heat sinks unit sheet is provided, the size of this heat sink unit is corresponding to the size of this chip carrier unit, and respectively be formed with a plurality of openings that run through around this heat sink unit, this heat sink unit correspondence connect put on this first chip respectively;
On this heat sink unit respectively, connect and put second chip, and make this second chip be electrically connected to this chip carrier unit by passing the lead that this heat sink module sheet runs through opening;
Carry out the Encapsulation Moulds compression technology, make the complete coating of packing colloid be positioned at first, second chip and heat sink module sheet on this chip carrier module sheet; And
Cut single job, run through opening cutting around this chip carrier unit respectively and around the heat sink unit, be formed in the semiconductor package part of integrating this heat sink in the stack chip.
2. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this chip carrier is a substrate, and this type of substrate is a kind of among TFBGA and the LGA, and the module form be adopt matrix form arrange and stripe-arrangement in a kind of.
3. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this first chip is to be electrically connected to this chip carrier unit with flip-chip or routing mode.
4. the method for producing semiconductor packaging part of stack chip as claimed in claim 1, it is characterized in that, this first chip connect put and be electrically connected to this chip carrier unit after, also can on this first chip, connect earlier and put buffering spacer, on this buffering spacer, connect again and put this heat sink module sheet.
5. the method for producing semiconductor packaging part of stack chip as claimed in claim 4 is characterized in that, the material of this buffering spacer is a kind of in waste chips and the metal.
6. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this heat sink module sheet is to handle through melanism or brown, so that good conjugation between itself and the packing colloid to be provided.
7. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this heat sink module sheet communicates with each other at the opening that runs through of this adjacent heat sink unit respectively, when cutting single technology, cuts the hilted broadsword tool and is able to run through opening by this.
8. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this heat sink module sheet angle end that joins in this heat sink unit respectively is formed with cutting groove.
9. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this chip carrier unit is provided with conductive component, forms electrical connection for this first and second chip and external device.
10. the method for producing semiconductor packaging part of stack chip as claimed in claim 1 is characterized in that, this heat sink unit can be used as ground plane, and second chip is electrically connected to this heat sink unit by earth lead.
11. the semiconductor package part of a stack chip is characterized in that, this semiconductor package part comprises:
Chip carrier;
Connect first chip of putting and being electrically connected on this chip carrier;
Be formed with a plurality of heat sinks that run through opening, connect and put on this first chip and do not touch this chip carrier;
Connect second chip of putting on this heat sink, and this second chip is electrically connected to this chip carrier by passing the lead that this heat sink runs through opening; And
Be formed on the packing colloid on this chip carrier, coat this first, second chip, lead and heat sink.
12. the semiconductor package part of stack chip as claimed in claim 11 is characterized in that, this chip carrier is a substrate, and this type of substrate is a kind of among TFBGA and the LGA.
13. the semiconductor package part of stack chip as claimed in claim 11 is characterized in that, this first chip is that the mode with flip-chip or routing is electrically connected to this chip carrier.
14. the semiconductor package part of stack chip as claimed in claim 11 is characterized in that, is separated with buffering spacer between between this first chip and the heat sink.
15. the semiconductor package part of stack chip as claimed in claim 14 is characterized in that, the material of this buffering spacer is a kind of in waste chips and the metal.
16. the semiconductor package part of stack chip as claimed in claim 11 is characterized in that, this heat sink is to handle through melanism or brown, and good conjugation between itself and the packing colloid is provided.
17. the semiconductor package part of stack chip as claimed in claim 11 is characterized in that, this chip carrier is provided with conductive component, forms electrical connection for this first and second chip and external device.
18. the semiconductor package part of stack chip as claimed in claim 11 is characterized in that, this heat sink can be used as ground plane, and second chip is electrically connected to this heat sink by earth lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100076177A CN100362639C (en) | 2005-02-07 | 2005-02-07 | Semiconductor packer and production for godown chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100076177A CN100362639C (en) | 2005-02-07 | 2005-02-07 | Semiconductor packer and production for godown chip |
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| CN1819129A CN1819129A (en) | 2006-08-16 |
| CN100362639C true CN100362639C (en) | 2008-01-16 |
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| CNB2005100076177A Expired - Fee Related CN100362639C (en) | 2005-02-07 | 2005-02-07 | Semiconductor packer and production for godown chip |
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| CN101442012B (en) * | 2007-11-20 | 2010-10-27 | 华东科技股份有限公司 | Model sealing and cutting method for small window and formed encapsulation conformation |
| CN104269385B (en) * | 2014-10-21 | 2017-12-19 | 矽力杰半导体技术(杭州)有限公司 | Package assembling and its manufacture method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6650006B2 (en) * | 2001-05-25 | 2003-11-18 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with stacked chips |
| US6716676B2 (en) * | 2001-06-04 | 2004-04-06 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
| CN1174484C (en) * | 2000-11-17 | 2004-11-03 | 矽品精密工业股份有限公司 | Semiconductor package with radiating structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1174484C (en) * | 2000-11-17 | 2004-11-03 | 矽品精密工业股份有限公司 | Semiconductor package with radiating structure |
| US6650006B2 (en) * | 2001-05-25 | 2003-11-18 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with stacked chips |
| US6716676B2 (en) * | 2001-06-04 | 2004-04-06 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
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