CN101090077A - Semiconductor package and its manufacturing method - Google Patents
Semiconductor package and its manufacturing method Download PDFInfo
- Publication number
- CN101090077A CN101090077A CNA2006100918502A CN200610091850A CN101090077A CN 101090077 A CN101090077 A CN 101090077A CN A2006100918502 A CNA2006100918502 A CN A2006100918502A CN 200610091850 A CN200610091850 A CN 200610091850A CN 101090077 A CN101090077 A CN 101090077A
- Authority
- CN
- China
- Prior art keywords
- electric
- semiconductor package
- conductor
- package part
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
This invention discloses a semiconductor package piece and its manufacturing method, in which the piece includes: a chip carrier set with multiple electric connection points, at least one semiconductor chip set and connected to the carrier, multiple conducting pieces set and connected to the connecting points and a package colloid formed on the carrier to cover the chip and the conducting pieces and expose at the side surfaces of the conducting pieces, which can provide extra multiple electric connection points so as to strengthen electric functions of electronic products.
Description
Technical field
The invention relates to a kind of semiconductor package part and method for making thereof, particularly about a kind of semiconductor package part and method for making thereof that extra electrical contact is provided.
Background technology
Because increasing substantially of various portable (Portable) products such as communication, network and computer, can dwindle integrated circuit (IC) area and have high density and the ball grid array of multitube pin characteristic (BGA) packaging part day by day becomes the main flow of encapsulation on the market, and normal and microprocessor, chipset, the contour performance chip collocation of drawing chip, performance is the calculation function of high speed more.Wherein, ball grid array (BGA) is a kind of advanced person's a semiconductor die package technology, its characteristics are to adopt a substrate to settle semiconductor chip, and the soldered ball (Solder Ball) that a plurality of one-tenth grid arrays are arranged is set at this substrate back, make on the semiconductor chip carriers of same units area and can hold more I/O link (I/O Connection), it is required to meet Highgrade integration (Integration) semiconductor chip, by these soldered balls whole encapsulation unit is welded and be electrically connected to external device (ED).
Moreover, for improving the semiconductor package part production capacity and saving process cost, the making of micro semiconductor packaging part now adopts batch mode more, promptly demarcate by the staggered encapsulation of many grids palisade on whole piece chip carrier (chip carrier) surface, pre-definedly go out many encapsulation units that are arranged, process last slice (Die bond), welding (Wire bond) and colloid encapsulation (Encapsulation) supervisor, and, form a plurality of independently semiconductor package parts with the connecting portion between cutting operation (Singulation) removal adjacent semiconductor encapsulation unit.For example for satisfying the compact design requirement of electronic product, industry develops a kind of littler thin spherical grid array of overall dimensions (TFBGA) packaging part or planar lattice array (Land Grid Array of providing; LGA) packaging part, it mainly in batch mode is based upon on the same substrate, this substrate marks off many packaging areas in advance, define indivedual TFBGA encapsulation units position respectively, steps such as crystalline substance, routing, mold pressing are carried out cutting action (Singulation process) at last again on the process, with each packaging area and settle the semiconductor chip cutting on it to come, form many LGA packaging parts, or soldered ball formation TFBGA packaging part is set on substrate.Correlation technique can be consulted cases such as United States Patent (USP) the 5776798th, 6593658,6281047.
In addition, industry also develop a kind of similar above-mentioned TFBGA packaging part, with quad flat pin-free (QFN) packaging part of lead frame as chip carrier, it is to arrange lead frame to be arranged equally, after placing semiconductor chip on this lead frame and carrying out routing, steps such as encapsulation mold pressing etc., carry out cutting action again, form many QFN packaging parts.Correlation technique is to consult cases such as United States Patent (USP) the 6143981st, 6399415,6424024.
Above-mentioned various light and thin type semiconductor package part can be applicable in the portable type electronic product, for example " semiconductor device of sensing type and the method for making thereof " of TaiWan, China patent No. I242820 number promptly discloses and utilizes the TFGBA structure to integrate control chip and sensor chip in an encapsulating structure, constitute (compact camera module, a CCM) encapsulating structure.
But, in above-mentioned various semiconductor package part or applied CCM encapsulating structure, the carrier of this semiconductor package part or encapsulating structure (as substrate or lead frame) can only below provide and the extraneous electrical contact that electrically connects, can't be in packaging part or encapsulating structure side, or upper surface (packing colloid part) provides extra electrical contact, electronic product excellent electrical property function so not only can't be provided, also will limit simultaneously the use of electronic product, the storehouse that for example can't carry out packaging part maybe can't utilize socket (socket) that packaging part is electrically connected to external device (ED).
Therefore, how to provide a kind of a plurality of electrical contacts can additionally be provided, avoid limiting problems such as electronic product use, the semiconductor package part and the method for making thereof of electronic product good electrical sexual function also can be provided simultaneously, become present problem demanding prompt solution.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof, and a plurality of electrical contacts can additionally be provided, thus the electrical functionality of strengthening electronic product and the scope of application.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof, can form electrical contact at the packaging part side.
Another purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof, can form electrical contact at packaging part side and end face.
A further object of the present invention is to provide a kind of semiconductor package part and method for making thereof, can be for the directly electrical storehouse that carries out semiconductor package part.
An also purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof, can electrically connect with socket.
For realizing above-mentioned and other purpose, the method for making of semiconductor package part of the present invention comprises: a chip carrier module sheet with many chip carriers is provided, and respectively this chip carrier is provided with a plurality of electric connection points; Between corresponding each chip carrier electric-conductor is being set on this chip carrier module sheet, and is making this electric-conductor electrically connect the electric connection point of adjacent chips carrier, and on this chip carrier respectively, connecing and put and electrically connect semiconductor chip; Encapsulate molding operation, on this chip carrier module sheet, form the packing colloid of this semiconductor chip of coating and electric-conductor; And cut along packing colloid between this chip carrier respectively and electric-conductor, separate the electric-conductor that is arranged on the adjacent chips carrier, and make this electric-conductor part surface expose this packing colloid, thereby separate respectively this chip carrier.
This electric-conductor upper surface also can directly expose this packing colloid after the encapsulation mold pressing, also this packing colloid can be carried out the thinning operation, expose this electric-conductor upper surface, then cut this packing colloid and electric-conductor again, make this electric-conductor side surface expose this packing colloid, can utilize the upper surface that exposes this electric-conductor and side surface like this as the electrical contact that electrically connects with the external world.
By above-mentioned method for making, the present invention also provides a kind of semiconductor package part, and this semiconductor package part comprises: a chip carrier, this chip carrier are provided with a plurality of electric connection points; At least one semiconductor chip connects and puts and be electrically connected to this chip carrier; Many electric-conductors connect and put and be electrically connected to this electric connection point; And a packing colloid, be formed on this chip carrier, coat this semiconductor chip and electric-conductor, and make this electric-conductor side surface expose this packing colloid at least.
Therefore, semiconductor package part of the present invention and method for making thereof are to have on the chip carrier module sheet of many chip carriers one, between corresponding each chip carrier electric-conductor is set, and make this electric-conductor electrically connect the electric connection point of adjacent chips carrier, and on this chip carrier respectively, connect and put and electrically connect semiconductor chip, carry out molding operation again, form the packing colloid of this semiconductor chip of coating and electric-conductor, then along respectively cutting between this chip carrier, separate the electric-conductor that is arranged on the adjacent chips carrier, make the part surface of this electric-conductor expose this packing colloid, wherein, this electric-conductor upper surface can directly expose this packing colloid after mold pressing, also this packing colloid can be carried out the thinning operation, the upper surface that exposes this electric-conductor, then form just like nickel/golden electrodeposited coating on the electric-conductor surface of exposing this packing colloid, providing follow-up and extraneous electrically connects, and then separate respectively this chip carrier, the electric-conductor that this packing colloid is exposed in utilization provides extra electrical contact, for the follow-up storehouse that carries out packaging part, or utilize socket (socket) that packaging part is electrically connected to external device (ED), avoid limiting the problems such as use of electronic product, electronic product excellent electrical property function also can be provided simultaneously.
Description of drawings
Figure 1A to Fig. 1 H is semiconductor package part of the present invention and method for making embodiment 1 schematic diagram thereof;
Fig. 2 A to Fig. 2 E is semiconductor package part of the present invention and method for making embodiment 2 schematic diagrames thereof;
Fig. 2 B ' is a schematic diagram of removing the part packing colloid with lapping mode;
Fig. 3 is the substrate module sheet schematic diagram that uses among semiconductor package part of the present invention and the method for making embodiment 3 thereof;
Fig. 4 A to Fig. 4 E is semiconductor package part of the present invention and method for making embodiment 4 schematic diagrames thereof;
Fig. 5 A to Fig. 5 C is the schematic diagram that semiconductor package part of the present invention is used.
Embodiment
Embodiment 1
Figure 1A to Fig. 1 H is the schematic diagram of semiconductor package part of the present invention and method for making embodiment 1 thereof.
Shown in Figure 1A, at first, the one chip carrier module sheet with many chip carriers is provided, respectively this chip carrier is provided with a plurality of electric connection points, cooperate simultaneously and consult Figure 1B, it is the generalized section of corresponding Figure 1A chip carrier module sheet, this chip carrier module sheet is a substrate module sheet 100 in the present embodiment, respectively this chip carrier is thin spherical grid array (TFBGA) or planar lattice array (LGA) substrate 10, respectively this substrate 10 by many laterally and directly divide to line of cut (shown in dotted line), simultaneously this laterally and directly to the line of cut place, on the corresponding substrate module sheet 100, form plating bus 11 on the lower surface, this plating bus 11 is located on this substrate 10, between lower surface, and this plating bus 11 is to extend the line construction that is electrically connected to substrate 10 surfaces, wherein, be provided with a plurality of as first electric connection pad (pad) 101 and second electric connection pad 102 at the upper surface of this substrate 10 respectively, and be provided with the 3rd electric connection pad 103 etc. at these substrate 10 lower surfaces and electrically connect point, wherein, this first electric connection pad 101 can pass through conductive through hole (via) 104 electrical communication to the 3rd electric connection pad 103, and this first, second and third electric connection pad 101,102,103 can be electrically connected to this plating bus 11 by the conducting wire.The 3rd electric connection pad 103 corresponding thin spherical grid arrays (TFBGA) or planar lattice array (LGA) substrate are solder ball pad (ball pad) or electricity connection end (terminal), this first electric connection pad 101 can for example be that weldering refers to (bonding finger), second electric connection pad can for example be a contact pad 102, but not as limit, for example this first electric connection pad 101 can be a flip-chip weld pad (bumppad) etc.
Shown in Fig. 1 C, corresponding 10 of each substrates are provided with electric-conductor 12 on this substrate module sheet 100, and make this electric-conductor 12 electrically connect second electric connection pad 102 of adjacent substrate 10, and connect on this substrate 10 respectively and put and electrically connect semiconductor chip 13; Please cooperate and consult Fig. 1 D, it is the generalized section of corresponding diagram 1C, wherein this electric-conductor 12 is metals such as copper post or copper ball for example, utilize second electric connection pad 102 that is electrically connected to adjacent substrate 10 as electric conducting materials such as scolding tin, or this electric-conductor 12 can directly use soldering tin materials such as soldered ball, in addition, this semiconductor chip 13 is electrically connected to first electric connection pad 101 of this substrate 10 in the routing mode.Certainly also can utilize flip chip that semiconductor chip is electrically connected to this substrate, and connecing of this electric-conductor put operation and can be cooperated and put crystal type and carry out before and after putting brilliant step.
Shown in Fig. 1 E, on this substrate module sheet 100, form the packing colloid 14 of this semiconductor chip 13 of coating and electric-conductor 12.
Shown in Fig. 1 F, the edge is this substrate this packing colloid 14 of 10 cuttings and electric-conductor 12 respectively, separate the electric-conductor 12 that is arranged on the adjacent substrate 10, and make these electric-conductor 12 side surfaces expose this packing colloid 14, wherein this depth of cut makes this electric-conductor 12 still possess electrical connection with plating bus 11 at least, with in follow-up electroplating work procedure, nickel/deposition of gold is exposed on the electric-conductor 12 of packing colloid at this by this plating bus 11.
Shown in Fig. 1 G, in cutting and separating respectively behind the electric-conductor 12 on this substrate 10, owing to remain in the electric-conductor 12 on this substrate 10 respectively, still can be electrically connected to this plating bus 11, therefore can on electric-conductor 12 side surfaces that expose this packing colloid 14, form for example metal level 15 of nickel/gold by plating mode by second electric connection pad 102 and conductive through hole 104.
Shown in Fig. 1 H, carry out cutting operation afterwards again, separate respectively this substrate 10, formation can provide the semiconductor package part of a plurality of extra electrical contacts in the packing colloid side.
Therefore, by above-mentioned method for making, the invention provides a kind of semiconductor package part, this semiconductor package part comprises: the chip carrier of substrate 10 for example, this substrate 10 are provided with the electric connection points of a plurality of as first, second and third electric connection pad 101,102,103; At least one semiconductor chip 13 is electrically connected to this substrate 10 with routing or flip chip; Many electric-conductors 12 connect and put and be electrically connected to this electric connection point as second electric connection pad 102; And a packing colloid 14, be formed on this substrate 10, be used for coating this semiconductor chip 13 and electric-conductor 12, and make these electric-conductor 12 side surfaces expose this packing colloid 14 at least.
Embodiment 2
Fig. 2 A to Fig. 2 E is the schematic diagram of semiconductor package part of the present invention and method for making embodiment 2 thereof, and present embodiment and the foregoing description are roughly the same, so similar elements is no longer described.
Shown in Fig. 2 A, substrate module sheet 200 with many substrates 20 at first is provided, respectively on this substrate 20, be equipped with plating bus 21 between lower surface, and this plating bus 21 is to extend the surface lines structure that is electrically connected to substrate 20, wherein be provided with electric connection points a plurality of as first electric connection pad 201 and second electric connection pad 202 at the upper surface of this substrate 20 respectively, and be provided with the 3rd electric connection pad 203 at the lower surface of this substrate 20, this first electric connection pad 201 can pass through conductive through hole (via) 204 electrical communication to the 3rd electric connection pad 203, and this first, second and third electric connection pad 201,202,203 can be electrically connected to this plating bus 21 by the conducting wire.
Then, corresponding 20 of each substrates are provided with electric-conductor 22 on this substrate module sheet 200, and make this electric-conductor 22 electrically connect second electric connection pad 202 of adjacent substrate 20, and on this substrate 20 respectively, connect and put and electrically connect semiconductor chip 23, this semiconductor chip 23 can be electrically connected to this substrate by bonding wire.
Shown in Fig. 2 B and 2C, encapsulate molding operation, on this substrate module sheet 200, form the packing colloid 24 of this semiconductor chip 23 of coating and electric-conductor 22, wherein the height of this electric-conductor 22 is greater than the height of this semiconductor chip 23 and last bonding wire thereof, when encapsulating molding operation, make these electric-conductor 22 contacts at the die cavity top of encapsulating mould (not marking), after finishing the encapsulation molding operation, directly make the upper surface of this electric-conductor 22 expose this packing colloid 24; Also can be shown in Fig. 2 B ', this electric-conductor 22 is not resisted against the die cavity top of encapsulating mould, make packing colloid 24 cover this electric-conductor 22 earlier, again this packing colloid 24 is carried out thinning operation as grinding, make the upper surface flush of upper surface and this electric-conductor 22 of this packing colloid 24, thereby make these electric-conductor 22 upper surfaces expose this packing colloid 24.Cut on while edge respectively 20 of this substrates, cut this packing colloid 24 and electric-conductor 22, separate the electric-conductor 22 that is arranged on the adjacent substrate 20, and make these electric-conductor 22 side surfaces expose this packing colloid 24, wherein this depth of cut makes this electric-conductor 22 still keep electrical connection with plating bus 21 at least, in follow-up electroplating work procedure, nickel/deposition of gold is exposed on the electric-conductor 22 of packing colloid at this by this plating bus 21.
Shown in Fig. 2 D, utilize plating mode on electric-conductor 22 side surfaces that expose this packing colloid 24 and upper surface, to form for example metal level 25 of nickel/gold by plating bus 21.
Shown in Fig. 2 E, carry out cutting operation afterwards again, separate respectively this substrate 20, formation can be in the packing colloid side and end face the semiconductor package part of a plurality of extra electrical contacts is provided.
Embodiment 3
Fig. 3 is the substrate module sheet schematic diagram that uses among semiconductor package part of the present invention and the method for making embodiment 3 thereof.
As shown in the figure, present embodiment and the foregoing description are roughly the same, main difference is that this substrate module sheet 300 has a plurality of substrates 30, respectively be equipped with plating bus 31 between the upper and lower surface of this substrate 30, and respectively the upper surface of this substrate 30 is provided with electric connection point a plurality of as first electric connection pad 301 and second electric connection pad 302, wherein second electric connection pad 302 of 30 of this adjacent substrates connects together, and this first, second electric connection pad 301,302 is electrically connected to this plating bus 31.
The follow-up method of utilizing as above-mentioned embodiment, electric-conductor is connect on second electric connection pad of putting and being electrically connected between adjacent substrate, and put crystalline substance, the packing colloid, the packing colloid between each substrate of cutting and separating that form to cover chip and electric-conductor and electric-conductor, exposing on the electric-conductor of packing colloid electroplated metal layer and separating operation such as each substrate, formation can provide a plurality of semiconductor package parts that expose the packing colloid electrical contact.
Embodiment 4
Fig. 4 A to Fig. 4 E is the schematic diagram of semiconductor package part of the present invention and method for making embodiment 4 thereof.The semiconductor package part of present embodiment and method for making and the foregoing description are roughly the same, and main difference is using lead frame as chip carrier in the present embodiment.
Shown in Fig. 4 A, at first, the one lead frame module sheet 400 with many lead frames 40 is provided, respectively this lead frame 40 has chip carrier 401 and ring and is located at many electric connection points as pin 402 around this chip carrier 401, wherein this lead frame 40 can for example be the QFN lead frame, and respectively this lead frame 40 joins with connecting bus (connecting bus) 41.
Shown in Fig. 4 B, 402 of pins corresponding to adjacent wires frame 40 on this lead frame module sheet are provided with electric-conductor 42, and make this electric-conductor 42 electrically connect the pin 402 of adjacent wires frame 40, and on the chip carrier 401 of this lead frame 40 respectively, connect and put semiconductor chip 43, and make this semiconductor chip 43 be electrically connected to this pin 402 by many bonding wires.Then, can on this lead frame module sheet, form one and coat this semiconductor chip 43 and electric-conductor 42, and make these electric-conductor 42 upper surfaces expose packing colloid 44.
Shown in Fig. 4 C, packing colloid 44 on the cutting and separating adjacent wires frame 40 and electric-conductor 42 make these electric-conductor 42 side surfaces expose this packing colloid 44; Wherein, when this packing colloid 44 of cutting and electric-conductor 42, this depth of cut makes this electric-conductor 42 still keep electrical connection with this connecting bus 41 at least.
Shown in Fig. 4 D,, on electric-conductor 42 side surfaces that expose this packing colloid 44 and upper surface, form for example metal level 45 of nickel/gold with plating mode by connecting the respectively connecting bus 41 of these lead frame 40 pins 402.
Shown in Fig. 4 E, carry out cutting operation afterwards again, separate respectively this lead frame 40, formation can provide the semiconductor package part of a plurality of extra electrical contacts at packing colloid side surface and upper surface.
Fig. 5 A to Fig. 5 C is the schematic diagram that semiconductor package part of the present invention is used; Shown in Fig. 5 A, semiconductor package part 5a of the present invention can utilize electric-conductor 52 surfaces of exposing packing colloid 54 as electrical contact, electrically connects with socket (socket) contact jaw 56, and the CCM that can be loaded into socket is provided encapsulating structure; Shown in Fig. 5 B and Fig. 5 C, semiconductor package part 5b of the present invention, 5c also can utilize electric-conductor 52 surfaces of exposing packing colloid 54 as electrical contact, electrical thereon storehouse second semiconductor package part 57,58, wherein this second semiconductor package part 57,58 can be ball grid array (BGA) semiconductor package (shown in Fig. 5 B) or lead frame semiconductor package part (shown in Fig. 5 C).
In sum, semiconductor package part of the present invention and method for making thereof are to have on the chip carrier module sheet of many chip carriers, between corresponding each chip carrier electric-conductor is set, and make this electric-conductor electrically connect the electric connection point of adjacent chips carrier, and on this chip carrier respectively, connect and put and electrically connect semiconductor chip, carry out molding operation again, form the packing colloid of this semiconductor chip of coating and electric-conductor, then along respectively cutting between this chip carrier, separate the electric-conductor that is arranged on the adjacent chips carrier, make the part surface of this electric-conductor expose this packing colloid, wherein, this electric-conductor upper surface can directly expose this packing colloid after mold pressing, also this packing colloid can be carried out the thinning operation, the upper surface that exposes this electric-conductor, then form just like nickel/golden electrodeposited coating on the electric-conductor surface of exposing this packing colloid, follow-up with extraneous electric connection is provided, and then separate respectively this chip carrier, the electric-conductor that this packing colloid is exposed in utilization provides extra electrical contact, for the follow-up storehouse that can carry out packaging part, or utilize socket (socket) that packaging part is electrically connected to external device (ED), avoid limiting the problems such as use of electronic product, also can make electronic product have the excellent electrical property function simultaneously.
Claims (21)
1. the method for making of a semiconductor package part is characterized in that, the method for making of this semiconductor package part comprises:
The one chip carrier module sheet with many chip carriers is provided, and respectively this chip carrier is provided with a plurality of electric connection points;
Between corresponding each chip carrier electric-conductor is being set on this chip carrier module sheet, and is making this electric-conductor electrically connect the electric connection point of adjacent chips carrier, and on this chip carrier respectively, connecing and put and electrically connect semiconductor chip;
Encapsulate molding operation, on this chip carrier module sheet, form the packing colloid of this semiconductor chip of coating and electric-conductor; And
Cut along packing colloid between this chip carrier respectively and electric-conductor, separate the electric-conductor that is arranged on the adjacent chips carrier, and make this electric-conductor part surface expose this packing colloid, thereby separate respectively this chip carrier.
2. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, the method for making of this semiconductor package part also is included in when encapsulating molding operation, make this electric-conductor be resisted against the die cavity top of encapsulating mould, after finishing the encapsulation molding operation, directly make this electric-conductor upper surface expose this packing colloid.
3. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, the method for making of this semiconductor package part also comprises makes this packing colloid cover this electric-conductor earlier, again through this packing colloid of thinning, exposes this electric-conductor upper surface.
4. as the method for making of claim 1,2 or 3 described semiconductor package parts, it is characterized in that the method for making of this semiconductor package part also is included in the electric-conductor surface of exposing this packing colloid and forms a metal level.
5. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this chip carrier module sheet is a substrate module sheet, this chip carrier is thin spherical grid array or planar lattice array substrate, respectively this substrate by many laterally and directly to line of cut divided, laterally and directly be formed with plating bus at this simultaneously to the upper and lower surface of corresponding each substrate, line of cut place, this plating bus is located between the upper and lower surface of this substrate, and this plating bus is to extend the surface lines structure that is electrically connected to substrate.
6. the method for making of semiconductor package part as claimed in claim 5, it is characterized in that, this substrate upper surface is provided with many first electric connection pads and second electric connection pad, this substrate lower surface is provided with the 3rd electric connection pad, this first electric connection pad can pass through the conductive through hole electrical communication to the 3rd electric connection pad, and this first, second and third electric connection pad is electrically connected to this plating bus.
7. the method for making of semiconductor package part as claimed in claim 6 is characterized in that, this electric-conductor is second electric connection pad that is electrically connected to adjacent substrate, and this semiconductor chip is first electric connection pad that is electrically connected to this substrate.
8. the method for making of semiconductor package part as claimed in claim 6 is characterized in that, second electric connection pad between this adjacent substrate connects together.
9. the method for making of semiconductor package part as claimed in claim 5 is characterized in that, this electric-conductor is electrically connected to plating bus, forms metal level by plating mode on the electric-conductor surface of exposing this packing colloid.
10. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that this chip carrier module sheet is a lead frame module sheet, this chip carrier is a lead frame, respectively this lead frame has chip carrier and is located on this chip carrier many pins on every side, and respectively this lead frame joins with connecting bus.
11. the method for making of semiconductor package part as claimed in claim 1 is characterized in that, this semiconductor package part can utilize the electric-conductor surface of exposing packing colloid as electrical contact, electrically connects with the socket contact jaw.
12. the method for making as claim 2 or 3 described semiconductor package parts is characterized in that, this semiconductor package part can utilize the electric-conductor surface of exposing packing colloid as electrical contact, electrical thereon another semiconductor package part of storehouse.
13. a semiconductor package part is characterized in that, this semiconductor package part comprises:
One chip carrier, this chip carrier are provided with a plurality of electric connection points;
At least one semiconductor chip connects and puts and be electrically connected to this chip carrier;
Many electric-conductors connect and put and be electrically connected to this electric connection point; And
One packing colloid is formed on this chip carrier, coats this semiconductor chip and electric-conductor, and makes this electric-conductor side surface expose this packing colloid at least.
14. semiconductor package part as claimed in claim 13 is characterized in that, this packing colloid upper surface of this semiconductor package part and this electric-conductor upper surface flush make this electric-conductor upper surface expose this packing colloid.
15. as claim 13 or 14 described semiconductor package parts, it is characterized in that this semiconductor package part also comprises a metal level, be formed at the electric-conductor surface of exposing this packing colloid.
16. semiconductor package part as claimed in claim 13 is characterized in that, this chip carrier is ball grid array or planar lattice array substrate.
17. semiconductor package part as claimed in claim 16, it is characterized in that, this substrate upper surface is provided with many first electric connection pads and second electric connection pad, this substrate lower surface is provided with the 3rd electric connection pad, and this first electric connection pad can be by the conductive through hole electrical communication to the 3rd electric connection pad.
18. semiconductor package part as claimed in claim 17 is characterized in that, this electric-conductor is electrically connected to this second electric connection pad, and this semiconductor chip is electrically connected to this first electric connection pad.
19. semiconductor package part as claimed in claim 13 is characterized in that, this chip carrier is a lead frame, and respectively this lead frame has chip carrier and is located on this chip carrier many pins on every side.
20. semiconductor package part as claimed in claim 13 is characterized in that, this semiconductor package part can utilize the electric-conductor surface of exposing packing colloid as electrical contact, electrically connects with the socket contact jaw.
21. semiconductor package part as claimed in claim 14 is characterized in that, this semiconductor package part can utilize the electric-conductor surface of exposing packing colloid as electrical contact, electrical thereon another semiconductor package part of storehouse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100918502A CN101090077A (en) | 2006-06-12 | 2006-06-12 | Semiconductor package and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100918502A CN101090077A (en) | 2006-06-12 | 2006-06-12 | Semiconductor package and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101090077A true CN101090077A (en) | 2007-12-19 |
Family
ID=38943344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100918502A Pending CN101090077A (en) | 2006-06-12 | 2006-06-12 | Semiconductor package and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101090077A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664170A (en) * | 2012-04-19 | 2012-09-12 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN104392968A (en) * | 2008-11-21 | 2015-03-04 | 先进封装技术私人有限公司 | Semiconductor substrate |
| CN104505351A (en) * | 2014-12-30 | 2015-04-08 | 中国科学院微电子研究所 | Preparation method of lateral-interconnection package on package structure |
| CN105513976A (en) * | 2015-12-02 | 2016-04-20 | 上海凯虹电子有限公司 | Semiconductor packaging method, packaging body and packaging unit |
| CN110349857A (en) * | 2019-08-01 | 2019-10-18 | 合肥矽迈微电子科技有限公司 | Side wall reveals copper encapsulating structure and its manufacture craft |
-
2006
- 2006-06-12 CN CNA2006100918502A patent/CN101090077A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392968A (en) * | 2008-11-21 | 2015-03-04 | 先进封装技术私人有限公司 | Semiconductor substrate |
| US9847268B2 (en) | 2008-11-21 | 2017-12-19 | Advanpack Solutions Pte. Ltd. | Semiconductor package and manufacturing method thereof |
| CN102664170A (en) * | 2012-04-19 | 2012-09-12 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN102664170B (en) * | 2012-04-19 | 2015-06-17 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN104505351A (en) * | 2014-12-30 | 2015-04-08 | 中国科学院微电子研究所 | Preparation method of lateral-interconnection package on package structure |
| CN105513976A (en) * | 2015-12-02 | 2016-04-20 | 上海凯虹电子有限公司 | Semiconductor packaging method, packaging body and packaging unit |
| CN105513976B (en) * | 2015-12-02 | 2018-04-17 | 上海凯虹电子有限公司 | Method for packaging semiconductor, packaging body and encapsulation unit |
| CN110349857A (en) * | 2019-08-01 | 2019-10-18 | 合肥矽迈微电子科技有限公司 | Side wall reveals copper encapsulating structure and its manufacture craft |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207781575U (en) | Encapsulated electronic device | |
| US7872343B1 (en) | Dual laminate package structure with embedded elements | |
| CN101252096B (en) | Chip package structure and preparation method thereof | |
| US20070278701A1 (en) | Semiconductor package and method for fabricating the same | |
| US20210050226A1 (en) | Method of manufacturing semiconductor devices and corresponding semiconductor device | |
| CN101335217B (en) | Semiconductor package and manufacturing method thereof | |
| CN102005432B (en) | Packaging structure with four pin-less sides and packaging method thereof | |
| US8487424B2 (en) | Routable array metal integrated circuit package fabricated using partial etching process | |
| US20060223238A1 (en) | Leadless semiconductor package and manufacturing method thereof | |
| CN105720034B (en) | Lead frame, semiconductor device | |
| WO2007095381A2 (en) | A sip module with a single sided lid | |
| EP1189273A3 (en) | Semiconductor device and production process | |
| US20040238923A1 (en) | Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same | |
| CN101090077A (en) | Semiconductor package and its manufacturing method | |
| CN1855450A (en) | High-heat loss rate semiconductor sealer and its production | |
| TW201705426A (en) | Resin-encapsulated semiconductor device and method of manufacturing the same | |
| CN108183091A (en) | A kind of encapsulating structure and its process | |
| TWM558999U (en) | Light-emitting package component | |
| CN1808702A (en) | Semi-conductor package structure and mfg. method thereof | |
| KR20230054602A (en) | PACKAGE WITH COMPARTMENTalized LID FOR Heat Spreader AND EMI SHIELD | |
| CN103107145A (en) | Semiconductor package, prefabricated lead frame and manufacturing method thereof | |
| CN101378023B (en) | Semiconductor package and manufacturing method thereof | |
| CN110890284A (en) | Chip stacking and packaging structure and process method thereof | |
| CN103824820A (en) | Leadframe area array packaging technology | |
| CN102208355B (en) | Square planar guide-pin-free semiconductor packaging part and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |