CN1808702A - Semi-conductor package structure and mfg. method thereof - Google Patents
Semi-conductor package structure and mfg. method thereof Download PDFInfo
- Publication number
- CN1808702A CN1808702A CNA2005100025387A CN200510002538A CN1808702A CN 1808702 A CN1808702 A CN 1808702A CN A2005100025387 A CNA2005100025387 A CN A2005100025387A CN 200510002538 A CN200510002538 A CN 200510002538A CN 1808702 A CN1808702 A CN 1808702A
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- semiconductor package
- electrode pad
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
This invention relates to one semiconductor sealing structure and its process method, wherein, the structure comprises chip to form multiple electrode welding pad by action surface and the baseboard with first and second surfaces; the baseboard has at least one through hole to connect the weld pad wire to the second surface of the baseboard and to connect the chip electrode weld pad to the baseboard first surface through the conductive protruding block; then processing the sealed pressing procedure to form first and second sealed glue parts with multiple weld balls on the second surface.
Description
Technical field
The invention relates to a kind of semiconductor package and method for making thereof, particularly about a kind of windowing type ball grid array (WBGA) semiconductor package and method for making thereof.
Background technology
Semiconductor package part is a kind of electronic installation that carries as the active member of semiconductor chip etc., structure mainly makes at least one chip connect to put the side at substrate, and borrow many to be electrically connected to this substrate as conducting elements such as bonding wires, and chip and bonding wire are to coat with the packing colloid that resin material (as epoxy resin etc.) is made, and avoid being subjected to extraneous aqueous vapor and pollutant to encroach on.This semiconductor package part can comprise that also a plurality of soldered balls that are the array way arrangement plant the opposite side at substrate, and it is relative with a side that is equipped with chip and bonding wire.This semiconductor package part with soldered ball is called ball grid array (ball grid array, BGA) packaging part, and pass through this soldered ball as I/O (input/output, I/O) end, make carry the chip be located in the packaging part can with external device, (printed circuit board PCB) becomes electrical connection as printed circuit board (PCB).The height of semiconductor package part comprises thickness, substrate thickness and the ball height of the packing colloid that is used for coating chip and bonding wire, and this makes overall package part size be difficult to further dwindle.
In order effectively to dwindle the semiconductor package part size, as United States Patent (USP) the 6th, 218, a kind of window type (window-type) packaging part of No. 731 propositions.Fig. 1 E promptly shows a kind of existing windowing type ball grid array packaging part.As shown in the figure, semiconductor chip 10 borrows adhesive 13 to connect the perforate 103 of putting on the upper surface 100 of substrate 1 and covering substrate 10.This chip 10 also borrows the electrode pad 11 on it to be electrically connected to the lower surface 101 of substrate 10 by many bonding wires 14 that are applied in this perforate 103.Simultaneously, chip 10 and bonding wire 14 respectively by last packing colloid 15 and down packing colloid 16 coat, and a plurality of soldered ball 17 plants be not formed with the zone of packing colloid 16 down on substrate 1 lower surface 101.
Above-mentioned windowing type ball grid array packaging part is that the process with Figure 1A to Fig. 1 E makes.
At first, shown in Figure 1A, provide a substrate film Z who is made up of many substrates 1, wherein each substrate 1 has a perforate 103 that runs through wherein, and this perforate 103 is preferably rectangular.Then, carry out putting crystalline substance (chip-bonding) operation and bonding wire (wire-bonding) operation.In putting brilliant operation, at least one chip 10 borrows adhesive 13 to connect the perforate 103 of putting on the upper surface 100 of each substrate 1 and covering this substrate 1, then, in the bonding wire operation, form many bonding wires 14 in the perforate 103 of each substrate 1, make the electrode pad 11 of chip on 10 by its be electrically connected to the lower surface 101 of counterpart substrate 1 by this bonding wire 14.
Shown in Figure 1B, an encapsulating mould is provided, have a patrix 18 and a counterdie 19, this patrix 18 is formed with a upper mould cave 180, and this counterdie 19 is formed with the perforate 103 that many following die cavitys 190 respectively correspond to a row substrate 1.The size of this upper mould cave 180 is enough to take in all and connects the chip of putting on substrate 1 10.The size of each time die cavity 190 covers the perforate 103 of all substrates 1 of this respective column and holds bonding wire 14 banks of giving prominence on substrate 1 lower surface 101.This encapsulating mould touches on the substrate film Z, patrix 18 is connect put on the upper surface 100 of substrate 1, and counterdie 19 connects to be put on the lower surface 101 of substrate 1.
Shown in Fig. 1 C, carry out mold pressing (molding) operation, resin material (as epoxy resin) is injected the following die cavity 190 of counterdie 19, form many following packing colloids 16, each time packing colloid 16 is filled in the perforate 103 of respective column and coats corresponding bonding wire 14, and resin material injected the upper mould cave 180 of patrix 18, form on one packing colloid 15 and be used to coat all and connect the chip of putting on substrate 1 10.
After finishing first and second molding operation, on substrate film Z, remove patrix 18 and counterdie 19, the zone that is covered by following packing colloid 16 on the lower surface 101 of substrate 1 is not exposed.
Shown in Fig. 1 D, plant a plurality of soldered balls 17 and on the lower surface 101 of substrate 1, expose the zone.At last, when finish above-mentioned put crystalline substance, bonding wire, mold pressing and plant the ball operation after, carry out all single (singulation) operations, packing colloid 15 in the cutting, substrate film Z and down packing colloid 16 to separate each substrate 1, forms many have singly from windowing type ball grid array formula (WBGA) semiconductor package part (shown in Fig. 1 E) of substrate 1, chip 10 and a plurality of soldered ball 14.
Yet the electrode pad that above-mentioned WBGA packaging part only is suitable on the chip is concentrated central authorities or the ad-hoc location that is arranged in chip, shown in Fig. 2 A to Fig. 2 C.If the arrangement of the electrode pad on the chip shown in Fig. 3 A to Fig. 3 D, is not just concentrated and is arranged in middle position, and when being dispersed in each zone of chip simultaneously, then can make the operation of WBGA packaging part meet with many difficulties.
At first, if the electrode pad on the chip is not only concentrated and is arranged on central authorities (as United States Patent (USP) the 5th, 777, shown in No. 391) and when also being distributed in simultaneously other zone, promptly need electrode pad distributing position that should chip is provided with the corresponding opening that runs through for the substrate of this chip of carrying, pass through this substrate for bonding wire and run through electrode pad and the substrate that opening electrically connects this chip, yet, can cause the difficulty on the more complicated and operation of the electrical layout designs of substrate because of these run through the setting of opening; In addition, the base openings structure of substrate more at most can become fragile, and the space of energy design circuit can further be reduced in the substrate, and this has influence on the cost and the acceptance rate of quality, usefulness and the operation thereof of packaging part.
Moreover, be that as shown in Figure 3A shape is when arranging for example when the electrode pad on the chip acting surface distributes, then this chip finish put crystalline substance and routing operation after, profile when carrying out mold pressing procedure will be shown in Fig. 4 A, wherein counterdie 49 must design according to the substrate perforate 403 and the position of bonding wire 44, just offer corresponding die cavity, thereby, when substrate perforate 403 and bonding wire 44 many more, make the design of counterdie 49 more complicated, and in response to various substrate perforate 403 and bonding wire 44, must offer various counterdies 49, this can expend many costs; When carrying out mold pressing, also can too much run through opening because of this substrate is provided with in addition, make and can reduce for the part of counterdie 49 clampings, this is with regard to the probability that improves the glue that overflows, the reliability that reduces packaging part.
Moreover, see also Fig. 4 B, the complete WBGA structure that presents after its demonstration is finished mold pressing and planted ball, the size of this soldered ball 47 is subjected to the restriction of the space D of 46 of each time packing colloids, therefore, if substrate perforate 403 is many more, space D can be tending towards reduction, cause regional limited that soldered ball 47 can graft, the soldered ball cloth that can have a strong impact on this packaging part is planted space and design.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package and method for making thereof, utilize conductive projection and bonding wire that the combination of the electric connection between chip and substrate is provided, can reduce the number of WBGA base plate for packaging perforate, and then reduce the complexity of mold design and save the cost of packaging process.
Another object of the present invention is to provide a kind of semiconductor package and method for making thereof, utilize conductive projection and bonding wire that the combination of the electric connection between chip and substrate is provided, reduce the number of WBGA base plate for packaging perforate, and then reduce the complexity and the intensity of keeping board structure of substrate design and operation thereof.
Another object of the present invention is to provide a kind of semiconductor package and method for making thereof, avoid reducing the mould holding requisite space, and then the excessive glue generation probability that causes when reducing mold pressing, keep the acceptance rate of operation.
Another object of the present invention is to provide a kind of semiconductor package and method for making thereof, and the proper area that provides soldered ball to graft is avoided influencing soldered ball cloth and planted meter.
Another object of the present invention is to provide a kind of semiconductor package and method for making thereof, utilizes conductive projection and bonding wire that the combination of the electric connection between chip and substrate is provided, and improves the electrical conduction function of electronic component.
For reaching above-mentioned and other purpose, the invention provides a kind of semiconductor package, this structure comprises that one has the substrate of first surface and opposing second surface, and this substrate is formed with at least one opening that runs through; The chip that has a plurality of electrode pad on one acting surface, the electrode pad of this chip of part connects by conductive projection and puts and be electrically connected on this substrate first surface, and the electrode pad of this chip of part is electrically connected to this substrate second surface by the bonding wire that passes this substrate and run through opening; One is formed on first packing colloid on this substrate first surface, coats this semiconductor chip; One is formed on second packing colloid on this substrate second surface, coats this bonding wire; And a plurality of soldered balls, plant and put on this substrate second surface.
This substrate has first surface and opposing second surface, and this substrate forms at least one opening that runs through that penetrates first surface and second surface, on this substrate first surface and second surface, a plurality of electric connection pads are set, the electric connection pad of this substrate first surface is that the partial electrode weld pad on the corresponding chip distributes, do electric connection by conductive projection and this chip, the electric connection pad of substrate second surface is then for borrowing bonding wire to do electric connection with the partial electrode weld pad of chip.Packing colloid has two parts, a part is formed on first packing colloid of this substrate first surface, coats this semiconductor chip, and another part then is formed on second packing colloid on this substrate second surface, coat this bonding wire, a plurality of soldered balls are then planted and are put on the second surface of this substrate.
A kind of semiconductor package method for making of the present invention, this method for making mainly comprises: provide acting surface chip that forms a plurality of electrode pad and the substrate with first surface and relative second surface, and opening is at least always worn in this substrate formation; With cover crystal type will the part this chip electrode pad connect by conductive projection on the first surface of putting and be electrically connected to this substrate, and will the part this chip electrode pad by passing the bonding wire that this substrate runs through opening, be electrically connected to this substrate second surface; Carry out the encapsulating die press operation, on this substrate second surface, form second packing colloid that coats this bonding wire on this substrate first surface, to form first packing colloid that coats this chip respectively, to reach; And on this substrate second surface, plant and put a plurality of soldered balls.
Therefore, semiconductor package of the present invention and method for making thereof are applied in windowing type ball grid array (WBGA) semiconductor package part, when making chip be electrically connected to substrate, the electrode pad of chip part is covered crystal type by the conductive projection utilization earlier to be connect and puts and be electrically connected to the substrate first surface, again remaining chip electrode weld pad is electrically connected to the substrate second surface by bonding wire, by the area dividing of chip power utmost point bond pad locations and the combination that distributes conductive projection and bonding wire, reach the purpose that reduces base openings, and then reduce the complexity of mold design and save the cost of encapsulation, the difficulty of substrate design and operation thereof is fallen, keep the intensity of board structure, avoid reducing the mould holding requisite space, and then the excessive glue generation probability that causes when reducing mold pressing, keep the acceptance rate of operation, by reducing the opening of substrate, also can be the proper area that soldered ball grafts to be provided, avoid soldered ball to graft the restriction of layout.
Description of drawings
Figure 1A to Fig. 1 E is existing open window type ball grid array semiconductor packaging piece operation schematic diagram;
Fig. 2 A to Fig. 2 C is the floor map that the electrode pad of chip concentrates on central distribution;
Fig. 3 A to Fig. 3 D is that the electrode pad of chip is arranged in chip central authorities and all the other regional floor map simultaneously;
Fig. 4 A has encapsulating structure as Fig. 3 A chips in the mold pressing procedure generalized section;
Fig. 4 B is the complete WBGA encapsulating structure generalized section that presents after finishing mold pressing and planting ball;
Fig. 5 A to Fig. 5 D is the method for making generalized section of semiconductor package of the present invention;
Fig. 6 is the generalized section of semiconductor package embodiment 2 of the present invention.
Embodiment
Embodiment 1
See also Fig. 5 D, it shows the profile of semiconductor package embodiment of the present invention.This semiconductor package has elements such as substrate 5, chip 50, conductive projection 520, bonding wire 54, packing colloid 55,56 and soldered ball 57.
This substrate 5 has first surface 501 and opposing second surface 502, and this substrate 5 be formed with at least one penetrate first surface 501 and second surface 502 run through opening 503.
This chip 50 can for example be the form shown in Fig. 3 B, this chip 50 has acting surface, acting surface is provided with a plurality of electrode pad 51,52, being distributed as of electrode pad 51,52 is cross, this electrode pad the 51, the 52nd is respectively and carries out follow-uply covering brilliant operation and routing procedure and being divided into the 511 and second electrode pad zone 521, first electrode pad zone, wherein this first electrode pad zone 511 is that predetermined electrode pad 51 of carrying out the routing operation constitutes, and this second electrode pad zone 521 is that the predetermined electrode pad 52 of covering crystalline substance constitutes.
Moreover, these substrate 5 first surfaces 501 and second surface 502 are formed with a plurality of electric connection pads 500,505, and the electric connection pad 500 of this substrate first surface 501 is able to be electrically connected to the part electric connection pad 505 of this substrate second surface 502 by being arranged in this substrate for example conductive blind hole (via) or plated-through-hole interlayer conductive structures 504 such as (PTH).In addition, the electric connection pad 500 of this substrate first surface 501 is that second electrode pad zone 521 of corresponding chip 50 top electrode weld pads 52 distributes, and directly doing electric connection by conductive projection 520 and this chip 50, and then improves electrical functionality.505 confessions of the electric connection pad of substrate second surface 502 borrow bonding wire 54 to do electric connection with first electrode pad zone 511 of chip 50 top electrode weld pads 51.
Packing colloid has two parts, a part is formed in first packing colloid 55 of these substrate 5 first surfaces 501, so as to coating this semiconductor chip 50, another part then is formed on second packing colloid 56 on these substrate 5 second surfaces 502, so as to coating this bonding wire 54.
These 57 of a plurality of soldered balls are planted and are put on the solder ball pad 506 of the second surface 502 of this substrate 5, provide this semiconductor chip 50 to be electrically connected to external device (ED).
Also see also Fig. 5 A to Fig. 5 D, it shows the method for making generalized section of semiconductor package of the present invention.
Shown in Fig. 5 A, provide acting surface to be formed with a plurality of electrode pad 51,52 chip 50 and substrate 5 with first surface 501 and relative second surface 502, this substrate 5 form at least one penetrate first surface 501 and second surface 502 run through opening 503, and this substrate is formed with a plurality of electric connection pads 500 on its first and second surface, 505, the electric connection pad 500 of this substrate first surface 501 can be by being arranged in this substrate for example conductive blind hole (via) or plated-through-hole interlayer conductive structures 504 such as (PTH), be electrically connected to the part electric connection pad 505 of this substrate second surface 502, the electrode pad 52 that supplies this chip 50 is by covering crystal type, be electrically connected on these substrate 5 first surfaces 501 electric connection pad 500 by conductive projection 520, and make this chip 50 close the side that this substrate runs through opening 503, make the electrode pad 51 of this chip 50 be emerging in this and run through opening 503.
This chip 50 for example can adopt the semiconductor chip shown in Fig. 3 B (but not as limit, can be that all the other non-only central authorities concentrate the chip that electrode pad is arranged in addition), this electrode pad 51,52 is carried out the subsequent handling routing respectively and is covered brilliant operation, be divided into the 511 and second electrode pad zone 521, first electrode pad zone, wherein this first electrode pad zone 511 is that predetermined electrode pad 51 of carrying out the routing operation constitutes, and this second electrode pad zone 521 is that the predetermined electrode pad 52 of covering crystalline substance constitutes.The second electrode pad zone 521 of these chip 50 electrode pad 52 is to be electrically connected to this substrate 5 by conductive projection 520, the form of this conductive projection 520 can be scolding tin contact form or gold bump form, for example this electrode pad 52 is pre-soldering tin material to be set through reflow on the electric connection pad 500 that solder bump is engaged in substrate first surface 501 simultaneously by forming thereon, this chip 50 is connect put and be electrically connected to substrate first surface 501; Perhaps also can utilize the lower column of cost of manufacture to engage (stud bond) operation, it mainly is that capillary (capillary) by bonding equipment inserts and puts gold thread, and burn till spheroid at this gold thread one end, capillary is depressed on the electrode pad 52 of chip 50, so as on the electrode pad 52 of this chip 50, forming gold bump, and then make the second electrode pad zone 521 of this chip 50 be able to connect to put and be electrically connected on these substrate 5 first surfaces 501 by this gold bump.
See also Fig. 5 B, the first electrode pad zone 511 of the electrode pad that runs through opening 503 51 of this substrate 5 will be emerging on this chip 50, by passing the bonding wire that runs through opening 503 54 of substrate 5, be electrically connected to the electric connection pad 505 of substrate second surface 502.
See also Fig. 5 C, then carry out the encapsulating die press operation, it mainly provides an encapsulating mould with a patrix 58 and a counterdie 59, this patrix 58 is formed with upper mould cave 580, this counterdie 59 is formed with die cavity 590 down, the size of this upper mould cave 580 is enough to take in and connects the chip of putting on substrate 5 50, the size of this time die cavity 590 covers this counterpart substrate 5 and runs through opening 503 and hold bonding wire 54 banks of giving prominence on substrate 5 second surfaces 502, in resin material (as epoxy resin) injection, following die cavity 580, in 590, on these substrate 5 second surfaces 502, form second packing colloid 56 that coats this bonding wire 54 so as on these substrate 5 first surfaces 501, forming first packing colloid 55 that coats this chip 50 respectively, reaching.In the present embodiment, though the electrode pad distributed areas on the chip acting surface are big, but utilize the present invention with the electrode pad of chip (on every side) part utilize earlier cover crystal type and be electrically connected to the substrate first surface after, electrode pad with chip (central authorities) part is electrically connected to the substrate second surface by the routing mode again, therefore can be as existing WBGA packaging part, only offering the corresponding opening that runs through in substrate center gets final product, so can utilize mould commonly used to encapsulate mold pressing equally, so as to the saving cost, and then can provide the follow-up layout design of carrying out soldered ball than large space that on the substrate second surface, has.
See also Fig. 5 D, on the solder ball pad 506 that is not coated on substrate 5 second surfaces 502, plant at last and put a plurality of soldered balls 57 by second packing colloid 56.In addition, it should be noted in the operation of the present invention that the making of this semiconductor package can also can be that the encapsulating structure that is batch form carries out operation at single encapsulating structure.
Embodiment 2
See also Fig. 6, it is the generalized section that semiconductor package second of the present invention is implemented attitude, the structure and the operation of it and the foregoing description 1 are roughly the same, main difference is that the electrode pad on this chip acting surface can be according to distributing position, actual states such as spacing and operation demand take in, decision is covered crystal type at the electrode pad employing of part, the electrode pad of another part adopts the routing mode to be electrically connected to substrate, for example in Fig. 6, consider if the electrode pad of chip 60 middle sections 62 distributes comparatively sparse, then can utilize cost of manufacture lower, and the column that step is comparatively easy engages (stud bond) operation, on the electrode pad that is positioned at chip central authorities, directly plant golden projection, and connect and put and be electrically connected to substrate 6 first surfaces 601 to cover crystal type; Relatively, remaining electrode weld pad 61 positions beyond these substrate 6 corresponding chip 60 central areas are provided with runs through opening 603, and the electrode pad 61 that makes this chip 60 is emerging in this and is run through opening 603, by the routing mode, electrically connect this electrode pad 61 and substrate second surface 602 to pass this bonding wire that runs through opening 603 64.Thereafter, carry out sealing again and plant the ball operation, in addition, this encapsulating structure is can adopt single or a batch mode to make equally, and when batch mode of employing was made, still needing, it was single to form a plurality of encapsulating structures unit to cut.
Therefore, semiconductor package of the present invention and method for making thereof mainly are in windowing type ball grid array formula (WBGA) semiconductor package part, because when being formed on electrode pad distributed areas on the chip acting surface and not only concentrating on central authorities, when making chip be electrically connected to substrate, the electrode pad of chip part is covered crystal type by conductive projection with utilization earlier, connect and put and be electrically connected to the substrate first surface, again remaining chip electrode weld pad is electrically connected to the substrate second surface by bonding wire, reduce the setting that substrate runs through opening, having solved existing windowing type ball grid array (WBGA) semiconductor package part offers a plurality of when running through opening in substrate, substrate circuit layout that causes and making complexity problem, also avoided simultaneously follow-up and carried out in the Chip Packaging mold pressing procedure improving and the mold pressing problem that the glue probability increases of overflowing, thereby can not influence follow-up laying at the substrate surface soldered ball for the mould development cost of manufacture that cooperates being provided with of the many openings of substrate to be caused.
Claims (13)
1. the method for making of a semiconductor package is characterized in that, this method for making comprises:
Provide acting surface chip that forms a plurality of electrode pad and substrate, and opening is at least always worn in this substrate formation with first surface and relative second surface;
With cover crystal type will the part this chip electrode pad connect by conductive projection on the first surface of putting and be electrically connected to this substrate, and will the part this chip electrode pad by passing the bonding wire that this substrate runs through opening, be electrically connected to this substrate second surface;
Carry out the encapsulating die press operation, on this substrate second surface, form second packing colloid that coats this bonding wire on this substrate first surface, to form first packing colloid that coats this chip respectively, to reach; And
On this substrate second surface, plant and put a plurality of soldered balls.
2. the method for making of semiconductor package as claimed in claim 1 is characterized in that, this encapsulating structure is an open window type ball grid array semiconductor packaging piece.
3. the method for making of semiconductor package as claimed in claim 1, it is characterized in that, this substrate forms a plurality of electric connection pads on its first and second surface, for the partial electrode weld pad of chip by covering crystal type, being electrically connected to the electric connection pad of this substrate first surface by conductive projection, and make this chip close the side that this substrate runs through opening, make the remaining electrode weld pad of this chip be emerging in this and run through opening, utilize through this and run through the bonding wire of opening, make the partial electrode weld pad of chip be electrically connected to the electric connection pad of substrate second surface.
4. the method for making of semiconductor package as claimed in claim 1 is characterized in that, the form of this conductive projection can be scolding tin contact form or gold bump form.
5. the method for making of semiconductor package as claimed in claim 1, it is characterized in that, the chip bonding of this chip and substrate is to form solder bump on the electrode pad of chip, be engaged in simultaneously pre-soldering tin material is set on the substrate first surface, through reflow this chip is connect and put and be electrically connected to the substrate first surface.
6. the method for making of semiconductor package as claimed in claim 1, it is characterized in that, this chip can utilize column to engage operation with the chip bonding of substrate, insert and put gold thread by capillary, and burn till spheroid at this gold thread one end capillary is depressed on the electrode pad of chip, so as on the electrode pad of this chip, forming gold bump, and then make this chip be able to connect to put and be electrically connected on this substrate first surface by this gold bump.
7. the method for making of semiconductor package as claimed in claim 1 is characterized in that, the making of this semiconductor package can or be the encapsulating structure of batch form at single encapsulating structure.
8. a semiconductor package is characterized in that, this structure comprises:
One has the substrate of first surface and opposing second surface, and this substrate is formed with at least one opening that runs through;
The chip that has a plurality of electrode pad on one acting surface, the electrode pad of this chip of part connects by conductive projection and puts and be electrically connected on this substrate first surface, and the electrode pad of this chip of part is electrically connected to this substrate second surface by the bonding wire that passes this substrate and run through opening;
One is formed on first packing colloid on this substrate first surface, coats this semiconductor chip;
One is formed on second packing colloid on this substrate second surface, coats this bonding wire; And
A plurality of soldered balls are planted and are put on this substrate second surface.
9. semiconductor package as claimed in claim 8 is characterized in that this encapsulating structure is an open window type ball grid array semiconductor packaging piece.
10. semiconductor package as claimed in claim 8, it is characterized in that, this substrate is formed with a plurality of electric connection pads on its first and second surface, for the partial electrode weld pad of chip by covering crystal type, being electrically connected to the electric connection pad of this substrate first surface by conductive projection, and make this chip close the side that this substrate runs through opening, make the remaining electrode weld pad of this chip be emerging in this and run through opening, utilize through this and run through the bonding wire of opening, make the partial electrode weld pad of chip be electrically connected to the electric connection pad of substrate second surface.
11. semiconductor package as claimed in claim 8 is characterized in that, the form of this conductive projection can be scolding tin contact form or gold bump form.
12. semiconductor package as claimed in claim 8, it is characterized in that, this chip can be engaged in simultaneously at formation solder bump on the electrode pad of chip with engaging of substrate pre-soldering tin material is set on the substrate first surface, through reflow this chip is connect and puts and be electrically connected to the substrate first surface.
13. semiconductor package as claimed in claim 8, it is characterized in that, this chip can utilize column to engage operation with engaging of substrate, insert and put gold thread by capillary, and burn till spheroid at this gold thread one end, capillary is depressed on the electrode pad of chip, on the electrode pad of this chip, forms gold bump, and then make this chip be able to connect to put and be electrically connected on this substrate first surface by this gold bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100025387A CN1808702A (en) | 2005-01-20 | 2005-01-20 | Semi-conductor package structure and mfg. method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100025387A CN1808702A (en) | 2005-01-20 | 2005-01-20 | Semi-conductor package structure and mfg. method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1808702A true CN1808702A (en) | 2006-07-26 |
Family
ID=36840508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100025387A Pending CN1808702A (en) | 2005-01-20 | 2005-01-20 | Semi-conductor package structure and mfg. method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1808702A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866889B (en) * | 2009-04-17 | 2012-06-27 | 南茂科技股份有限公司 | Substrate-free chip packaging and manufacturing method thereof |
| CN102612743A (en) * | 2009-11-19 | 2012-07-25 | 住友电木株式会社 | Semiconductor device |
| CN103426870A (en) * | 2012-05-16 | 2013-12-04 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| WO2016074176A1 (en) * | 2014-11-12 | 2016-05-19 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
| CN110783316A (en) * | 2018-07-30 | 2020-02-11 | 台湾积体电路制造股份有限公司 | Device with magnetic shield and manufacturing method thereof |
-
2005
- 2005-01-20 CN CNA2005100025387A patent/CN1808702A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866889B (en) * | 2009-04-17 | 2012-06-27 | 南茂科技股份有限公司 | Substrate-free chip packaging and manufacturing method thereof |
| CN102612743A (en) * | 2009-11-19 | 2012-07-25 | 住友电木株式会社 | Semiconductor device |
| CN103426870A (en) * | 2012-05-16 | 2013-12-04 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| WO2016074176A1 (en) * | 2014-11-12 | 2016-05-19 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
| US9778688B2 (en) | 2014-11-12 | 2017-10-03 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
| CN110783316A (en) * | 2018-07-30 | 2020-02-11 | 台湾积体电路制造股份有限公司 | Device with magnetic shield and manufacturing method thereof |
| US11404383B2 (en) | 2018-07-30 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic shielding material with insulator-coated ferromagnetic particles |
| US11990423B2 (en) | 2018-07-30 | 2024-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic shielding material with insulator-coated ferromagnetic particles |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8283767B1 (en) | Dual laminate package structure with embedded elements | |
| US6835599B2 (en) | Method for fabricating semiconductor component with multi layered leadframe | |
| US7608921B2 (en) | Multi-layer semiconductor package | |
| US6777788B1 (en) | Method and structure for applying thick solder layer onto die attach pad | |
| KR101050402B1 (en) | Semiconductor Multipackage Modules Including Processor and Memory Package Assemblies | |
| US6664615B1 (en) | Method and apparatus for lead-frame based grid array IC packaging | |
| US5962810A (en) | Integrated circuit package employing a transparent encapsulant | |
| US20070278701A1 (en) | Semiconductor package and method for fabricating the same | |
| US8115288B2 (en) | Lead frame for semiconductor device | |
| KR19990006158A (en) | Ball grid array package | |
| US20060145362A1 (en) | Semiconductor package and fabrication method of the same | |
| CN1808702A (en) | Semi-conductor package structure and mfg. method thereof | |
| CN1287452C (en) | Windowing ball grid array semiconductor packaging element with wire-holder as carrier and making method thereof | |
| CN1855450A (en) | High-heat loss rate semiconductor sealer and its production | |
| US20020003308A1 (en) | Semiconductor chip package and method for fabricating the same | |
| CN101090077A (en) | Semiconductor package and its manufacturing method | |
| KR19990024255U (en) | Stacked Ball Grid Array Package | |
| KR20010025874A (en) | Multi-chip semiconductor package | |
| JP4038021B2 (en) | Manufacturing method of semiconductor device | |
| KR100247641B1 (en) | Package and method of manufacturing the same | |
| KR20070019359A (en) | Two sided mount type substrate having window for encapsulating and method for manufacturing a multi-chip package using the same | |
| CN1228838C (en) | Structure reinforced open window type semiconductor packaging unit | |
| CN115966537A (en) | Bridge chip, fan-out type packaging structure and corresponding packaging method | |
| CN114864526A (en) | Semiconductor packaging structure and semiconductor packaging method | |
| CN101051629A (en) | Semiconductor package structure and its producing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20060726 |