CN103426870A - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

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Publication number
CN103426870A
CN103426870A CN2012101815937A CN201210181593A CN103426870A CN 103426870 A CN103426870 A CN 103426870A CN 2012101815937 A CN2012101815937 A CN 2012101815937A CN 201210181593 A CN201210181593 A CN 201210181593A CN 103426870 A CN103426870 A CN 103426870A
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China
Prior art keywords
bonding wire
semiconductor
semiconductor package
package part
wire section
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CN2012101815937A
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Chinese (zh)
Inventor
唐绍祖
蔡瀛洲
蓝章益
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN103426870A publication Critical patent/CN103426870A/en
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Abstract

A semiconductor package and a method for fabricating the same, the semiconductor package comprising: the semiconductor module comprises a substrate with a plurality of electric connection pads, a semiconductor assembly which is provided with a plurality of electrode pads and is connected with the substrate in a flip chip manner, and a welding wire segment arranged on the electrode pads. The electrode pads and the electrical connection pads are electrically connected by the bonding wire sections, and the line width of the bonding wire sections is extremely small, so that the size of the electrical connection pads can be relatively reduced, and the requirements of fine spacing and miniaturization are met.

Description

Semiconductor package part and method for making thereof
Technical field
The present invention is about semiconductor package part, particularly about a kind of semiconductor package part and method for making thereof of reaching thin space and microminiaturization demand by wire bonds.
Background technology
In existing Flip Chip, as shown in Figure 1A, crystal covering type semiconductor package part 1 comprises that a base plate for packaging 10 and with a plurality of wafer-covered solder pads 100 has the chip 11 of a plurality of electronic padses 110, and pre-scolding tin material can be set with in conjunction with this wafer-covered solder pad 100 on those electronic padses 110, this pre-scolding tin material of reflow is to form solder bump 12, so that electrical I/O (I/O) and mechanical be connected of this chip 11 with 10 of this base plate for packaging to be provided again; Afterwards, re-use primer (underfill) 14 coupling this chip 11 and this base plate for packaging 10, with the Integrity And Reliability of the electric connection of guaranteeing 10 of this chip 11 and this base plate for packaging.
General step of making this solder bump 12, by first form patterning photoresistance (figure slightly) on this chip 11 to expose this electronic pads 110, sequentially electroplate again the copper post with pre-scolding tin material on this electronic pads 110, then remove this photoresistance, finally by reflow process to form solder bump 12.Because this copper post can not change shape in reflow process, so can effectively control height and the volume of this solder bump 12, to avoid producing the phenomenons such as the bad or bridge joint short circuit of coplanarity (coplanarity), thereby can reach the requirement of flip chip structure to the thin space (Fine Pitch) of projection.
Yet, while making this solder bump 12, need patterned technique and electroplating technology, cause step various, the process time is tediously long, thereby is unfavorable for improving production capacity, and electroplating cost is high, thereby is difficult to reduce the cost of product.
In addition, in existing semiconductor package part 1, as shown in Figure 1A ', because the wide r of path of this solder bump 12 is 80 μ m, so the wide R in the footpath of those wafer-covered solder pads 100 at least is required to be 120 μ m, make respectively between this solder bump 12, to keep certain distance, contact bridge joint phenomenon occurring when avoiding reflow and causes short circuit, but therefore can't dwindle again the respectively wide R in footpath and the spacing y of this wafer-covered solder pad 100, cause the laying area of this base plate for packaging 10 to reduce, and its wiring density can't improve, so that further microminiaturization packaging part, and be difficult to promote again electrical functionality.
On the other hand, along with electronic product is compact and the trend of system combination, make the space of semiconductor package part use more important, and for the performance that improves single semiconductor package part to meet the compact demand of electronic product, by by least two chip portfolios in single semiconductor package part, with reduction electronic product integrated circuit structural volume, and lifting electrical functionality, for example, the restriction of System Operation speed is minimized, and reduce the length of chip chamber connection line and reduce signal delay and access time.
In recent years, use stacking method to increase the quantity of chip to save the substrate usage space, as No. 20090068790 United States Patent (USP) or semiconductor package part 1 ' as shown in Figure 1B, each chip 11 ' utilizes rerouting line layer (Redistribution layer, RDL) technique in this electronic pads 110 ' upper form a plurality of stretch out be protruding with a plurality of electric conductors 13, respectively this chip 11 ' vertical stack has on the substrate 10 ' of a plurality of electric connection pads 100 ' in one again, then utilize pulse method to be coated with a plurality of conduction micelles 12 ' to be electrically connected this electric conductor 13 and this electric connection pad 100 '.Afterwards, then carry out packaging technology (figure slightly).
Yet, in the semiconductor package part 1 ' of existing tool stack chip 11 ', this conduction micelle 12 ' is the glue material, it is not good with the electrical reliability engaged between metal material (as this electric conductor 13 or electric connection pad 100 ').
In addition, because of this conduction micelle 12 ' width quite large, cause the spacing z of respectively this electric connection pad 100 ' on this substrate 10 ' need reach large (as shown in Figure 1B ', this spacing z is greater than 200um), to avoid respectively this conduction micelle 12 ' to contact and cause short circuit, so this substrate 10 ' need have larger loaded area to lay those electric connection pads 100 ', cause this substrate 10 ' still to need to maintain certain size and be difficult to dwindle again, so that further microminiaturization packaging part.
Therefore, how to overcome the variety of problems of above-mentioned prior art, become in fact the problem of desiring most ardently at present solution.
Summary of the invention
In view of all deficiencies of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof, but makes the size relative decrease of this electric connection pad, to reach the demand of thin space and microminiaturization.
Semiconductor package part of the present invention comprises: a substrate, and it has a plurality of electric connection pads; At least one semiconductor subassembly, it has relative first surface and second surface reaches the side joined with this first and second surface, and this semiconductor subassembly is placed on this substrate with its first surface, and has a plurality of electronic padses on this first surface; And the bonding wire section, it has relative first end and the second end, this bonding wire Duan Yiqi first end is formed on this electronic pads, and outside direction is extended towards this semiconductor subassembly side, with the second end of making this bonding wire section in conjunction with this electric connection pad.
The present invention also provides a kind of method for making of semiconductor package part, it comprises: at least one semiconductor subassembly is provided, this semiconductor subassembly has relative first surface and second surface reaches the side joined with this first and second surface, has a plurality of electronic padses on this first surface; Form the bonding wire section on this electronic pads, this bonding wire section has relative first end and the second end, and this bonding wire Duan Yiqi first end is formed on this electronic pads, and the second end of this bonding wire section direction outside towards this semiconductor subassembly side extended; And make this semiconductor subassembly be placed in one with its first surface to have on the substrate of a plurality of electric connection pads, and this electric connection pad is in conjunction with the second end of this bonding wire section.
In aforesaid semiconductor package part and method for making thereof, the second end of this bonding wire section has the metal bulb; Perhaps, can there is conductive projection on this electric connection pad.
In aforesaid semiconductor package part and method for making thereof, when this semiconductor subassembly is a plurality of, respectively this semiconductor subassembly is mutual storehouse, for example, and stepped storehouse, vertical alignment storehouse, interleaving stack or part vertical alignment storehouse and the stepped storehouse of part; And those semiconductor subassemblies are electrically connected mutually, for example with this bonding wire section, do to be electrically connected or be electrically connected with the conductive layer of the second end of this bonding wire section.Wherein, the second end depositing process or the wicking technique of this bonding wire section are electrically connected.
In aforesaid semiconductor package part and method for making thereof, also comprise form conductive layer on this electric connection pad to coat the part surface of this bonding wire section, and the mode that forms this conductive layer is for changing depositing process or wicking technique.
In aforesaid semiconductor package part and method for making thereof, also comprise form insulating material on this electric connection pad to coat the part surface of this bonding wire section, and this insulating material also is formed on this substrate.In addition, the mode that forms this insulating material is gluing process, fill primer technique or mold pressing packaging technology.
As from the foregoing, in semiconductor package part of the present invention and method for making thereof, in packaging technology, the routing technology is the electric connection mode the simplest and easy, quick, that step is few, cost is low, so by routing fabrication techniques bonding wire section, to overcome the disappearances such as the step that has chip-covered boss technique now is many, cost is high, the process time is long, so be conducive to improve production capacity.
In addition, the width of the present invention's and existing conduction micelle wide much smaller than the footpath of existing solder bump by the live width of bonding wire section, so the spacing of those electric connection pads can significantly reduce to meet the demand of thin space, but make not only its size relative decrease of this substrate, and still can lay enough electric connection pads, thereby can reach the demand of microminiaturization.
Moreover, than existing conducting resin material, between bonding wire section of the present invention and electric connection pad or respectively the electrical reliability engaged between this bonding wire section is better.
The accompanying drawing explanation
Figure 1A is the generalized section of existing crystal covering type semiconductor package part; Wherein, Figure 1A ' looks schematic diagram for Figure 1A omits on the part of chip;
Figure 1B is the generalized section of the semiconductor package part of existing tool stack chip; Wherein, Figure 1B ' looks schematic diagram for Figure 1B omits on the part of chip;
The generalized section of the method for making of the first embodiment that Fig. 2 A to Fig. 2 E is semiconductor package part of the present invention; Wherein, Fig. 2 C ' looks schematic diagram, Fig. 2 C on the part for Fig. 2 C omission semiconductor subassembly " be another embodiment of Fig. 2 C ', another embodiment that Fig. 2 E ' is Fig. 2 E;
The generalized section of the second embodiment that Fig. 3 is semiconductor package part of the present invention; And
The 3rd schematic side view to the 6th embodiment that Fig. 4 to Fig. 7 is semiconductor package part of the present invention; Wherein, Fig. 4 ' for Fig. 4 on look schematic diagram.
The primary clustering symbol description
Figure BDA00001722240500041
Figure BDA00001722240500051
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, appended graphic the illustrated structure of this specification, ratio, size etc., equal contents in order to coordinate specification to disclose only, understanding and reading for those skilled in the art, not in order to limit the enforceable qualifications of the present invention, so technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this specification, quote as " on ", D score, 'fornt', 'back', " left side ", " right side ", " side ", " first ", " second " reach terms such as " one ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when also being considered as the enforceable category of the present invention.For example, in the present invention, " first " of first surface refers to the surface that forms electronic pads, and the first surface of non-limiting all semiconductor subassemblies is all identical purposes.
Refer to Fig. 2 A to Fig. 2 E, the generalized section of the method for making of its first embodiment that is semiconductor package part 2 of the present invention.
As shown in Figure 2 A, provide semiconductor assembly 21, it has relative first surface 21a and second surface 21b and adjacent this first and second surperficial 21a, and the side 21c of 21b, have a plurality of electronic padses 210 on this first surface 21a.In the present embodiment, this semiconductor subassembly 21 can be chip, wafer or passive component.
As shown in Fig. 2 B, form a bonding wire section 22 on this electronic pads 210 respectively, and an end of this bonding wire section 22 direction outside towards the side 21c of this semiconductor subassembly 21 extended.
In the present embodiment, the material of this bonding wire section 22 comprises gold, silver or copper material, and the mode of making this bonding wire section 22 is for beating short-term technique, and it needs to apply general routing technique, for example: use general routing device after pulling out required wire length, then bonding wire is blocked and gets final product; Afterwards, the alternative diaphragm (figure slightly) that forms on the surface of this semiconductor subassembly 21.
In addition, described bonding wire section 22 has relative first end 22a and the second end 22b (end), and first end 22a is incorporated on this electronic pads 210, and the second end 22b is truncated end.
As shown in Figure 2 C, this semiconductor subassembly 21 is placed in to one with its first surface 21a and has on the substrate 20 of a plurality of electric connection pads 200, and this electric connection pad 200 is in conjunction with the second end 22b of this bonding wire section 22.In addition, can use sticky epitaxial in this semiconductor subassembly 21 with substrate 20 to strengthen its mechanical connection.
In the present embodiment, the material of this electric connection pad 200 comprises copper or aluminium, and can on this electric connection pad 200, form the surface-treated layer (figure slightly) as nickel/golden material.
In addition, although this semiconductor subassembly 21 is incorporated on this substrate 20 to cover crystal type, but replace by this bonding wire section 22 solder bump that existing chip bonding is used, and the wide footpath much smaller than existing solder bump, the footpath of this bonding wire section 22 is wide, so the bonded area of those electric connection pads 200 can be less, for example be designed to the wire pad of finger-shaped (finger), and need not be designed to the wafer-covered solder pad that bonded area is larger, be beneficial to promote wiring density.
Particularly, as shown in Fig. 2 C ', the about 100um(of length L of the bonding wire section 22 in beating short-term technique is containing upper and lower extension), the length D(of this electric connection pad 200 is as 90um) can be less than the footpath wide (120um) that has wafer-covered solder pad now, and being greater than the live width of this bonding wire section 22, the width of this electric connection pad 200 gets final product, so the required bonded area of those electric connection pads 200 is much smaller than the existing required bonded area of wafer-covered solder pad.Therefore, but this substrate 20 its size relative decrease not only, and still can lay enough electric connection pads 200, thus can effectively dwindle the size of this substrate 20, to reach the demand of microminiaturization.
Moreover, about 20 to 30 μ m of the spacing x of this electric connection pad 200 respectively, and the bearing of trend according to this bonding wire section 22 changes (being the front, rear, left and right directions), respectively the large I of the spacing x of this electric connection pad 200 adjusts, to meet the demand of thin space, and be beneficial to the purpose that promotes wiring density and reach microminiaturization.
In addition, can be on demand, those electric connection pads 200 ' are staggered, as Fig. 2 C " as shown in, the spacing of two adjacent electric connection pads 200 is 0 μ m approximately, and about 20 to the 30 μ m of the spacing x ' of two electric connection pads 200 separately; to meet the demand of elasticity wiring, and more can promote wiring density.For example, Fig. 2 C " the respectively spacing t ' of this bonding wire section 22 be less than the respectively spacing t of this bonding wire section 22 of Fig. 2 C ', even and the spacing t of this bonding wire section 22 respectively, t ' is so little, respectively bonding wire bridge joint phenomenon still can not occur in this bonding wire section 22.
As shown in Figure 2 D, form a conductive layer 23 on this electric connection pad 200, to coat the second end 22b of this bonding wire section 22, for the power that is connected of strengthening between this bonding wire section 22 and this electric connection pad 200.Yet, in other embodiment, can not form this conductive layer 23.
In the present embodiment, form the mode of this conductive layer 23 for changing depositing process, electroplating technology, wicking technique or gluing process.
Describedization depositing process utilizes the chemical reaction of burning reduction, and selectivity deposition layer of metal material is in metal surface.Wherein, this change depositing process is that the useization plating solution carries out operation, and this changes the of a great variety of plating solution, and for example, changing copper electrolyte is sulfur acid copper (Copper Surfate), formaldehyde (Formaldehyde) and methyl alcohol (Methanol); Change nickel plating bath for containing ammonium citrate (Ammoniun Citrate), NH4Cl, Nickel dichloride hexahydrate (Nickel Chloride Hexahydrate), sodium hypophosphite (Sodium Hypophosphite), edetate (Ethylene Diamine Tetracetate) and ammonium hydroxide (Ammoniun Hydroxide); Change the tin plating solution for containing tin methane sulfonate (Tin (II) Methanesulphonate), methanesulfonic acid (Methanesulphonic Acid) and thiocarbamide (Thiourea); Change silver plating solution for containing propyl alcohol (Propyl Alcohol), hydrochloric acid (Hydrochloric Acid) and stannous chloride (Stannous Chloride), but that the kind of this change plating solution is not limited to is above-mentioned.
Described wicking technique is to utilize the loose tin of gold, on the second end 22b in this bonding wire section 22 and this electric connection pad 200, to be stained with one deck tin material.
Described gluing process is the most easy mode, with the conducting resinl (not shown) as elargol, copper cream, coats the second end 22b of this bonding wire section 22, but must consider the thermal coefficient of expansion of this conducting resinl and electrical correlated condition.
As shown in Figure 2 E, carrying out the mold pressing packaging technology, is packing colloid to form insulating material 24() on this substrate 20, to coat this semiconductor subassembly 21 and bonding wire section 22(or this conductive layer 23).
In another is implemented, as shown in Fig. 2 E ', utilize and fill primer (underfill) technique formation insulating material 24 ' on this electric connection pad 200, to coat the second end 22b(or this conductive layer 23 of this bonding wire section 22); In other embodiment, also the utilisation point adhesive process forms insulating material.
In addition, the mode that forms insulating material 24,24 ' is various, is not limited to above-mentioned.
Method for making of the present invention is utilized this bonding wire section 22 of equipment making of routing technique, because of the routing technology quite ripe, so be applied to beat the short-term mode, can make technique simple and easy, quick, and because processing step is few, cost is low, and be conducive to improve production capacity (Unit Per Hour, UPH), and can reduce costs.
Refer to Fig. 3, the generalized section of its second embodiment that is semiconductor package part 3 of the present invention.The second end 32b that the difference of the present embodiment and the first embodiment only is this bonding wire section 32 also selectivity is formed with metal bulb 320, and on this electric connection pad 300 also selectivity there is conductive projection 301.
During making, by on those electric connection pads 300, planting conductive projection 301, and the second end 32b that is located at the bonding wire section 32 on this semiconductor subassembly 21 is burnt into to a metal bulb 320, then the metal bulb of each bonding wire section 32 320 is engaged to the conductive projection 301 of this electric connection pad 300.
In the present embodiment, this semiconductor package part 3 is formed with this metal bulb 320 and conductive projection 301, and, in other embodiment, can make this semiconductor package part only be formed with the wherein one of metal bulb 320 or conductive projection 301.
In addition, can the utilization depositing process, wicking technique or gluing process do combination by this metal bulb 320 with this conductive projection 301, and the correlation technique of relevantization depositing process, wicking technique or gluing process can be with reference to foregoing.
In addition, relevant this conductive projection 301 of a great variety, plant ball, copper post (Cu pillar), soldering tin material (Solder bump) or stud bumps (Stud bump) etc. such as metal, and there is no particular restriction.
Refer to Fig. 4, Fig. 5, Fig. 6 and Fig. 7, it discloses semiconductor package part 4,5,6 of the present invention, 7 the 3rd to six embodiment, the Main Differences of those embodiment and above-described embodiment is this semiconductor package part 4,5,6,7 include a plurality of semiconductor subassemblies 41,41 ', 51,61,61 ', 71, and this semiconductor subassembly 41,41 ' respectively, 51,61,61 ', 71 mutual storehouses with its bonding wire section 42,42 ', 52,62,72 are electrically connected.
As shown in Figure 4, those semiconductor subassemblies 41,41 ' is stepped storehouse, and does electrically to engage with the metal bulb 420 of those bonding wire sections 42, and the bonding wire section 42(of the semiconductor subassembly 41 ' of bottommost or metal bulb 420) be electrically connected this electric connection pad 200(or conductive projection 301).And the semiconductor subassembly 41 of top is stacked over to cover crystal type on the semiconductor subassembly 41 of below, and a plurality of bonding wire sections 42 are electrically connected to each other.
As shown in Figure 5, those semiconductor subassemblies 51 are the vertical alignment storehouse.
As shown in Figure 6, this semiconductor subassembly 61 ' of part is the vertical alignment storehouse, and the stepped storehouse of this semiconductor subassembly 61 of part.
As shown in Figure 7, those semiconductor subassemblies 71 are staggered storehouse, and this bonding wire section 72(or metal bulb 720) be electrically connected the circuit (figure slightly) of this semiconductor subassembly 71.
In stack architecture of the present invention, it utilizes this bonding wire section 42,52, metal bulb 420,520 is directly burnt in 62,72 end, 620,720, more electrically engage adjacent metal bulb 420 to change plating or wicking, 520,620,720, so than conduction micelle of the prior art, metal of the present invention bulb 420,520,620,720 can improve the reliability electrically engaged.
In addition, this metal bulb 420,520,620, the wide width much smaller than conduction micelle of the prior art in 720 footpath, thereby need not worry the metal bulb 420,520,620 of front, rear, left and right side, 720 contact and cause the problem of short circuit, so the spacing x of those electric connection pads 200 can significantly reduce (as shown in Fig. 2 C '), but make not only its size relative decrease of this substrate 20, and still can lay enough electric connection pads 200.Therefore, the present invention can effectively dwindle the size of this substrate 20, thereby breaks through the bottleneck of microminiaturization demand.
Moreover, in the 3rd to six embodiment, the 3rd embodiment of take is example, as shown in Fig. 4 ', the semiconductor subassembly 41 ' of bottommost also can form bonding wire section 42 ' in other side, to be electrically connected those electric connection pads 400.
In addition, this bonding wire section 42,42 ', 52,62 respectively, 72 alternative electric connections, but not all this bonding wire sections 42,42 ', 52,62,72 all need to be electrically connected, and this bonding wire section 42,42 ', 52 respectively, 62,72 also can otherwise be electrically connected, and as changed plating, engage or electroplate joint, also are about to upper and lower adjacent bonding wire section 42,42 ', 52,62,72 end directly electrically engages, and without being electrically connected with this metal bulb 420,520,620,720.
In the of the present invention first to the 6th embodiment, the technique of this substrate 20 can adopt SMT(Surface-mount technology) technique or NSMD(none solder mask define) technique.
In addition, this semiconductor subassembly has relative acting surface and non-acting surface, and its electronic pads can be according to being laid on this acting surface and non-acting surface.For example: if be bonded on second half conductor assembly or substrate with the acting surface of this semiconductor subassembly, on this acting surface, lay electronic pads; If the non-acting surface with this semiconductor subassembly is bonded on second half conductor assembly or substrate, on this non-acting surface, lay electronic pads.
Moreover, about storehouse mode and the electric connection mode of those semiconductor subassemblies are various, be not limited to above-mentionedly, for example, the end metal of this bonding wire section is electrically connected to change depositing process or wicking technique.
The invention provides a kind of semiconductor package part 2,2 ', 3, it comprises: a substrate 20, be located at the semiconductor assembly 21 on this substrate 20 and be formed at the bonding wire section 22,32 on this semiconductor subassembly 21.
Described substrate 20 has a plurality of electric connection pads 200,300, and can on demand, make on this electric connection pad 300 and have conductive projection 301.
Described semiconductor subassembly 21 has relative first surface 21a and second surface 21b and adjacent this first and second surperficial 21a, the side 21c of 21b, this semiconductor subassembly 21 is placed on this substrate 20 with its first surface 21a, and has a plurality of electronic padses 210 on this first surface 21a.
Described bonding wire section 22,32 are located on this electronic pads 210 and extend to the side 21c direction of this semiconductor subassembly 21, and one end (being first end 22a) is in conjunction with this electric connection pad 200,300, and can on demand, make an end (i.e. the second end 32b) of this bonding wire section 32 there is metal bulb 320.
Described semiconductor package part 2 also comprises that one is formed at the conductive layer 23 on this electric connection pad 200, and it is in order to coat the part surface of this bonding wire section 22.Comprise again the insulating material 24,24 ' be formed on this electric connection pad 200, it coats this bonding wire section 22.Described insulating material 24,24 ' also is formed on this substrate 20.
In semiconductor package part 4,5, in other embodiment of 6,7, this semiconductor subassembly 41,41 ', 51,61,61 ', 71 while being a plurality of, respectively this semiconductor subassembly 41,41 ', 51,61,61 ', 71 is mutual storehouse, for example, and those semiconductor subassembly 41,41 ' stepped storehouses; Perhaps, those semiconductor subassemblies 51 are the vertical alignment storehouse; Perhaps, this semiconductor subassembly 61 ' of part is the vertical alignment storehouse, and the stepped storehouse of this semiconductor subassembly 61 of part; Perhaps, those semiconductor subassemblies 71 are staggered storehouse.
Described respectively this semiconductor subassembly 41,41 ', 51,61,61 ', 71 also are electrically connected mutually, for example, and those semiconductor subassemblies 41,41 ', 51,61,61 ', 71 with its bonding wire section 42,52,62,72 do to be electrically connected or with this bonding wire section 42,52,62,72 end conductive layer (change depositing process or wicking technique and form it, figure slightly) is electrically connected.
In sum, semiconductor package part of the present invention and method for making thereof, mainly make the bonding wire section by routing technique, simple and easy and quick with the technique that makes crystal covering type packaging part or stacking-type packaging part, and reduce processing step and reduce costs, and can improve production capacity.
In addition, minimum by the live width of bonding wire section, to reduce the spacing of those electric connection pads, but make the size relative decrease of this substrate, thereby this semiconductor package part can reach the demand of microminiaturization.
Moreover bonding wire section of the present invention is not the glue material, so it is better with the electrical reliability engaged between metal material.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.So the scope of the present invention, should be as listed as claims.

Claims (22)

1. a semiconductor package part, it comprises:
One substrate, it has a plurality of electric connection pads;
At least one semiconductor subassembly, it has relative first surface and second surface reaches the side joined with this first and second surface, and this semiconductor subassembly is placed on this substrate with its first surface, and has a plurality of electronic padses on this first surface; And
The bonding wire section, it has relative first end and the second end, this bonding wire Duan Yiqi first end is formed on this electronic pads, and outside direction is extended towards this semiconductor subassembly side, with the second end of making this bonding wire section in conjunction with this electric connection pad.
2. semiconductor package part according to claim 1, is characterized in that, the second end of this bonding wire section has the metal bulb.
3. semiconductor package part according to claim 1, is characterized in that, on this electric connection pad, has conductive projection.
4. semiconductor package part according to claim 1, is characterized in that, when this semiconductor subassembly is a plurality of, respectively this semiconductor subassembly is mutual storehouse.
5. semiconductor package part according to claim 4, is characterized in that, those semiconductor subassemblies are electrically connected mutually.
6. semiconductor package part according to claim 5, is characterized in that, those semiconductor subassemblies are electrically connected with this bonding wire section.
7. semiconductor package part according to claim 5, is characterized in that, those semiconductor subassembly systems are electrically connected with the conductive layer of the second end of this bonding wire section.
8. semiconductor package part according to claim 4, is characterized in that, the stepped storehouse of those semiconductor subassemblies, vertical alignment storehouse or interleaving stack.
9. semiconductor package part according to claim 4, is characterized in that, this semiconductor subassembly of part is the vertical alignment storehouse, and the stepped storehouse of this semiconductor subassembly of part.
10. semiconductor package part according to claim 1, is characterized in that, also comprises conductive layer, and it is formed on this electric connection pad, to coat the part surface of this bonding wire section.
11. semiconductor package part according to claim 1, is characterized in that, also comprises insulating material, it is formed on this electric connection pad, to coat the part surface of this bonding wire section.
12. the method for making of a semiconductor package part, it comprises:
At least one semiconductor subassembly is provided, and this semiconductor subassembly has relative first surface and second surface reaches the side joined with this first and second surface, has a plurality of electronic padses on this first surface;
Form the bonding wire section on this electronic pads, this bonding wire section has relative first end and the second end, and this bonding wire Duan Yiqi first end is formed on this electronic pads, and the second end of this bonding wire section direction outside towards this semiconductor subassembly side extended; And
Make this semiconductor subassembly be placed in one with its first surface and have on the substrate of a plurality of electric connection pads, and this electric connection pad is in conjunction with the second end of this bonding wire section.
13. the method for making of semiconductor package part according to claim 12, is characterized in that, the second end of this bonding wire section has the metal bulb.
14. the method for making of semiconductor package part according to claim 12, is characterized in that, when this semiconductor subassembly is a plurality of, respectively this semiconductor subassembly is mutual storehouse.
15. the method for making of semiconductor package part according to claim 14, is characterized in that, those semiconductor subassemblies are electrically connected with this bonding wire section.
16. the method for making of semiconductor package part according to claim 14, is characterized in that, the second end depositing process or wicking technique with this bonding wire section between those semiconductor subassemblies are electrically connected.
17. the method for making of semiconductor package part according to claim 14, is characterized in that, the stepped storehouse of those semiconductor subassemblies, vertical alignment storehouse or interleaving stack.
18. the method for making of semiconductor package part according to claim 14, is characterized in that, this semiconductor subassembly of part is the vertical alignment storehouse, and the stepped storehouse of this semiconductor subassembly of part.
19. the method for making of semiconductor package part according to claim 12, is characterized in that, also comprises and form conductive layer on this electric connection pad, to coat the part surface of this bonding wire section.
20. the method for making of semiconductor package part according to claim 19, is characterized in that, forms the mode of this conductive layer for changing depositing process, electroplating technology or wicking technique.
21. the method for making of semiconductor package part according to claim 12, is characterized in that, also comprises and form insulating material on this electric connection pad, to coat the part surface of this bonding wire section.
22. the method for making of semiconductor package part according to claim 21, is characterized in that, the mode that forms this insulating material is gluing process, filling primer technique or mold pressing packaging technology.
CN2012101815937A 2012-05-16 2012-06-04 Semiconductor package and fabrication method thereof Pending CN103426870A (en)

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Application publication date: 20131204