CN110890284A - Chip stacking and packaging structure and process method thereof - Google Patents
Chip stacking and packaging structure and process method thereof Download PDFInfo
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- CN110890284A CN110890284A CN201911226398.XA CN201911226398A CN110890284A CN 110890284 A CN110890284 A CN 110890284A CN 201911226398 A CN201911226398 A CN 201911226398A CN 110890284 A CN110890284 A CN 110890284A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a chip stacking and packaging structure and a process method thereof, belonging to the field of integrated circuit packaging. The invention provides a chip stacking and packaging structure and a process method thereof, aiming at the problems of complex manufacture procedure, high cost and large thickness of a chip stacking and packaging substrate in the prior art. The problem that the existing chip stacking packaging substrate is complex in manufacturing process and high in cost is solved, and meanwhile, the control of the thickness of a packaging body is also met. The problems of complex manufacturing process and high cost of the existing chip stack packaging substrate are avoided, the whole process is simplified, and the cost is reduced.
Description
Technical Field
The invention relates to the field of integrated circuit packaging, in particular to a chip stacking packaging structure and a process method thereof.
Background
With the trend of light weight, thinness, shortness, smallness and diversified functions of electronic products, in order to meet the trend, a chip-stacked package structure is generally used to replace a pop (package on package) package or a pip (package in package) package (package in package), such as the taiwan patent publication No. TWI390704B, in which a groove is formed on the front surface of a substrate, a first chip (flip chip) is disposed in the groove and electrically connected to the substrate, a second chip is disposed on the first chip and electrically connected to the substrate to package a product, and balls are mounted on the back surface to form an electrical pin output and then a circuit board patch is mounted. However, in the prior art, the substrate needs to form the groove to accommodate the first chip, the manufacturing process of the substrate is complex, and the groove is designed, and the groove of the substrate needs to design a circuit layer for the first chip accommodated in the groove, which increases the complexity of the substrate manufacturing process and the manufacturing cost. Therefore, how to reduce the cost and improve the market competitiveness of the product is a problem which is urgently solved at present.
Disclosure of Invention
1. Technical problem to be solved
The invention provides a chip stacking and packaging structure and a process method thereof, aiming at the problems of complex manufacture procedure, high cost and large thickness of a chip stacking and packaging substrate in the prior art.
2. Technical scheme
The purpose of the invention is realized by the following technical scheme.
A process method of a chip stacking and packaging structure comprises the following steps:
the method comprises the following steps: selecting a metal base material, selectively half-etching the front surface of the metal base material, half-etching the positions where the grooves need to be formed and the positions between the pins, and forming the grooves and a plurality of separated front surface pins which are distributed around the grooves through the half-etching; the number of the pins on the front surface can be set according to requirements;
step two: a first chip is arranged at the position of a groove in the front surface of the metal base material, a plurality of conductive bumps are arranged on the functional surface of the first chip, and the first chip is arranged in the direction that the conductive bumps face the groove; the functional surface is the surface of the chip provided with functional electrical contacts, also called the front surface of the chip, whereas the surface without functional electrical contacts is the non-functional surface, also called the back surface of the chip;
step three: after the first chip is installed, arranging a second chip on the front side of the front side pins, wherein the second chip is electrically connected with the corresponding front side pins through the electrical connection parts;
step four: after the second chip is installed, the front surface of the metal base material is encapsulated, and the first chip, the second chip, the electrical connection part and the front surface pin are coated by a plastic encapsulating material;
step five: after the front surface is encapsulated, removing all the back surface of the metal base material to expose the conductive bump of the first chip and the insulating filling material between the first chip and the bottom of the groove, and removing the insulating filling material between the lead pins and the periphery of the lead pins formed by the front surface pins after the back surface is removed;
step six: and after the back surface of the metal base material is removed, electroplating a metal layer on the exposed positions of the conductive bumps and the lead pins, cutting and molding after electroplating, and finishing the packaging manufacture of the chip stacking and packaging structure.
Furthermore, in the second step, the first chip is arranged in the groove, non-conductive chip mounting glue can be arranged at the position of the groove corresponding to the first chip, and the first chip is arranged in the groove through the non-conductive chip mounting glue; the first chip can also be plated with a metal layer in advance at the position corresponding to the conductive bump in the groove through a normal flip-chip process, and the conductive bump of the first chip is welded in the groove through solder paste.
Furthermore, the insulation filling material filled between the first chip and the bottom of the groove is underfill glue or non-conductive mounting glue or molding compound.
Furthermore, in the third step, the electrical connection portion is a bonding wire or a solder ball.
The utility model provides a chip stacks packaging structure, includes first chip, sets up a plurality of pin terminals around first chip, sets up in the positive second chip of pin terminal and molding compound, the functional surface of first chip is provided with a plurality of electrically conductive lugs, the second chip passes through electric connection portion electric connection to pin terminal, molding compound cladding first chip, second chip, electric connection portion and pin terminal, electrically conductive lug and pin terminal bottom surface expose in the external surface of packaging at least.
Furthermore, the electrical connection portion is a bonding wire or a solder ball.
Furthermore, the conductive bump is a solder ball or a conductive pillar.
Further, the back surface of the first chip is lower than the front surfaces of the terminal pins.
3. Advantageous effects
Compared with the prior art, the invention has the advantages that:
this scheme chip piles up's encapsulation product adopts metal substrate, sets up the recess of the first chip of holding on metal substrate's basis, carries out the setting of second chip in the top of chip and recess, encapsulates the technology back, exposes flip chip's conductive bump and pin through grinding or etching. The scheme solves the problems that the existing chip stacking packaging substrate is complex in manufacturing process and high in cost, and simultaneously, the control on the thickness of a packaging body is also met. The problems of complex manufacturing process and high cost of the existing chip stack packaging substrate are avoided, the whole process is simplified, and the cost is reduced.
Drawings
FIG. 1 is a schematic structural diagram of a substrate after half-etching to form grooves and front pins;
FIG. 2 is a schematic structural diagram after a first chip is mounted;
FIG. 3 is a schematic diagram of a second chip mounted thereon;
FIG. 4 is a schematic view of the front side seal after installation;
FIG. 5 is a schematic view of the structure after etching of the back side of the mounting;
FIG. 6 is a schematic top view of a cross section of a chip;
fig. 7 is a schematic diagram of a chip backside structure.
The reference numbers in the figures illustrate:
1. a metal substrate; 2. a front pin; 3. a first chip; 4. a second chip; 5. a conductive bump; 6. a groove; 7. plastic packaging material; 8. a terminal pin; 9. an electrical connection portion.
Detailed Description
The invention is described in detail below with reference to the drawings and specific examples.
The chip stacking and packaging structure is manufactured by the following process method, and the steps are as follows:
the method comprises the following steps: as shown in fig. 1, a metal substrate 1 is selected, selective half-etching is performed on the metal substrate 1, except for the positions of pins, the selective half-etching is performed to remove the pins by etching, finally, the half-etching is performed to form a groove 6 and a plurality of separated front pins 2 arranged around the groove, and the number of the specific front pins 2 can be set as required. After the etching is finished, a metal layer can be electroplated on the front side of the front side pin 2, and the metal layer electroplated on the front side pin can be a tin layer, a silver alloy layer, nickel palladium gold and the like. The metal substrate 1 may be a copper substrate, or may be another metal material suitable for packaging. The groove 6 is used for subsequently accommodating a required chip, and the etching mode of the groove 6 can select different etching processes according to requirements, such as laser etching or chemical etching.
Step two: as shown in fig. 2, the first chip 3 is mounted in the recess 6 on the front surface of the metal substrate 1, the first chip 3 is a flip chip, the functional surface of the first chip 3 is provided with a plurality of conductive bumps 5, the functional surface is also referred to as the front surface of the chip, which refers to the surface of the chip provided with the functional electrical contacts, whereas the surface without the functional electrical contacts is the non-functional surface, which is also referred to as the back surface of the chip. The first chip 3 is soldered with the conductive bump 5 in the groove 6 by solder paste, and after the subsequent packaging is completed, the first chip 3 forms a corresponding electrical connection part on the back of the package by the conductive bump 5. And underfill adhesive is filled between the bottom of the first chip 3 and the groove 6, or the underfill adhesive is directly filled with packaging plastic package materials subsequently. The conductive bumps 5 are typically solder balls or conductive pillars. In order to improve the welding strength between the conductive bump 5 and the groove 6, a metal layer, which may be a tin layer, may be electroplated in advance at a position corresponding to the conductive bump 5 at the bottom of the groove 6. After the first chip 3 is mounted in the recess 6, it is generally ensured that the upper surface of the first chip 3 is lower than the front surface of the front leads 2, so as not to affect the mounting of the second chip 4. The functional surface of the first chip 3 can also be attached in the groove 6 through non-conductive mounting glue, and the non-conductive mounting glue is filled between the bottom of the first chip 3 and the groove 6. The bottom filling glue, the non-conductive mounting glue and the plastic packaging material are all insulating filling substances.
Step three: as shown in fig. 3, after the first chip 3 is mounted, the second chip 4 is mounted. The second chip 4 is disposed on the front surface of the front surface pins 2, the second chip 4 is supported by the front surface pins 2, and the second chip 4 is electrically connected to the corresponding front surface pins 2 through the electrical connection portions 9. The electrical connection 9 may be a bonding wire or a solder ball. As shown in fig. 3, the second chip 4 is mounted on the front surface leads 2 by a normal mounting method, and then the second chip 4 is electrically connected to the front surface leads 2 by the electrical connection portions 9 by wire bonding, where the electrical connection portions 9 are bonding wires. Of course, the second chip 4 can also be mounted on the front-side leads 2 directly through the electrical connection portions 9 by flip-chip mounting, where the electrical connection portions 9 are solder balls.
Step four: as shown in fig. 4, after the second chip 4 is mounted, the front surface of the metal substrate 1 is encapsulated, and the first chip 3, the second chip 4, the electrical connection portion 9 and the front surface pins 2 are encapsulated by the molding compound 7.
Step five: as shown in fig. 5, after the front side encapsulation is completed, all the back sides of the metal base material 1, including all the metal base materials at the bottom of the groove 6, the metal base materials at the back sides corresponding to the front side pins 2, the metal base materials at the back sides between the front side pins 2 and the metal base materials at the back sides corresponding to the periphery, are removed, the conductive bumps 5 of the first chip 3 are exposed, the front side pins 2 are removed through the back sides, and then the lead pins 8, the insulating filling material at the bottom of the first chip 3 and the groove 6, and the insulating filling material between the lead pins 8 and the. The back surface removing process of the metal substrate 1 can adopt an etching solution half-etching process, a grinding process, a laser and other modes.
Step six: after the back surface of the metal substrate 1 is completely removed, the exposed portions of the conductive bumps 5 and the terminal pins 8 are plated with a metal layer, which is typically a tin layer, and then the metal layer is cut and formed to complete the package manufacturing of the chip stack package structure. The formed package structure is as shown in fig. 6 and 7, the back of the package body simultaneously includes the conductive bumps 5 and the terminal pins 8 at the connection portions of the first chip 3 and the second chip 4 for electrical output, and when the package chip is used, the corresponding connection portions are directly designed on the corresponding circuit board to correspondingly connect the chips.
By the process method, the designed stack package ensures the lightness and thinness of the whole package, the thickness of the stack package is reduced, and the process is simple and the cost is low by adopting the metal plate. The chip stacking and packaging structure manufactured by the process method comprises a first chip 3, a plurality of lead pins 8 arranged around the first chip 3, a second chip 4 arranged on the front side of the lead pins 8 and a plastic packaging material 7, wherein a plurality of conductive bumps 5 are arranged on the functional surface of the first chip 3, the conductive bumps 5 can be solder balls or conductive columns, one surface of the first chip 3, on which the conductive bumps 5 are arranged, faces the back surface, the second chip 4 is electrically connected to the lead pins 8 through electrical connection parts 9, the plastic packaging material 7 coats the first chip 3, the second chip 4, the electrical connection parts 9 and the lead pins 8, and at least the bottom surfaces of the conductive bumps 5 and the lead pins 8 are exposed out of the outer surface of the packaging body. The bottom of the first chip 3 can be underfill, non-conductive chip mounting adhesive or molding compound 7. The back surface of the first chip 3 is lower than the front surface of the terminal pin 8, so that the second chip 4 can be smoothly mounted on the terminal pin 8. If the first chip 3 is higher on the back than the terminal pins 8, the second chip 4 is mounted on the first chip 3. If the second chip 4 is flip-chip mounted, the second chip 4 cannot be flip-chip mounted on the terminal pins 8, and the second chip 4 cannot be electrically connected to the terminal pins 8; if the second chip 4 is installed in a normal installation mode, the second chip 4 is not attached to the terminal pins 8, and the second chip 4 is bent under pressure during routing, so that the chip is easily broken and damaged.
The packaging structure that the chip of this scheme piled up can guarantee that first chip 3 sinks to set up in the encapsulation, and holistic encapsulation thickness reduces, and exposes in the external surface of encapsulation through the electrically conductive lug 5 of first chip 3 and the at least bottom surface of pin, does not influence the signal of telecommunication output of first chip 3 and second chip 4, simple structure, easy popularization.
The invention and its embodiments have been described above schematically, without limitation, and the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The representation in the drawings is only one of the embodiments of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not limit the claims concerned. Therefore, if a person skilled in the art receives the teachings of the present invention, without inventive design, a similar structure and an embodiment to the above technical solution should be covered by the protection scope of the present patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Several of the elements recited in the product claims may also be implemented by one element in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (9)
1. A process method for a chip stack package structure is characterized by comprising the following steps:
the method comprises the following steps: selecting a metal base material (1), carrying out selective half-etching on the front surface of the metal base material (1), and forming a groove (6) and a plurality of separated front surface pins (2) which are distributed around the groove (6) through the half-etching;
step two: a first chip (3) is arranged at the position of a groove (6) in the front surface of a metal base material (1), a plurality of conductive bumps (5) are arranged on the functional surface of the first chip (3), and the first chip (3) is arranged in the direction that the conductive bumps (5) face the groove (6);
step three: after the first chip (3) is installed, arranging a second chip (4) on the front surface of the front surface pin (2), wherein the second chip (4) is electrically connected with the corresponding front surface pin (2) through an electric connection part (9);
step four: after the second chip (4) is installed, the front surface of the metal base material (1) is encapsulated, and the first chip (3), the second chip (4), the electric connection part (9) and the front surface pin (2) are coated by a plastic package material (7);
step five: after the front surface is encapsulated, removing the whole back surface of the metal base material (1) to expose the conductive bump (5) of the first chip (3) and the insulating filling material between the first chip (3) and the bottom of the groove (6), and removing the insulating filling material between the lead pins (8) and on the periphery of the lead pins (2) on the front surface after the back surface is removed;
step six: and after the back surface of the metal base material (1) is removed, electroplating a metal layer on the exposed parts of the conductive bumps (5) and the lead pins (8), cutting and molding after electroplating, and finishing the packaging manufacture of the chip stacking and packaging structure.
2. The process method of the chip stack package structure according to claim 1, wherein in the second step, a non-conductive die attach adhesive is disposed at a position of the recess (6) corresponding to the first chip (3), and the first chip (3) is mounted in the recess (6) by the non-conductive die attach adhesive.
3. The process method of the chip stack package structure according to claim 1, wherein in the second step, the first chip (3) is pre-plated with a metal layer at a position corresponding to the conductive bump (5) in the groove (6) by a normal flip-chip process, and the conductive bump (5) of the first chip (3) is soldered in the groove (6) by a solder paste.
4. A process method for chip stacking and packaging structure according to claim 1, 2 or 3, wherein the insulating filling material filled between the first chip (3) and the bottom of the groove (6) is underfill adhesive or non-conductive die attach adhesive or molding compound (7).
5. The process of chip stack package structure according to claim 1, wherein in the third step, the electrical connection portion (9) is a bonding wire or a solder ball.
6. A chip stack package structure, comprising: the packaging structure comprises a first chip (3), a plurality of terminal pins (8) arranged around the first chip (3), a second chip (4) arranged on the front side of the terminal pins (8) and a plastic package material (7), wherein a functional surface of the first chip (3) is provided with a plurality of conductive bumps (5), one surface of the first chip (3) provided with the conductive bumps (5) is arranged towards the back side, the second chip (4) is electrically connected to the terminal pins (8) through an electrical connection part (9), the plastic package material (7) coats the first chip (3), the second chip (4), the electrical connection part (9) and the terminal pins (8), and at least the bottom surfaces of the conductive bumps (5) and the terminal pins (8) are exposed out of the outer surface of the packaging body.
7. The CSP structure of claim 6, wherein the electrical connection (9) is a bonding wire or a solder ball.
8. The chip stack package structure according to claim 6 or 7, wherein the conductive bump (5) is a solder ball or a conductive pillar.
9. The chip stack package structure according to claim 6, wherein the back surface of the first chip (3) is lower than the front surface of the terminal pin (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911226398.XA CN110890284A (en) | 2019-12-04 | 2019-12-04 | Chip stacking and packaging structure and process method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911226398.XA CN110890284A (en) | 2019-12-04 | 2019-12-04 | Chip stacking and packaging structure and process method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN110890284A true CN110890284A (en) | 2020-03-17 |
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| CN201911226398.XA Pending CN110890284A (en) | 2019-12-04 | 2019-12-04 | Chip stacking and packaging structure and process method thereof |
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| CN (1) | CN110890284A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115052420A (en) * | 2022-06-17 | 2022-09-13 | 河南驰诚电气股份有限公司 | Circuit board with electronic circuit laminated design and design method thereof |
-
2019
- 2019-12-04 CN CN201911226398.XA patent/CN110890284A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115052420A (en) * | 2022-06-17 | 2022-09-13 | 河南驰诚电气股份有限公司 | Circuit board with electronic circuit laminated design and design method thereof |
| CN115052420B (en) * | 2022-06-17 | 2024-01-19 | 河南驰诚电气股份有限公司 | Circuit board for electronic circuit lamination design and design method thereof |
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