CN215008217U - High-speed high-reliability DFN packaging lead frame of MOS (metal oxide semiconductor) transistor and MOS transistor - Google Patents
High-speed high-reliability DFN packaging lead frame of MOS (metal oxide semiconductor) transistor and MOS transistor Download PDFInfo
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- CN215008217U CN215008217U CN202121482930.7U CN202121482930U CN215008217U CN 215008217 U CN215008217 U CN 215008217U CN 202121482930 U CN202121482930 U CN 202121482930U CN 215008217 U CN215008217 U CN 215008217U
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- pins
- base island
- lead frame
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- mos
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to a MOS manages high-speed high reliability DFN encapsulation lead frame and the MOS pipe of DFN encapsulation, the lead frame includes lead frame unit, brace rod and cutting way, and every lead frame unit includes a base island and two rows of pins at least, and two rows of pins distribute in two sides of base island, the base island is connected through linking the muscle with some pins. After the DFN is adopted for packaging, the size is greatly reduced, the number of lead frame units borne by a single lead frame is greatly increased, the material cost of plastic packaging materials, metal wires, electroplating and the like is greatly reduced, the production efficiency is improved, and rich profit returns can be generated. The heat generated by the MOSFET chip is firstly conducted to the base island, and then the base island is quickly conducted out through the pins, so that the heat dissipation area is increased, the integral heat dissipation performance of the product is enhanced, in addition, the ultrathin packaging thickness of the DFN packaging is more beneficial to the integral heat dissipation of the product, and the service life and the reliability of the product are improved.
Description
Technical Field
The utility model relates to the technical field of, especially, relate to a MOS manages MOS pipe of high-speed high reliability DFN encapsulation lead frame and DFN encapsulation.
Background
With the rapid development of the micro-miniature and portable electronic products, such as smart watches, bluetooth headsets, small detection devices, and the like, and the cost consideration of the integrated circuit industry, the integrated circuit is rapidly developed to the DFN and QFN products with smaller volume and thinner thickness. Some manufacturers directly require a packaging factory to design and package the original SOP8L product with a larger volume into DFN and QFN products, for example, the volume of a conventional MOS transistor packaged by SOP8L is 4.9 × 3.9 × 1.55mm, specifically, as shown in fig. 1 and 2, the number of lead frame units on each lead frame is only 256, the production efficiency is low, the production cost is high, and this puts higher requirements on design and process reliability for the packaging factory.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a MOS manages high-speed high reliability DFN encapsulation lead frame and the MOS pipe of DFN encapsulation, adopt the DFN encapsulation, small in size, the cost is reduced moreover.
The utility model discloses a realize like this: the utility model provides a high-speed high reliability DFN encapsulation lead frame of MOS pipe, includes lead frame unit, brace rod and cutting way, and every lead frame unit includes a base island and two rows of pins at least, and two rows of pins distribute in two sides of base island, the base island passes through even muscle with some pins and is connected.
The base material of the lead frame is copper, and the upper surface layer is plated with silver.
The size of a single lead frame is 258mm × 78mm, the number of loaded lead frame units is 2856, and the size of a base island is 2.8 × 1.8 mm.
And 4 pins are arranged on two sides of the base island, and 4 pins of one row of pins are connected with the base island through connecting ribs.
Wherein, still through the side even muscle half-connection between 4 pins of being connected with the base island, also through the side even muscle half-connection between 3 pins in the other row of pin, the side even muscle bottom surface is half etching.
The utility model provides another kind of technical scheme does: the utility model provides a MOS pipe of DFN encapsulation, includes the base island, two rows of pins, MOSFET chip, metal wire and plastic-sealed body, and two rows of pins distribute in two sides of base island, the base island is connected through even muscle with some pins, the MOSFET chip passes through the conducting resin to be fixed on the base island, and the base island forms a circuit port, and the MOSFET chip still realizes electrical connection through metal wire and other pins, the plastic-sealed body is used for parcel and protection base island, pin, MOSFET chip and metal wire.
Wherein, the encapsulation size of MOS pipe is 3.3 x 0.75 mm.
And 4 pins are arranged on two sides of the base island, and 4 pins in one row of pins are connected with the base island through connecting ribs.
Wherein, still through the side even muscle half-connection between 4 pins of being connected with the base island, also through the side even muscle half-connection between 3 pins in the other row of pin, the side even muscle bottom surface is half etching.
And the lower surfaces of the base island and the pins are exposed out of the plastic package body to form a heat dissipation surface.
The utility model has the advantages that: after the DFN is adopted for packaging, the size is greatly reduced, the number of lead frame units borne by a single lead frame is greatly increased, the material cost of plastic packaging materials, metal wires, electroplating and the like is greatly reduced, the production efficiency is improved, and rich profit returns can be generated. Because the MOS tube has large heat productivity, the MOS tube is easy to be damaged due to poor heat dissipation of a product, and the heat dissipation problem needs to be considered in order to ensure the reliability of the product, the applicant does not use the design scheme that the base island and the pins of a common DFN lead frame are separated, but connects the base island with partial pins through connecting ribs, the heat generated by the MOSFET chip is firstly conducted to the base island, and then the base island is quickly conducted out through the pins, which is equivalent to increase the heat dissipation area and enhance the integral heat dissipation performance of the product.
Drawings
FIG. 1 is a top view of a prior art SOP8L package structure;
FIG. 2 is a side view of a prior art SOP8L package structure;
fig. 3 is a schematic structural view (front side) of the high-speed and high-reliability DFN package lead frame of the MOS transistor according to the present invention;
fig. 4 is a schematic structural view (back side) of the high-speed and high-reliability DFN package lead frame of the MOS transistor according to the present invention;
fig. 5 is a schematic cross-sectional view of a DFN packaged MOS transistor according to the present invention;
fig. 6 is a perspective view of a DFN-packaged MOS transistor according to the present invention.
1. A lead frame unit; 11. a base island; 12. a pin; 13. connecting the ribs; 14. connecting ribs on the side surface; 15. supporting ribs; 16. cutting a channel; 2. a MOSFET chip; 3. a metal wire; 4. molding the body; 5. and (3) conductive adhesive.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As the embodiment of the high-speed high reliability DFN package lead frame of MOS pipe, as shown in fig. 3 and fig. 4, including lead frame unit 1, brace rod 15 and cutting way 16, every lead frame unit 1 includes a base island 11 and two rows of pins 12 at least, and two rows of pins 12 distribute in two sides of base island 11, base island 11 is connected through even muscle 13 with partial pin 12.
As an embodiment of the MOS pipe of DFN encapsulation, as shown in fig. 5 and fig. 6, including base island 11, two rows of pins 12, MOSFET chip 2, metal wire 3 and plastic-sealed body 4, two rows of pins 12 distribute in two sides of base island 11, base island 11 is connected through even muscle 13 with partial pin 12, MOSFET chip 2 passes through conducting resin 5 to be fixed on base island 11, and base island 11 forms a circuit port, and MOSFET chip 2 still realizes electrical connection through metal wire 3 and other pins, plastic-sealed body 4 is used for parcel and protection base island 11, pin 12, MOSFET chip 2 and metal wire 3.
After the DFN is adopted for packaging, the size is greatly reduced, the number of the lead frame units 1 borne by a single lead frame is greatly increased, the material cost of plastic packaging materials, metal wires, electroplating and the like is greatly reduced, the production efficiency is improved, and the full profit return can be generated. Because the MOS tube has large heat productivity, the MOS tube is easy to be damaged due to poor heat dissipation of a product, and in order to ensure the reliability of the product, the heat dissipation problem needs to be considered, the applicant does not use the design scheme that the base island of a common DFN lead frame is separated from the pins, but connects the base island 11 with partial pins 12 through connecting ribs 13, the heat generated by the MOSFET chip 2 is firstly conducted to the base island 11, and then the base island 11 is quickly conducted out through the pins 12, which is equivalent to increasing the heat dissipation area and enhancing the integral heat dissipation performance of the product.
In this embodiment, the base material of the lead frame is copper, and the upper surface layer is silver-plated (the sand spot portion in fig. 3 is a silver-plated region). The conduction performance between the MOSFET chip 2 and the base island 11 can be increased.
In this embodiment, the size of a single lead frame is 258mm × 78mm, the number of the lead frame units 1 to be loaded is 2856, compared with the original SOP8L packaging structure, the number is increased by 11 times, the size of the base island is 2.8 × 1.8mm, and the application of the MOS transistor product with the maximum chip size of 2.7 × 1.77mm can be satisfied. In this embodiment, two sides of the base island are provided with 4 pins, and 4 pins of one row of pins are connected with the base island through connecting ribs. The packaging size of the MOS tube is 3.3 x 0.75 mm. Compared with the SOP8L packaging structure, the volume is reduced to 27%.
In this embodiment, 4 pins connected to the base island 11 are also half-connected by the side rib 14, and 3 pins in another row of pins are also half-connected by the side rib 14, and the bottom surface of the side rib 14 is half-etched (as shown by the shaded portion in fig. 4). When in plastic packaging, plastic packaging materials are injected to form a lock catch type structure, so that the bonding strength of the base island part and the plastic packaging body part is enhanced, and the anti-delamination capability of the whole product is further enhanced.
In this embodiment, the lower surfaces of the base island 11 and the pins 12 are exposed out of the plastic package body 4 to form a heat dissipation surface, which can be in close contact with a PCB at an application end, thereby enhancing the overall heat dissipation performance of the product.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. The high-speed high-reliability DFN packaging lead frame for the MOS tube is characterized by comprising lead frame units, support ribs and cutting channels, wherein each lead frame unit at least comprises a base island and two rows of pins, the two rows of pins are distributed on two sides of the base island, and the base island is connected with part of the pins through connecting ribs.
2. The high-speed high-reliability DFN packaging lead frame for MOS tube of claim 1, wherein the base material of the lead frame is copper, and the upper surface layer is silver-plated.
3. The high-speed high-reliability DFN packaging lead frame of MOS tube of claim 1, wherein the single lead frame size is 258mm x 78mm, the number of lead frame units carried is 2856, and the size of the base island is 2.8 x 1.8 mm.
4. The high-speed high-reliability DFN packaging lead frame for MOS tube according to claim 1, wherein 4 pins are arranged on both sides of the base island, and wherein 4 pins of one row of pins are connected with the base island through connecting ribs.
5. The high-speed high-reliability DFN packaging lead frame for MOS tube according to claim 4, wherein 4 pins connected with the base island are also half-connected through side connecting ribs, 3 pins in another row of pins are also half-connected through side connecting ribs, and the bottom surfaces of the side connecting ribs are half-etched.
6. The utility model provides a MOS pipe of DFN encapsulation, its characterized in that, includes base island, two rows of pins, MOSFET chip, metal wire and plastic-sealed body, and two rows of pins distribute in the both sides of base island, the base island passes through even muscle with some pins and is connected, the MOSFET chip passes through conducting resin and fixes on the base island, and the base island forms a circuit port, and the MOSFET chip still realizes electrical connection through metal wire and other pins, the plastic-sealed body is used for parcel and protection base island, pin, MOSFET chip and metal wire.
7. The DFN packaged MOS transistor of claim 6, wherein the package size of the MOS transistor is 3.3 x 0.75 mm.
8. The DFN packaged MOS tube of claim 6, wherein 4 pins are disposed on both sides of the base island, and wherein 4 pins in a row of pins are connected to the base island through the connecting rib.
9. The DFN packaged MOS transistor of claim 8, wherein 4 pins connected to the base island are also half-connected by a side rib, 3 pins in another row are also half-connected by a side rib, and a bottom surface of the side rib is half-etched.
10. The DFN packaged MOS device of claim 9, wherein the lower surfaces of the base island and the leads are exposed from the molding compound to form a heat spreader.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121482930.7U CN215008217U (en) | 2021-06-30 | 2021-06-30 | High-speed high-reliability DFN packaging lead frame of MOS (metal oxide semiconductor) transistor and MOS transistor |
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| CN202121482930.7U CN215008217U (en) | 2021-06-30 | 2021-06-30 | High-speed high-reliability DFN packaging lead frame of MOS (metal oxide semiconductor) transistor and MOS transistor |
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| CN215008217U true CN215008217U (en) | 2021-12-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117637661A (en) * | 2024-01-26 | 2024-03-01 | 中科华艺(天津)科技有限公司 | RF (radio frequency) chip packaging structure with switching characteristic and manufacturing method thereof |
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2021
- 2021-06-30 CN CN202121482930.7U patent/CN215008217U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117637661A (en) * | 2024-01-26 | 2024-03-01 | 中科华艺(天津)科技有限公司 | RF (radio frequency) chip packaging structure with switching characteristic and manufacturing method thereof |
| CN117637661B (en) * | 2024-01-26 | 2024-04-05 | 中科华艺(天津)科技有限公司 | RF (radio frequency) chip packaging structure with switching characteristic and manufacturing method thereof |
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