CN209804635U - Large-current semiconductor power device beneficial to welding - Google Patents
Large-current semiconductor power device beneficial to welding Download PDFInfo
- Publication number
- CN209804635U CN209804635U CN201920812348.9U CN201920812348U CN209804635U CN 209804635 U CN209804635 U CN 209804635U CN 201920812348 U CN201920812348 U CN 201920812348U CN 209804635 U CN209804635 U CN 209804635U
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- lead
- chip
- pin
- power device
- bonding
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a semiconductor device, especially one kind has one kind and does benefit to welded heavy current semiconductor power device, belongs to semiconductor device packaging technology field. The high-current semiconductor power device facilitating welding comprises: the lead frame comprises a chip carrier base island region and a pin assembly; the lead assembly comprises a first lead, and the first lead comprises a bonding part and a leading-out part; the semiconductor chip is arranged in the chip carrier base island region and is connected with the bonding part of the first pin through a bonding part; and the packaging resin covers and seals the semiconductor chip, the bonding piece and the pin assembly on the lead frame, and the leading-out parts of the first pins are exposed out of the packaging resin. The high-current semiconductor power device which is beneficial to welding has high current capacity, low thermal resistance and low parasitic inductance, and is easy for PCB welding, so that the current capacity is stronger.
Description
Technical Field
The utility model relates to a semiconductor device, especially one kind has a heavy current semiconductor power device, belongs to semiconductor device encapsulation technical field.
background
Electronic products are moving towards portability, miniaturization, networking and multimedia, and power semiconductor packages are moving from through-hole to surface mount packages. The surface packaging structure of the semiconductor power device adopts a lead frame packaging mode mostly, namely chips after scribing are welded on the lead frame through welding materials, and pins of the lead frame and the surfaces of the chips are connected through metal materials to realize electric communication.
As the complexity of portable systems increases, the individual components that make up the system are required to be smaller and smaller, and QFN/DFN (Quad Flat No-Lead/Dual Flat No-Lead) packages are often used. The QFN/DFN package has small volume, improved packaging density and high current capacity, welding electrodes extending out of resin materials are small and short, the cross section of the welding electrodes is an unplated part, so that the welding performance with a PCB (printed circuit board) is poor in an SMT (surface mounting technology) process, and welding positions are located on the side face and the bottom face of a plastic package body, so that a visual detection system is difficult to identify.
Issues of significant concern in semiconductor power device packaging include high heat dissipation, low parasitic inductance, and low electrical resistance between the semiconductor device and surrounding circuitry. In high current applications, the current capability of a power device is often dependent on the number of leads bonded on the package lead frame and the bonding area between the leads and the PCB board. The QFN/DFN package has small pin current capability, small welding area with a PCB (printed circuit board), and large thermal resistance, so that the performance of the device is poor in large-current application.
Disclosure of Invention
In order to solve the not enough of existence among the prior art, the utility model provides a do benefit to welded heavy current semiconductor power device, do benefit to welded heavy current semiconductor power device and have heavy current ability, low thermal resistance, low parasitic inductance, and easily PCB welding for the current capacity is stronger.
according to the utility model provides a technical scheme, as the utility model provides a do benefit to welded heavy current semiconductor power device, do benefit to welded heavy current semiconductor power device and include:
the lead frame comprises a chip carrier base island region and a pin assembly; the pin assembly comprises a first pin and a second pin, and the first pin and the second pin respectively comprise a bonding part and a leading-out part;
The semiconductor chip is arranged in the chip carrier base island region and is respectively connected with the bonding parts of the first pin and the second pin through the bonding parts;
And the semiconductor chip, the bonding piece and the pin assembly are covered and sealed on the lead frame by the packaging resin, and the leading-out parts of the first pin and the second pin are exposed out of the packaging resin.
further, the semiconductor chip comprises a first main face and a second main face which are opposite, the first main face of the semiconductor chip is arranged in the chip base island area of the lead frame, and the second main face of the semiconductor chip is connected with the pin assembly through the bonding piece.
Further, the semiconductor chip comprises an IGBT chip and an FRD chip or a MOSFET chip.
Furthermore, the first main surface of the MOSFET chip is a drain electrode, and the second main surface is provided with a gate electrode and a source electrode; the source electrode of the MOSFET chip is connected with the bonding part of the first lead, and the grid electrode of the MOSFET chip is connected with the bonding part of the second lead.
Furthermore, the first main surface of the IGBT chip is a collector, the second main surface is provided with a gate and an emitter, the emitter of the IGBT chip is connected with the bonding part of the first pin, and the gate is connected with the bonding part of the second pin;
The first main surface of the FRD chip is a cathode, the second main surface of the FRD chip is an anode, and the anode of the FRD chip is connected with the bonding part of the first lead.
Further, the second lead and the first lead are isolated by the encapsulation resin.
Furthermore, a plurality of leading-out parts of the first pins are in a comb shape; the first pin further comprises a connecting part, and the leading-out parts of the first pin are connected in pairs through the connecting part.
Further, the width range of the second pin-out part and each first pin-out part is 0.5mm ~ 3mm, the length range is 0.65mm ~, and the distance range between two adjacent pin-out parts of the first pin is 0.5mm ~ 3 mm.
Further, the bonding member is a metal lead or a metal sheet.
From the foregoing, it can be seen that the utility model provides a do benefit to welded heavy current semiconductor power device, compare with prior art and possess following advantage:
the utility model belongs to a semiconductor power device of SMD encapsulation, and the demand that is connected between the circuit board and satisfies electronic equipment large-scale automated production more easily.
two, the utility model discloses when being connected with the PCB circuit board, first pin derivation part and second pin derivation part surpass encapsulation resin, and surpass length and be greater than 0.5mm for easily weld, and easily welding quality's detection.
Drawings
Fig. 1 is a schematic structural diagram of a first embodiment of the first aspect of the present invention.
fig. 2 is a schematic structural diagram of a first embodiment of the first aspect of the present invention.
fig. 3 is a schematic structural diagram of a second embodiment of the first aspect of the present invention.
Fig. 4 is a schematic structural diagram of a first embodiment of the connecting portion according to the first aspect of the present invention.
Fig. 5 is a schematic structural diagram of a second embodiment of the connecting portion according to the first aspect of the present invention.
Fig. 6 is a schematic structural diagram of a third embodiment of the connecting portion according to the first aspect of the present invention.
fig. 7 is a schematic structural view of a first embodiment of a cross section in the first aspect of the present invention.
Fig. 8 is a schematic structural view of a second embodiment of the cross section in the first aspect of the present invention.
100. The semiconductor package comprises a lead frame, 110, a chip carrier island region, 120, a first lead, 131, a bonding part, 132, a lead-out part, 133, a connecting part, 140, a second lead, 200, a semiconductor chip, 210, a second main surface, 300, a bonding part and 400, packaging resin.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. In which like parts are designated by like reference numerals. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.
This conduct the utility model provides a do benefit to welded large current semiconductor power device's first kind of embodiment, do benefit to welded large current semiconductor power device's first kind of embodiment and include:
As shown in fig. 1 and 2, the lead frame 100 includes a carrier substrate island 110 and a lead assembly, the lead assembly includes a first lead 120 and a second lead 140 arranged side by side, the first lead 120 and the second lead 140 respectively include a bonding portion 131 and a lead portion 132 connected as a whole, the second lead 140 and the first lead 120 are isolated by the encapsulation resin 400, the lead portions 132 of the first lead 120 are multiple, the lead portions 132 of the first lead 120 are comb-shaped, the first lead 120 further includes a connecting portion 133, the lead portions 132 of the first lead 120 are connected two by two through the connecting portion 133, and the connecting portion 133 is arranged in three manners as shown in fig. 4 ~ and fig. 6.
A semiconductor chip 200, as shown in fig. 1 and 2, the semiconductor chip 200 includes a first main surface and a second main surface 210 opposite to each other, the first main surface of the semiconductor chip 200 is soldered to the carrier land 110 of the lead frame 100, the second main surface 210 of the semiconductor chip 200 is connected to the bonding portion 131 of the first lead 120 through a bonding member 300, and the bonding portion 131 of the second lead 140 is connected. Specifically, as shown in fig. 1 and 2, the semiconductor chip 200 is a MOSFET chip, a first main surface of the MOSFET chip is a drain, and a second main surface 210 is provided with a gate and a source; the source of the MOSFET chip is connected to the bonding portion 131 of the first lead 120, and the gate is connected to the bonding portion 131 of the second lead 140. As shown in fig. 1 and 2, the bonding element 300 connecting the source of the MOSFET chip to the bonding portion 131 of the first lead 120 is a metal piece, and the bonding element 300 connecting the gate of the MOSFET chip to the bonding portion 131 of the second lead 140 is a metal wire.
As shown in fig. 1, 7 and 8, the package resin 400 covers the semiconductor chip 200, the bonding element 300, the bonding portions 131 of the first leads 120 and the bonding portions 131 of the second leads 140 on the lead frame 100, and the lead portions 132 of the first leads 120 and the lead portions 132 of the second leads 140 are exposed from the package resin 400.
Specifically, the width of each lead-out portion 132 of the first pin 120 and the width of the lead-out portion 132 of the second pin 140 range from 0.5mm ~ 3mm, the length of each lead-out portion 132 of the first pin 120 and the length of the lead-out portion 132 of the second pin 140 range from 0.65mm ~ 10mm, the distance between two adjacent lead-out portions 132 of the first pin 120 ranges from 0.5mm ~ 3mm, and the distance between the lead-out portion 132 of the second pin 140 and the lead-out portion 132 of the first pin 120 adjacent thereto ranges from 0.5mm ~ 3 mm.
It can be understood that, firstly, the bonding portions 131 of the first leads 120 and the bonding portions 131 of the second leads 140 are wrapped by the packaging resin 400, the lead-out portions 132 of the first leads 120 and the lead-out portions 132 of the second leads 140 are exposed out of the packaging resin 400, and the lead-out portions 132 of the first leads 120 and the lead-out portions 132 of the second leads 140 are designed to make solder paste smoothly climb to the inside and the side edges of the comb teeth when the solder paste is soldered to a PCB, so that the bonding between the pins and the PCB is enhanced, and the problem of poor soldering is avoided. Secondly, the connection part of the first pin 120 connects the lead-out parts 132 of the first pin 120 two by two, so that the contact area between the source electrode pin of the device and the PCB is increased, and the current capability of the device in the application of a system is improved.
This conduct the utility model discloses a first aspect provides a do benefit to welded large current semiconductor power device's second kind embodiment, do benefit to welded large current semiconductor power device second kind embodiment and include:
The lead frame 100 comprises a carrier substrate island region 110 and a lead assembly as shown in fig. 3, wherein the lead assembly comprises a first lead 120 and a second lead 140 which are arranged side by side, the first lead 120 and the second lead 140 respectively comprise a bonding part 131 and a leading-out part 132 which are connected into a whole, the second lead 140 and the first lead 120 are isolated by packaging resin 400, the leading-out parts 132 of the first lead 120 are multiple, the leading-out parts 132 of the first leads 120 are in a comb-tooth shape, the first lead 120 further comprises connecting parts 133, the leading-out parts 132 of the first lead 120 are connected in pairs through the connecting parts 133, and the arrangement mode of the connecting parts 133 comprises three modes as shown in fig. 3 ~ and fig. 5.
The semiconductor chip 200, as shown in fig. 3, the semiconductor chip 200 includes a first main surface and a second main surface 210 opposite to each other, the first main surface of the semiconductor chip 200 is soldered to the carrier base island 110 of the lead frame 100, the second main surface 210 of the semiconductor chip 200 is connected to the bonding portion 131 of the first lead 120 through the bonding member 300, and the bonding portion 131 of the second lead 140 is connected.
Specifically, as shown in fig. 3, the semiconductor chip 200 includes an IGBT chip and an FRD chip, the first main surface of the IGBT chip is a collector, the collector of the IGBT chip is soldered to the carrier land 110 of the lead frame 100, the second main surface 210 is provided with a gate and an emitter, the emitter of the IGBT chip is connected to the bonding portion 131 of the first lead 120, and the gate is connected to the bonding portion 131 of the second lead 140; the first main surface of the FRD chip is a cathode, the cathode of the FRD chip is soldered to the carrier base island 110 of the lead frame 100, the second main surface 210 is an anode, and the anode of the FRD chip is connected to the bonding portion 131 of the first lead 120. As shown in fig. 6, the bonding material 300 connecting the emitter of the IGBT chip and the bonding portion 131 of the first lead 120 is a metal piece, the bonding material 300 connecting the gate of the IGBT chip and the bonding portion 131 of the second lead 140 is a metal wire, and the bonding material 300 connecting the anode of the FRD chip and the bonding portion 131 of the first lead 120 is a metal piece.
And an encapsulation resin 400, as shown in fig. 1, 7 and 8, wherein the encapsulation resin 400 covers the semiconductor chip 200, the bonding element 300, the bonding portion 131 of the first lead 120 and the bonding portion 131 of the second lead 140 on the lead frame 100, and the lead-out portions 132 of the first lead 120 and the second lead 140 are exposed from the encapsulation resin 400.
Specifically, the width of each lead-out portion 132 of the first pin 120 and the width of the lead-out portion 132 of the second pin 140 range from 0.5mm ~ 3mm, the length of each lead-out portion 132 of the first pin 120 and the length of the lead-out portion 132 of the second pin 140 range from 0.65mm ~ 10mm, the distance between two adjacent lead-out portions 132 of the first pin 120 ranges from 0.5mm ~ 3mm, and the distance between the lead-out portion 132 of the second pin 140 and the lead-out portion 132 of the first pin 120 adjacent thereto ranges from 0.5mm ~ 3 mm.
it can be understood that, firstly, the bonding portions 131 of the first leads 120 and the bonding portions 131 of the second leads 140 are wrapped by the packaging resin 400, the lead-out portions 132 of the first leads 120 and the lead-out portions 132 of the second leads 140 are exposed out of the packaging resin 400, and the lead-out portions 132 of the first leads 120 and the lead-out portions 132 of the second leads 140 are designed to make solder paste smoothly climb to the inside and the side edges of the comb teeth when the solder paste is soldered to a PCB, so that the bonding between the pins and the PCB is enhanced, and the problem of poor soldering is avoided. Secondly, the connection part of the first pin 120 connects the lead-out parts 132 of the first pin 120 two by two, so that the contact area between the source electrode pin of the device and the PCB is increased, and the current capability of the device in the application of a system is improved.
Those of ordinary skill in the art will understand that: the above description is only for the specific embodiments of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. a high current semiconductor power device facilitating welding, comprising:
A lead frame (100), the lead frame (100) including a carrier-based island (110) and a pin assembly; the lead assembly comprises a first lead (120) and a second lead (140), wherein the first lead (120) and the second lead (140) respectively comprise a bonding part (131) and a leading-out part (132) which are connected into a whole;
The semiconductor chip (200) is arranged in the chip carrier base island region (110), and the semiconductor chip (200) is respectively connected with bonding parts (131) of the first lead (120) and the second lead (140) through bonding parts (300);
And the packaging resin (400) covers and seals the semiconductor chip (200), the bonding piece (300) and the pin assembly on the lead frame (100), and the leading-out parts (132) of the first pin (120) and the second pin (140) are exposed from the packaging resin (400).
2. The high current semiconductor power device facilitating soldering of claim 1, wherein the semiconductor chip (200) includes opposing first and second major faces (210), the first major face of the semiconductor chip (200) being disposed on the carrier pad region (110) of the lead frame (100), the second major face (210) of the semiconductor chip (200) being connected to the lead assembly by a bond (300).
3. The high-current semiconductor power device facilitating welding according to claim 2, wherein the semiconductor chip (200) comprises an IGBT chip and an FRD chip, or a MOSFET chip.
4. a high current semiconductor power device facilitating bonding according to claim 3, wherein the first major surface of the MOSFET die is a drain, and the second major surface (210) is provided with a gate and a source; the source of the MOSFET chip is connected with the bonding part (131) of the first lead (120), and the gate of the MOSFET chip is connected with the bonding part (131) of the second lead (140).
5. A high current semiconductor power device facilitating soldering according to claim 3,
The first main surface of the IGBT chip is a collector, the second main surface (210) is provided with a gate and an emitter, the emitter of the IGBT chip is connected with the bonding part (131) of the first lead (120), and the gate is connected with the bonding part (131) of the second lead (140);
The first main surface of the FRD chip is a cathode, the second main surface (210) is an anode, and the anode of the FRD chip is connected with the bonding part (131) of the first lead (120).
6. The high current semiconductor power device facilitating soldering of claim 1, wherein the second pin (140) is isolated from the first pin (120) by the encapsulation resin (400).
7. The high-current semiconductor power device facilitating welding as claimed in claim 1, wherein the plurality of lead-out portions (132) of the first pins (120) are provided, and the lead-out portions (132) of the plurality of first pins (120) are comb-shaped.
8. A high current semiconductor power device facilitating soldering according to claim 7, wherein the width of the lead-out portion (132) of the second pin (140) and the lead-out portion (132) of each first pin (120) is in the range of 0.5mm ~ 3mm, the length of the lead-out portion is in the range of 0.65mm ~ 10mm, and the distance between two adjacent lead-out portions (132) of the first pins (120) is in the range of 0.5mm ~ 3 mm.
9. A high current semiconductor power device facilitating soldering according to claim 1, wherein the bonding member (300) is a metal lead or a metal sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920812348.9U CN209804635U (en) | 2019-05-31 | 2019-05-31 | Large-current semiconductor power device beneficial to welding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920812348.9U CN209804635U (en) | 2019-05-31 | 2019-05-31 | Large-current semiconductor power device beneficial to welding |
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| Publication Number | Publication Date |
|---|---|
| CN209804635U true CN209804635U (en) | 2019-12-17 |
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| CN201920812348.9U Active CN209804635U (en) | 2019-05-31 | 2019-05-31 | Large-current semiconductor power device beneficial to welding |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110164831A (en) * | 2019-05-31 | 2019-08-23 | 无锡电基集成科技有限公司 | Conducive to the high-current semiconductor power device and its manufacturing method of welding |
| CN113053850A (en) * | 2021-03-16 | 2021-06-29 | 苏州悉智科技有限公司 | Power module packaging structure |
| CN116779574A (en) * | 2023-08-08 | 2023-09-19 | 深圳市锐骏半导体股份有限公司 | Semiconductor device integrated with sampling resistor and manufacturing method thereof |
-
2019
- 2019-05-31 CN CN201920812348.9U patent/CN209804635U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110164831A (en) * | 2019-05-31 | 2019-08-23 | 无锡电基集成科技有限公司 | Conducive to the high-current semiconductor power device and its manufacturing method of welding |
| CN113053850A (en) * | 2021-03-16 | 2021-06-29 | 苏州悉智科技有限公司 | Power module packaging structure |
| CN116779574A (en) * | 2023-08-08 | 2023-09-19 | 深圳市锐骏半导体股份有限公司 | Semiconductor device integrated with sampling resistor and manufacturing method thereof |
| CN116779574B (en) * | 2023-08-08 | 2024-04-19 | 深圳市锐骏半导体股份有限公司 | Semiconductor device integrated with sampling resistor and manufacturing method thereof |
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