CN113053850A - Power module packaging structure - Google Patents

Power module packaging structure Download PDF

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Publication number
CN113053850A
CN113053850A CN202110279220.2A CN202110279220A CN113053850A CN 113053850 A CN113053850 A CN 113053850A CN 202110279220 A CN202110279220 A CN 202110279220A CN 113053850 A CN113053850 A CN 113053850A
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China
Prior art keywords
bonding region
bonding
region
power device
power
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CN202110279220.2A
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Chinese (zh)
Inventor
蔡超峰
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Suzhou Xizhi Technology Co ltd
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Suzhou Xizhi Technology Co ltd
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Priority to CN202110279220.2A priority Critical patent/CN113053850A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Inverter Devices (AREA)

Abstract

A power module packaging structure comprises a substrate and at least two power devices arranged on the substrate, wherein the at least two power devices comprise a first power device and a second power device; the substrate is provided with a first mounting area connected with a first electrode of the first power device, a first bonding area connected with a second electrode of the first power device, a second mounting area connected with a first electrode of the second power device and a second bonding area connected with a second electrode of the second power device; the first power device and the second power device are formed with a minimum distance area in the first direction, and at least part of the first bonding area and at least part of the second bonding area are overlapped with the minimum distance area. The novel LED lamp has a simple structure, and can achieve the purpose of facilitating current grade expansion while improving the production efficiency.

Description

Power module packaging structure
[ technical field ] A method for producing a semiconductor device
The invention relates to a power module packaging structure, and belongs to the technical field of semiconductors.
[ background of the invention ]
The packaging of the module is the most basic component of a power module and is critical to the performance, volume and reliability of the power module. Therefore, when designing the circuit layout of the power module package, different circuit topologies are often designed separately, but performance and efficiency are sacrificed.
Accordingly, there is a need for improvements in the art that overcome the deficiencies in the prior art.
[ summary of the invention ]
The invention aims to provide a power module packaging structure which is simple in structure, and can achieve the purpose of facilitating current grade expansion while improving the production efficiency.
The purpose of the invention is realized by the following technical scheme: a power module packaging structure comprises a substrate and at least two power devices arranged on the substrate, wherein the at least two power devices comprise a first power device and a second power device;
the substrate is provided with a first mounting area connected with a first electrode of the first power device, a first bonding area connected with a second electrode of the first power device, a second mounting area connected with a first electrode of the second power device and a second bonding area connected with a second electrode of the second power device;
wherein the first power device and the second power device are formed with a minimum pitch region in a first direction, and at least a portion of the first bonding region and at least a portion of the second bonding region overlap the minimum pitch region.
In one embodiment, at least a portion of the first bonding region and at least a portion of the second bonding region are disposed in parallel.
In one embodiment, the current routing direction of at least a portion of the first bonding region is the same as the current routing direction of the second bonding region.
In one embodiment, a third bonding region is further disposed on the substrate, and at least a portion of the third bonding region overlaps with the minimum pitch region.
In one embodiment, at least a portion of the third bonding region is disposed in parallel with at least a portion of the first bonding region or at least a portion of the second bonding region, and a current routing direction of at least a portion of the third bonding region is opposite to a current routing direction of the first bonding region or the second bonding region.
In one embodiment, at least a portion of the third bonding region is disposed between the first bonding region and the second bonding region; or, at least a portion of the third bonding region is disposed outside the first bonding region or the second bonding region.
In one embodiment, the substrate comprises an insulating layer, a metal circuit layer and a thermal diffusion layer, wherein the metal circuit layer and the thermal diffusion layer are oppositely arranged on two sides of the insulating layer, and the first power device and the second power device are arranged on the metal circuit layer through a connecting material.
In one embodiment, the connection material is any one of lead-free or high lead solder, sintered silver, and conductive silver paste.
In one embodiment, the second electrode of the first power device is connected to the first bonding region through a first bonding wire of a wire bond, and the second electrode of the second power device is connected to the second bonding region through a second bonding wire of a wire bond; the first connecting wire and the second connecting wire are any one of ultrasonically-bonded aluminum wires, copper wires and aluminum strips.
In one embodiment, the substrate is any one of a ceramic copper clad substrate, an insulating metal substrate, and an active metal brazing substrate.
Compared with the prior art, the invention has the following beneficial effects: at least part of the first bonding area and at least part of the second bonding area are overlapped with the minimum distance area, so that the bonding point wiring is facilitated, the increase of the bonding points is reduced to reduce the bonding time, the production efficiency of a lead bonding process during topology expansion is improved, the manufacturing cost is reduced, and the expansion of the current level is facilitated.
[ description of the drawings ]
Fig. 1 is a schematic structural diagram of a power package module structure in the prior art.
Fig. 2 is a schematic structural diagram of another power package module structure in the prior art.
Fig. 3 is a schematic structural diagram of another power package module structure in the prior art.
Fig. 4 is a schematic structural diagram of another power package module structure in the prior art.
Fig. 5 is a schematic cross-sectional view of a power package module structure according to the present invention.
Fig. 6 is a schematic structural diagram of a power package module structure according to a first embodiment of the invention.
Fig. 7 is another structural schematic diagram of a power package module structure in the first embodiment of the invention.
Fig. 8 is a schematic structural diagram of a power package module structure according to a second embodiment of the invention.
Fig. 9 is a schematic structural diagram of a power package module structure in a third embodiment of the invention.
Fig. 10 is another structural schematic diagram of a power package module structure in a third embodiment of the invention.
Fig. 11 is a schematic structural diagram of a power package module structure in a fourth embodiment of the invention.
[ detailed description ] embodiments
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprising" and "having," as well as any variations thereof, in the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, a conventional circuit layout of a circuit topology between two power devices is shown in fig. 1. Here, the two power devices are referred to as a first power device 20 and a second power device 30, respectively, and the first power core device and the second power device 30 are connected to the substrate 10 through a connection material. The first power device 20 is connected with the first positive electrode region 3 on the substrate 10 through a wire-bonded connection line; the second power device 30 is connected with the second positive electrode region 4 on the substrate 10 through a wire-bonded connection line; and the cathodes of the first power device 20 and the second power device 30 are connected to the first cathode region 1 and the second cathode region 2 on the substrate 10 through the connection material, respectively.
When a power device package with a larger current level is to be implemented, power semiconductor devices may be added to the existing circuit layout, for example, the number of the power semiconductor devices of the first power device 20 and the second power device 30 is increased to two, as shown in fig. 2. Although the current level is improved by increasing the number of devices, the number of connecting wires for wire bonding is not increased, and the wires are limited by the current, so that the current level of the power semiconductor module is limited. .
In addition, the layout of the circuit is usually changed by wire bonding technology in the prior art. As shown in fig. 3, by additionally adding a wire bonding point, the first positive electrode region 3 and the second positive electrode region 4 are electrically connected, so that a larger current power device is packaged. However, although this method does not require changing the circuit layout of the substrate 10, the number of wire bonding points is increased, which results in an increase in the process time of wire bonding and an increase in the bonding time, which affects the production efficiency of the power module.
As shown in fig. 4, the prior art also integrates the first positive electrode region 3 and the second positive electrode region 4, and integrates the first negative electrode region 1 and the second negative electrode region 2, so as to eliminate the disadvantage of the increase of the bonding points. However, a new material for the substrate 10 is introduced due to a change in the layout thereof, thereby increasing the mold opening cost and the management cost of the raw material.
Therefore, the present invention provides a power package module structure, which can eliminate the above-mentioned drawbacks of the prior art. Specifically, referring to fig. 5 to 11, a power module package structure in a preferred embodiment of the present invention includes a substrate 10 and at least two power devices disposed on the substrate 10, where the at least two power devices include a first power device 20 and a second power device 30. In this embodiment, only two power devices are provided, and indeed, in other embodiments, the number of the power devices may be other, which is not specifically limited herein and is determined according to the actual situation. The first power device 20 and the second power device 30 may be diodes, power MOSFET devices, or switching devices such as IGBTs and GaN. The embodiment of the present invention is described by taking a diode as an example.
Referring to fig. 5 specifically, the substrate 10 is any one of a ceramic copper-clad substrate 10, an insulating metal substrate 10 and an active metal brazing substrate 10, and indeed, in other embodiments, the substrate 10 may be made of other materials, which are not limited herein, depending on the actual situation. The substrate 10 includes an insulating layer 12, a metal wiring layer 13 and a thermal diffusion layer 11 oppositely disposed on both sides of the insulating layer 12, and the first power device 20 and the second power device 30 are disposed on the metal wiring layer 13 through a connection material 14. The connecting material 14 is any one of lead-free or high-lead solder, sintered silver, and conductive silver paste, and has high conductivity. Indeed, in other embodiments, the connecting material 14 may be other, and is not limited herein, as the case may be.
Referring to fig. 6, a first mounting region 1, a second mounting region 2, a first connection region 3 and a second connection region 4 are respectively disposed on a substrate 10, a first electrode of a first power device 20 is connected to the first mounting region 1 through the connection material, and a first electrode of a second power device 30 is connected to the second mounting region 2 through the connection material. In the above description, the power device is a diode, so in this embodiment, the first electrode is a cathode, the second electrode is an anode, accordingly, the first mounting region 1 is a first cathode region 1, the second mounting region 2 is a second cathode region 2, and the first connection region 3 and the second connection region 4 are the first anode connection region and the second anode connection region. If the first power device 20 and the second power device 30 are power MOSFET devices or IGBTs, the first electrode is a positive electrode and the second electrode is a negative electrode, which is opposite to the polarity of the diode. Accordingly, the polarities of the first mounting area 1, the second mounting area 2, the first connection area 3 and the second connection area 4 are also changed. In the present invention, the substrate 10 is further provided with a first bonding region 5 and a second bonding region 6, and the polarity properties of the first bonding region 5 and the second bonding region 6 are the same as those of the first connection region 3 and the second connection region 4, respectively. The first and second bonding regions 5, 6 are extensions of the first and second connection regions 3, 4, respectively, extending in the horizontal direction, with the direction of the arrow a as the horizontal direction.
Wherein the first power device 20 and the second power device 30 are formed with a minimum pitch region in the first direction, and at least a portion of the first bonding region 5 and at least a portion of the second bonding region 6 overlap the minimum pitch region. In the present embodiment, with the direction of the arrow b as the first direction, the minimum pitch region is an envelope region formed along the shortest connecting line between the outermost sides of the first power device 20 and the second power device 30 in the first direction of the substrate 10, as shown by a region a, which is actually the minimum pitch region. The purpose of this is to: when the packaging of the power device with a larger current level is realized, additional bonding points are not needed to be added, so that the bonding process time is saved, the topology expansion is realized at low cost, the production efficiency is improved, and the current level expansion is facilitated.
In the present embodiment, the overlapping area between the first bonding region 5 and the minimum pitch region is 40% of the entire area of the first bonding region 5, and similarly, the overlapping area between the second bonding region 6 and the minimum pitch region is 40% of the entire area of the second bonding region 6. Indeed, in other embodiments, the overlapping area of the first bonding region 5 and the second bonding region 6 with the minimum pitch region may be other, and is not specifically limited herein, depending on the actual situation.
Specifically, the second electrode of the first power device 20 is connected to the first bonding region 5 through a first bonding wire of wire bonding, and the second electrode of the second power device 30 is connected to the second bonding region 6 through a second bonding wire of wire bonding; the first connection line and the second connection line are any one of an ultrasonically bonded aluminum line, a copper line, and an aluminum tape. It is needless to say that the first connecting line and the second connecting line may be made of other materials, which are not specifically limited herein and are determined according to actual situations.
At least part of the first bonding region 5 and the second bonding region 6 are arranged in parallel, and the current routing direction of at least part of the first bonding region 5 is the same as the current routing direction of the second bonding region 6. In the present embodiment, the first bonding regions 5 and the second bonding regions 6 are substantially all parallel to facilitate the manufacture of the substrate 10 and to facilitate the subsequent layout thereof as the number of the first power devices 20 and the second power devices 30 increases. Indeed, in other embodiments, the first bonding area 5 and the second bonding area 6 may also be partially parallel, arranged according to practical requirements. Wherein substantially all parallel means: the parallel area of the first and second bonding regions 5, 6 is at least 90% of the area of the first and second bonding regions 5, 6 themselves.
Referring to fig. 9, a third bonding region 7 is further disposed on the substrate 10, the polarity of the third bonding region 7 is the same as the polarity of the second mounting region 2, and is also an extension of the second mounting region 2 along the horizontal direction, and at least a portion of the third bonding region 7 overlaps with the minimum pitch region. The overlapping condition between the third bonding region 7 and the minimum pitch region is the same as that of the first bonding region 5 or the second bonding region 6, and is not described herein again. Moreover, at least a portion of the third bonding region 7 is disposed in parallel with the first and second bonding regions 5, 6, which also facilitates the fabrication of the substrate 10 and the layout of the subsequent devices when the number of devices is increased. In the present embodiment, the third bonding region 7 is substantially entirely parallel to the first bonding region 5 or the second bonding region 6, so as to facilitate the manufacture of the substrate 10 and facilitate the subsequent layout thereof when the number of the first power devices 20 and the second power devices 30 is increased. Indeed, in other embodiments, the third bonding region 7 and the first bonding region 5 or the second bonding region 6 may also be partially parallel and arranged according to actual requirements. The meaning of substantially all parallels is the same as above, and will not be described herein.
Wherein, the current routing direction of at least part of the third bonding region 7 is opposite to the current routing direction of the first bonding region 5 or the second bonding region 6. This at least partly means: at least one current routing direction on the third bonding area 7 is opposite to the current routing direction of the first bonding area 5 or the second bonding area 6. And at least part of the third bonding region 7 is arranged between the first bonding region 5 and the second bonding region 6; alternatively, at least part of the third bonding region 7 is arranged outside the first bonding region 5 or the second bonding region 6. In this embodiment, the at least part means: 70% of the total area of the third bonding region 7 is disposed between the first bonding region 5 and the second bonding region 6, or outside the first bonding region 5 or the second bonding region 6. Indeed, in other embodiments, other ratios of the total area of the third bonded region are possible.
The power package module structure of the present invention will be described in detail with reference to several embodiments.
The first embodiment is as follows:
as shown in fig. 6 and 7, in the present embodiment, only 1 of the first power devices 20 and the second power devices 30 are provided, and only the first mounting region 1, the first connection region 3, the first bonding region 5, the second mounting region 2, the second connection region 4, and the second bonding region 6 are provided on the substrate 10. The first electrode of the first power device 20 is connected to the first mounting region 1 by a connecting material, and the second electrode of the first power device 20 is connected to the first bonding region 5 by a first connecting wire, and the second power device 30 is connected as described above. It should be noted that a first bonding point bonded to the first connection line is disposed in the first bonding region 5, a second bonding point bonded to the second connection line is disposed in the second bonding region 6, the sizes of the first bonding point and the second bonding point are smaller than the sizes of the first bonding region 5 and the second bonding region 6, and the region where the first bonding point and the second bonding point are disposed is a region where the first bonding region 5 and the second bonding region 6 overlap with the minimum pitch region.
When the first power device 20 and the second power device 30 need to be connected in parallel, only the first bonding point and the second bonding point need to be connected without adding additional bonding points, so that the purposes of reducing bonding time, improving the production efficiency of a lead bonding process during topology expansion and reducing the manufacturing cost are achieved.
Example two:
different from the first embodiment, in the present embodiment, if the current level needs to be expanded, the number of the first power device 20 and the number of the second power device 30 may be increased. Referring to fig. 8, in the present embodiment, the number of the first power device 20 and the second power device 30 is increased to two, and the increased first power device 20 and the increased second power device 30 are connected to the first connection region 5 and the second connection region 6 respectively by using the wire bonding process, so that no additional bonding point is added, and the effect of saving the bonding time is achieved. Meanwhile, since the added first and second power devices 20 and 30 are connected to the first and second connection regions 5 and 6, respectively, through the added connection lines, the current capacity thereof is not limited.
Example three:
referring to fig. 9, different from the second embodiment, in the present embodiment, a third bonding region 7 is further disposed on the substrate 10, the third bonding region 7 is disposed between the first bonding region 5 and the second bonding region 6, and the third bonding region 7 is parallel to the first bonding region 5 and the second bonding region 6. Which can implement a circuit topology at low cost as shown in fig. 10.
Example four:
referring to fig. 11, different from the first embodiment, in the present embodiment, two first power devices 20 and two second power devices 30 are provided, and a third bonding region 7 is further provided on the substrate 10, the third bonding region 7 is disposed between the first bonding region 5 and the second bonding region 6, and the third bonding region 7 is parallel to the first bonding region 5 and the second bonding region 6, which is specifically referred to fig. 7. In order to expand circuit topologies with different requirements, the first bonding point is disposed in the third bonding region 7 without changing the layout structure of the substrate 10, which is more convenient and faster.
In summary, the following steps: at least part of the first bonding region 5 and at least part of the second bonding region 6 are overlapped with the minimum distance region, so that the bonding points are convenient to wire, the increase of the bonding points is reduced to reduce the bonding time, the production efficiency of a lead bonding process during topology expansion is improved, the manufacturing cost is reduced, and the expansion of the current level is convenient.
The above is only one embodiment of the present invention, and any other modifications based on the concept of the present invention are considered as the protection scope of the present invention.

Claims (10)

1. A power module packaging structure is characterized by comprising a substrate and at least two power devices arranged on the substrate, wherein the at least two power devices comprise a first power device and a second power device;
the substrate is provided with a first mounting area connected with a first electrode of the first power device, a first bonding area connected with a second electrode of the first power device, a second mounting area connected with a first electrode of the second power device and a second bonding area connected with a second electrode of the second power device;
wherein the first power device and the second power device are formed with a minimum pitch region in a first direction, and at least a portion of the first bonding region and at least a portion of the second bonding region overlap the minimum pitch region.
2. The power module package structure of claim 1, wherein at least a portion of the first bonding region and at least a portion of the second bonding region are disposed in parallel.
3. The power module package structure of claim 1, wherein a current routing direction of at least a portion of the first bonding region is the same as a current routing direction of the second bonding region.
4. The power module package structure of claim 1, wherein a third bonding area is further disposed on the substrate, and at least a portion of the third bonding area overlaps the minimum pitch area.
5. The power module package structure of claim 4, wherein at least a portion of the third bonding region is disposed parallel to at least a portion of the first bonding region or at least a portion of the second bonding region, and a current routing direction of at least a portion of the third bonding region is opposite to a current routing direction of the first bonding region or the second bonding region.
6. The power module package structure of claim 4, wherein at least a portion of the third bonding region is disposed between the first bonding region and the second bonding region; or, at least a portion of the third bonding region is disposed outside the first bonding region or the second bonding region.
7. The power module package structure of claim 1, wherein the substrate comprises an insulating layer, a metal wiring layer and a thermal diffusion layer disposed opposite to each other on both sides of the insulating layer, and the first and second power devices are disposed on the metal wiring layer through a connection material.
8. The power module package structure of claim 7, wherein the connection material is any one of a lead-free or high lead solder, sintered silver, and conductive silver paste.
9. The power module package structure of claim 7, wherein the second electrode of the first power device is connected to the first bonding region by a first wire-bonded connection line, and the second electrode of the second power device is connected to the second bonding region by a second wire-bonded connection line; the first connecting wire and the second connecting wire are any one of ultrasonically-bonded aluminum wires, copper wires and aluminum strips.
10. The power module package structure of claim 7, wherein the substrate is any one of a ceramic copper clad substrate, an insulating metal substrate, and an active metal solder substrate.
CN202110279220.2A 2021-03-16 2021-03-16 Power module packaging structure Pending CN113053850A (en)

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