CN212084994U - Parallel packaged device group - Google Patents
Parallel packaged device group Download PDFInfo
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- CN212084994U CN212084994U CN202020822370.4U CN202020822370U CN212084994U CN 212084994 U CN212084994 U CN 212084994U CN 202020822370 U CN202020822370 U CN 202020822370U CN 212084994 U CN212084994 U CN 212084994U
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Abstract
The utility model discloses a device group of parallelly connected encapsulation, it includes: at least two semiconductor devices, the semiconductor devices including chips; the conductive connecting block is welded and combined with the front side or the back side of the chip; when the conductive connecting block is combined with the front surfaces of the chips at the same time, the conductive connecting block is used for electrically interconnecting the front electrodes positioned on the front surfaces of the different chips; when the connecting parts are combined with the back surfaces of a plurality of chips at the same time, the conductive connecting blocks are used for electrically interconnecting the back electrodes positioned on the back surfaces of different chips; the utility model discloses a parallelly connected packaging device group adopts electrically conductive connecting block to couple together two or more semiconductor devices that should use the PCB circuit to connect, can improve the heat-sinking capability of the upper plate efficiency of a plurality of parallelly connected devices and reinforcing product.
Description
Technical Field
The utility model relates to a power semiconductor encapsulates product technical field, especially relates to a device group of parallelly connected encapsulation.
Background
When a power semiconductor packaging product is manufactured, a plurality of semiconductor devices are often required to be connected in parallel at the same time so as to realize a specific function; in the related art, in order to meet the above requirements, a manufacturing method of individually and sequentially mounting a plurality of semiconductor devices on a PCB is generally used. However, this results in a low efficiency of the upper board (PCB board).
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an aim at: provided is a parallel package device group capable of improving the board mounting efficiency of a semiconductor device.
The embodiment of the utility model provides a another aim at: provided is a parallel package device group capable of improving heat dissipation capability of a semiconductor device.
In order to achieve the purpose, the utility model adopts the following technical proposal:
a group of devices packaged in parallel, comprising:
at least two semiconductor devices, the semiconductor devices including chips;
the conductive connecting block is welded and combined with the front side or the back side of the chip; when the conductive connecting block is combined with the front surfaces of the chips at the same time, the conductive connecting block is used for electrically interconnecting the front electrodes positioned on the front surfaces of the different chips; when the connecting part is combined with the back surfaces of a plurality of chips at the same time, the conductive connecting block is used for electrically interconnecting the back electrodes positioned on the back surfaces of different chips.
Preferably, the conductive connection block is soldered to the front or back surface of the chip by a conductive soldering layer.
Preferably, the conductive connection block comprises a central portion and connection portions, each central portion extends to form at least two connection portions, and the conductive connection block is connected with the front side or the back side of the chip through the connection portions in a welding mode.
Preferably, the connecting portion protrudes in a thickness direction with respect to the central portion, and a portion of the connecting portion protruding with respect to the central portion protrudes into the conductive solder layer.
Preferably, the semiconductor device is a chip packaging structure; the chip packaging structure further comprises a packaging body, a lead frame packaged in the packaging body, a first conductive welding layer and a second conductive welding layer; the lead frame passes through first electrically conductive welding layer with chip welded connection, electrically conductive connecting block passes through second electrically conductive welding layer with chip welded connection.
Preferably, the lead frame is soldered to the back surface of the chip, and a side surface of the lead frame on a side away from the chip is exposed from the package.
Preferably, the conductive connection block is soldered to a side of the lead frame away from the chip, and the conductive connection block is used for electrically interconnecting the back electrodes in the plurality of chips.
Preferably, the wire-type electric connector also comprises a metal wire; the lead frame is provided with a pin, and the pin extends out of the packaging body; the front electrode is interconnected with the pin through the metal wire.
Preferably, the semiconductor device is a chip packaging structure; the chip packaging structure further comprises a packaging body, a lead frame packaged in the packaging body, a first conductive welding layer and a second conductive welding layer; the lead frame is welded on the back surface of the chip through the first conductive welding layer, and the side surface of the lead frame, which is far away from one side of the chip, is exposed out of the packaging body; the front surface of the chip is exposed out of the packaging body;
the conductive connecting block is welded on the front surface of the chip through the second conductive welding layer, and the conductive connecting block is used for interconnecting the front surface electrodes in the plurality of chips.
The utility model has the advantages that: the parallel packaging device group adopts the conductive connecting block to connect two or more semiconductor devices which should be connected by using a PCB circuit, so that the board loading efficiency of a plurality of parallel devices can be improved and the heat dissipation capacity of a product can be enhanced.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Fig. 1 is a schematic cross-sectional view of a device group packaged in parallel according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a device group packaged in parallel according to a second embodiment of the present invention.
In the figure: 10. a semiconductor device; 11. a chip; 12. a package body; 13. a lead frame; 131. a pin; 14. a first conductive solder layer; 15. a second conductive solder layer; 16. a metal wire; 20. a conductive connecting block; 21. a central portion; 22. a connecting portion.
Detailed Description
In order to make the technical problems, technical solutions and technical effects achieved by the present invention more clear, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected" and "fixed" are to be construed broadly, e.g., as meaning fixedly interconnected, detachably interconnected or integral; either mechanically or electrically; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
It is to be noted that "a plurality" is defined herein as two or more than two.
The utility model provides a device group of parallelly connected encapsulation, it adopts electrically conductive connecting block 20 to couple together two or more semiconductor device 10 that should use the PCB circuit to connect, also promptly, electrically conductive connecting block 20 is connected and mechanical connection with a plurality of semiconductor device 10 electricity simultaneously, so, when needing to connect in parallel a plurality of devices in order to realize the function that power semiconductor encapsulation product required simultaneously, can improve the upper plate efficiency of a plurality of devices that need to connect in parallel, and strengthen the heat-sinking capability of whole product.
As shown in fig. 1 and fig. 2, in an embodiment of the parallel packaged device group of the present invention, the parallel packaged device group includes:
at least two semiconductor devices 10, said semiconductor devices 10 comprising chips 11;
a conductive connection block 20 solder-bonded to the front or back of the chips 11, that is, the front of the plurality of chips 11 is electrically connected to the conductive connection block 20, or the back of the plurality of chips 11 is electrically connected to the conductive connection block 20; when the conductive connection block 20 is simultaneously combined with the front surfaces of a plurality of the chips 11, the conductive connection block 20 is used for electrically interconnecting the front electrodes; the conductive connection block 20 serves to electrically interconnect the plurality of back electrodes when the connection portion 22 is simultaneously bonded to the back surfaces of the plurality of chips 11.
It can be understood that, when the device group packaged in parallel is applied, the electric potentials of the electrodes which are electrically interconnected through the conductive connection block 20 are the same, so that the parallel requirement of the plurality of semiconductor devices 10 is realized.
It is also understood that the front electrode and the back electrode may be, but not limited to, electrodes of a diode and electrodes of a triode.
The device group packaged in parallel of the present invention electrically and mechanically connects a plurality of semiconductor devices 10 through the conductive connection block 20; the electrical connection means that the front electrodes on the plurality of chips 11 are electrically interconnected through the conductive connection block 20, or the back electrodes on the plurality of chips 11 are electrically interconnected through the conductive connection block 20, so that the plurality of interconnected electrodes are at the same potential; the mechanical connection means that a plurality of semiconductor devices 10 are fixed on the conductive connection block 20 to form a device group packaged in parallel, so that the plurality of semiconductor devices 10 can be operated simultaneously; therefore, when in application, only a device group which realizes the electrical connection and the mechanical connection of a plurality of devices through the conductive connecting block 20 needs to be directly installed on the PCB at one time, and the efficiency of board installation can be improved while the parallel connection of the plurality of devices is realized; in addition, because the conductive connection block 20 is larger than the metal wire 16 for electrical connection, the contact area with the chip 11 is larger, so the heat dissipation capability of the device group of the present invention is correspondingly improved.
Further, in another embodiment of the parallel packaged device group of the present invention, the front surface of the chip 11 is provided with the front electrode, and the back surface of the chip 11 is provided with the back electrode.
Further, as shown in fig. 1 and fig. 2, in another embodiment of the parallel packaged device group of the present invention, the conductive connection block 20 is soldered to the front or back surface of the chip 11 through a conductive soldering layer.
Specifically, in the present embodiment, the conductive connection block 20 is soldered to the chip 11 through the second conductive soldering layer 15.
Specifically, the conductive welding layer is formed by solidifying a solder, and the solder is an electric and heat conductive adhesive. In some embodiments, the conductive solder layer is a solder paste layer.
Specifically, the conductive connection block 20 and the chip 11 are combined through the conductive welding layer which conducts electricity and heat, so that the heat dissipation capacity of the parallel packaged device group is improved, and the heat dissipation effect is good.
Further, in order to facilitate the soldering connection between the conductive connection block 20 and the chip 11, in this embodiment, the conductive connection block 20 includes a central portion 21 and connection portions 22, each central portion 21 extends to form at least two connection portions 22, and the conductive connection block 20 is soldered to the front or back surface of the chip 11 through the connection portions 22; wherein the central portion 21 serves to connect a plurality of the connecting portions 22, and the size or other structural features of the plurality of connecting portions 22 are configured to match the chip 11.
Further, in order to improve the conductive solder bonding effect between the connection portion 22 and the chip 11, in this embodiment, the connection portion 22 protrudes in the thickness direction relative to the central portion 21, and a protruding portion of the connection portion 22 relative to the central portion 21 protrudes into the conductive solder layer.
Further, as shown in fig. 1 and fig. 2, in another embodiment of the parallel packaged device group of the present invention, the conductive connection block 20 is a graphite-tin composite copper connection block, which is made of graphite-tin composite copper and has better conductive heat dissipation performance.
Further, as shown in fig. 2, in another embodiment of the parallel packaged device group of the present invention, the conductive connection block 20 is used for electrically interconnecting the back electrodes in the plurality of chips 11.
Specifically, the semiconductor device 10 is a chip 11 package structure; the chip 11 packaging structure further comprises a packaging body 12, and a lead frame 13, a first conductive welding layer 14 and a second conductive welding layer 15 which are packaged in the packaging body 12; the lead frame 13 is soldered to the back surface of the chip 11 through the first conductive soldering layer 14, and the side surface of the lead frame 13 away from the chip 11 is exposed out of the package body 12; the conductive connection block 20 is soldered to a side of the lead frame 13 away from the chip 11 by the second conductive soldering layer 15, and the conductive connection block 20 is used for electrically interconnecting the rear electrodes in the plurality of chips 11.
Further, in this embodiment, the parallel packaged device group further includes a metal wire 16; the lead frame 13 has a lead 131, and the lead 131 extends out of the package body 12; the front electrode is interconnected with the pin 131 through the metal wire 16, and the pin 131 is used for being connected with a PCB.
Further, in some embodiments, the back electrode includes a drain, and the conductive connection block 20 is used to electrically interconnect the drains in a plurality of the chips 11, so as to realize parallel connection between the drains in the parallel packaged device group in application.
Further, as shown in fig. 1, in another embodiment of the parallel packaged device group of the present invention, the conductive connection block 20 is used for interconnecting the front electrodes in a plurality of the chips 11.
Specifically, the semiconductor device 10 is a chip 11 package structure; the chip 11 packaging structure further comprises a packaging body 12, and a lead frame 13, a first conductive welding layer 14 and a second conductive welding layer 15 which are packaged in the packaging body 12; the lead frame 13 is soldered to the back surface of the chip 11 through the first conductive soldering layer 14, and the side surface of the lead frame away from the chip 11 is exposed out of the package body 12; the front surface of the chip 11 exposes the package 12; the conductive connection block 20 is soldered to the front surface of the chip 11 through the second conductive solder layer 15, and the conductive connection block 20 is used to interconnect the front electrodes in the plurality of chips 11.
In particular, in some embodiments, the lead frame 13 is used for connection with a PCB board.
It can be understood that the package 12 may be polished to expose the front surface of the chip 11 out of the package 12, so as to facilitate the bonding between the chip 11 and the conductive connection block 20.
Further, in some embodiments, the back electrode includes a source electrode, and the conductive connection block 20 is used to electrically interconnect the source electrodes in a plurality of the chips 11, so as to realize parallel connection between the plurality of source electrodes in the parallel packaged device group during application.
Further, the package body 12 is made of an epoxy resin package material.
In the description herein, it is to be understood that the terms "upper", "lower", "left", "right", and the like are used in a descriptive sense and with reference to the illustrated orientation or positional relationship, and are used for convenience in description and simplicity in operation, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above with reference to specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without any inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A group of devices packaged in parallel, comprising:
at least two semiconductor devices (10), said semiconductor devices (10) comprising chips (11);
a conductive connection block (20) which is solder-bonded to the front surface or the back surface of the chip (11); the conductive connecting block (20) is combined with the front surfaces of a plurality of chips (11) at the same time, and the conductive connecting block (20) is used for electrically interconnecting the front electrodes positioned on the front surfaces of different chips (11); the conductive connection block (20) is used for electrically interconnecting back electrodes on the back surfaces of different chips (11) when the connection portions (22) are simultaneously bonded to the back surfaces of the chips (11).
2. The set of parallel packaged devices according to claim 1, wherein the conductive connection pads (20) are soldered to the front or back side of the chip (11) by a conductive soldering layer.
3. The set of parallel packaged devices according to claim 2, wherein the conductive connection block (20) comprises a central portion (21) and connection portions (22), each central portion (21) extends to provide at least two connection portions (22), and the conductive connection block (20) is connected with the front or back of the chip (11) through the connection portions (22) by soldering.
4. Parallel packaged device group according to claim 3, wherein the connection portion (22) protrudes in the thickness direction with respect to the central portion (21), and the portion of the connection portion (22) protruding with respect to the central portion (21) protrudes into the conductive solder layer.
5. The set of parallel packaged devices of claim 1, wherein the electrically conductive connection block (20) is a graphite tin composite copper connection block.
6. Parallel packaged device group according to any of claims 1 to 5, wherein the semiconductor device (10) is a chip (11) package structure; the chip (11) packaging structure further comprises a packaging body (12), and further comprises a lead frame (13), a first conductive welding layer (14) and a second conductive welding layer (15) which are packaged in the packaging body (12); the lead frame (13) is connected with the chip (11) in a welding mode through the first conductive welding layer (14), and the conductive connecting block (20) is connected with the chip (11) in a welding mode through the second conductive welding layer.
7. The set of parallel packaged devices according to claim 6, wherein the lead frame (13) is soldered to the back surface of the chip (11), and the side surface of the lead frame (13) on the side away from the chip (11) is exposed out of the package body (12).
8. The set of parallel packaged devices according to claim 7, wherein the conductive connection block (20) is soldered to a side of the lead frame (13) remote from the chips (11), the conductive connection block (20) being used for electrically interconnecting the back electrodes within a plurality of the chips (11).
9. The set of parallel packaged devices of claim 8, further comprising a metal wire (16); the lead frame (13) is provided with a pin (131), and the pin (131) extends out of the packaging body (12); the front electrode is interconnected with the pin (131) through the metal wire (16).
10. Parallel packaged device group according to any of claims 1 to 5, wherein the semiconductor device (10) is a chip (11) package structure; the chip (11) packaging structure further comprises a packaging body (12), and further comprises a lead frame (13), a first conductive welding layer (14) and a second conductive welding layer (15) which are packaged in the packaging body (12); the lead frame (13) is welded on the back surface of the chip (11) through the first conductive welding layer (14), and the side surface of the lead frame (13) far away from the chip (11) is exposed out of the packaging body (12); the front surface of the chip (11) is exposed out of the packaging body (12);
the conductive connecting block (20) is welded on the front surface of the chip (11) through the second conductive welding layer (15), and the conductive connecting block (20) is used for interconnecting the front surface electrodes in the plurality of chips (11).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020822370.4U CN212084994U (en) | 2020-05-15 | 2020-05-15 | Parallel packaged device group |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020822370.4U CN212084994U (en) | 2020-05-15 | 2020-05-15 | Parallel packaged device group |
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| CN212084994U true CN212084994U (en) | 2020-12-04 |
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| CN202020822370.4U Active CN212084994U (en) | 2020-05-15 | 2020-05-15 | Parallel packaged device group |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022127060A1 (en) * | 2020-12-15 | 2022-06-23 | 杰群电子科技（东莞）有限公司 | Power device packaging structure and power electronic device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022127060A1 (en) * | 2020-12-15 | 2022-06-23 | 杰群电子科技（东莞）有限公司 | Power device packaging structure and power electronic device |
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