CN218039187U - Packaging structure applied to planar power device - Google Patents

Packaging structure applied to planar power device Download PDF

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Publication number
CN218039187U
CN218039187U CN202221331840.2U CN202221331840U CN218039187U CN 218039187 U CN218039187 U CN 218039187U CN 202221331840 U CN202221331840 U CN 202221331840U CN 218039187 U CN218039187 U CN 218039187U
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China
Prior art keywords
chip
metal
metal frame
layer
heat dissipation
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CN202221331840.2U
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Chinese (zh)
Inventor
张黎
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Zhejiang Hexin Integrated Circuit Co ltd
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Zhejiang Hexin Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model discloses a be applied to planar power device's packaging structure belongs to semiconductor package technical field. The lower chip metal lug on the front surface of the chip is inversely arranged on the etched surface of the three-dimensional metal frame, and the direct interconnection between the chip and the PCB is realized through the turning of the lower chip metal lug and the three-dimensional metal frame, so that the packaging structure is reduced, the traditional routing process is avoided, the packaging resistance is reduced, and the current bearing capacity is improved; meanwhile, the interconnection distance between the chip and the outside is shortened, and the conductive effect of the chip is enhanced; the back of the chip is exposed and directly welded on the PCB for heat dissipation, so that the packaging heat dissipation capacity is improved, the stability of the chip in high-speed operation is improved, and the product quality is improved; in addition, the metal pins of the three-dimensional metal frame are in a concave arc column shape, so that the binding force between the metal pins and the plastic package material is enhanced, and the purpose of increasing the reliability of the product is achieved.

Description

Packaging structure applied to planar power device
Technical Field
The utility model relates to a be applied to planar power device's packaging structure belongs to semiconductor package technical field.
Background
With the development of the 5G industry, the consumer electronics industry and the new energy automobile industry, for example, the power consumption of the 5G base station is increased, the power consumption of the 5G base station is twice that of the 4G base station, in order to reduce the power consumption requirement, the requirements on low loss and high thermal stability of a chip need to be increased, and meanwhile, the requirements on low on-resistance, low heat productivity and quick heat dissipation of a packaging type are also higher.
The traditional wire bonding type packaging adopts a wire bonding packaging form, namely a wire bonding resistor R w Larger, which increases the on-resistance of the entire package and ultimately affects the current carrying capability of the product.
Patent CN106711100A discloses a semiconductor packaging structure and processing method, and its chip (namely vertical MOSFET device) sets up in the front of lead frame, turns over to chip direction through the lead frame, forms the frame hem, leads the drain terminal to with the source electrode through the lead frame the plane that the grid is the same, is convenient for the chip welding on PCB. Once the lead frame is shaped, the size, shape and functional structure of the chip are restricted, which is not beneficial to the continuous development of the industry; meanwhile, the edge of the lead frame is folded, folding stress exists, and in the use process of the chip packaging structure, the released stress is not beneficial to long-term attachment and heat dissipation of the chip and the lead frame, so that the reliability of the product is reduced.
Disclosure of Invention
In order to overcome the deficiency of the prior art, the utility model provides a be applied to planar power device's packaging structure for the chip that adopts this kind of packaging method realizes low on resistance, bears heavy current, heat dispersion excellence, and packaging structure is simple.
The technical scheme of the utility model:
the utility model provides a packaging structure applied to a plane type power device, which comprises a chip, a heat dissipation layer, a three-dimensional metal frame and a plastic packaging material,
the front surface of the chip is provided with a plurality of under-chip metal bumps, one ends of the under-chip metal bumps are connected with electrodes of the chip, and the other ends of the under-chip metal bumps are provided with welding layers to form I/O ends of the chip;
the heat dissipation layer is arranged on the back of the chip, the three-dimensional metal frame comprises a plurality of metal frame support bars and metal pins, the metal frame support bars are equal in length and are arranged on the same plane in parallel at equal intervals, the back of the metal frame support bars is an etching surface, and the metal pins are arranged at two ends of the etching surface of each metal frame support bar;
the etched surface of the metal frame supporting strip and the inner side of the metal pin form a cavity;
the front surface of the chip is reversely arranged in the cavity, and the metal lug under the chip is fixedly connected with the etching surface of the metal frame support strip through the welding layer and is electrically connected with the three-dimensional metal frame; the front surface of the three-dimensional metal frame is provided with a protective film with gum,
the plastic package material is integrally filled and plastically packaged in gaps among the three-dimensional metal frame, the chip and the metal frame supporting bars, and the gaps among the metal frame supporting bars form a flow guide channel of the plastic package material and only expose the outer surface of the heat dissipation layer and the upper surfaces of the metal pins;
the upper surface of the metal pin is provided with a conductive metal layer I, and the outer surface of the heat dissipation layer is provided with a conductive metal layer III.
Be applied to planar power device's packaging structure the etching face of metal frame support bar can be the rough surface.
Be applied to planar power device's packaging structure metal pin is concave arc column, its cross section can be circular, rectangle or hexagon.
Be applied to planar power device's packaging structure the cylinder of metal pin is the mat surface, roughness Ra scope is: ra is 0.2 to 0.4.
Be applied to planar power device's packaging structure metal pin and three-dimensional metal frame structure as an organic whole.
Be applied to planar power device's packaging structure the cross sectional dimension on heat dissipation layer be not less than the cross sectional dimension of chip.
Be applied to planar power device's packaging structure the welding layer be Cu/Sn layer or Ni/Au layer.
Advantageous effects
The utility model relates to a packaging structure for planar power device adopts the positive under-chip metal lug of chip to flip-chip to the etched surface of three-dimensional metal frame, realizes chip and PCB direct interconnection through the inflection of under-chip metal lug, three-dimensional metal frame, has reduced packaging structure, has avoided traditional routing technology, has reduced encapsulation resistance, has increased the electric current bearing capacity; meanwhile, the interconnection distance between the chip and the outside is shortened, and the conductive effect of the chip is enhanced; the back of the chip is exposed and directly welded on the PCB for heat dissipation, so that the packaging heat dissipation capacity is improved, the stability of the chip in high-speed operation is improved, and the product quality is improved; in addition, the metal pins of the three-dimensional metal frame are in a concave arc column shape, so that the binding force between the metal pins and the plastic package material is enhanced, and the purpose of increasing the reliability of the product is achieved.
Drawings
Fig. 1 is a schematic diagram of a cross-sectional structure of a package structure applied to a planar power device according to the present invention;
fig. 2 is a schematic diagram illustrating a cross-sectional structure of an embodiment of a package structure applied to a planar power device according to the present invention;
FIG. 3 is a schematic diagram of the relative positions of the chip and the three-dimensional metal frame in FIG. 1;
fig. 4 is a schematic diagram of an embodiment of a cross-sectional structure of a package structure applied to a planar power device according to the present invention;
wherein: chip 10
Under-chip metal bump 11
Solder layer 12
Metal frame support bar 21
Metal pin 22
Mold cavity 26
Heat dissipation layer 30
Conductive metal layer I61
Conductive metal layer III 63
And a plastic molding material 90.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The utility model relates to a be applied to planar power device's packaging structure, as shown in fig. 1 to fig. 4, metal lug 11 under its chip 10's the front is equipped with a plurality of chip, the back is equipped with heat dissipation layer 30. One end of the under-chip metal bump 11 is connected to an electrode (the electrode is not shown in the figure) of the chip 10, and the electrode of the chip 10 is buried in the silicon substrate under the passivation layer on the surface of the chip; the other end of the under-chip metal bump 11 is provided with a solder layer 12 to become an I/O terminal of the chip 10, and the solder used for the solder layer 12 may be one or a combination of titanium, copper, silver, nickel, gold, tin, and tin-silver.
The cross sectional dimension of heat dissipation layer 30 is not less than the cross sectional dimension of chip 10, and the excellent metal copper of electric conductive property is preferred to its material, and heat dissipation layer 30 sets up at the back of chip 10, directly welds chip 10 to PCB through heat dissipation layer 30 and carries out the heat dissipation, has promoted the encapsulation heat-sinking capability, has promoted the quality of product, has realized the excellent heat dispersion of encapsulation product.
The three-dimensional metal frame 20 comprises a plurality of metal frame support bars 21 and metal pins 22, the back surfaces of the metal frame support bars 21 are etched surfaces, and the metal pins 22 are arranged at two ends of the etched surface of each metal frame support bar 21.
Generally, the metal frame support bars 21 are equal in length and are arranged in parallel and equidistant in the same plane with a gap therebetween. The cross section of the metal pin 22 is circular, rectangular, hexagonal, etc., and the cross section of the metal pin 22 is illustrated as rectangular in fig. 3. The etched surface of the metal frame support bar 21 and the inner side of the metal lead 22 form a cavity 26. The etched surface of the metal frame support bars 21 is rough, which helps to provide a strong connection between the three-dimensional metal frame 20 and the metal leads 22 and the vertical MOSFET chip 10.
The front surface of the chip 10 is inversely installed in the cavity 26, and the metal bump 11 under the chip is fixedly connected with the etched surface of the metal frame support bar 21 through the welding layer 12 and is electrically connected with the three-dimensional metal frame 20. The roughness of the etched surface of the metal frame support bar 21 contributes to the connection strength with the chip 10.
The direct electrical interconnection of the chip 10 and the PCB is realized through the turning of the metal lug 11 under the chip and the three-dimensional metal frame 20, the chip 10 is efficiently radiated through the PCB, the interconnection distance between the chip 10 and the outside is shortened, the conductive effect of the chip is enhanced, the traditional routing mode is avoided, and the resistance R between the drain electrode of the chip and the lead frame is reduced D The resistance R of the bonding wire is reduced W Thereby achieving the purpose of reducing the on resistance RDS (on) of the packaged product.
The front surface of the three-dimensional metal frame 20 is a flat exposed surface, and a protective film 40 with a back adhesive, such as an advll LC tape, is disposed thereon. The protective film 40 has uniform thickness, is attached to the front surface of the three-dimensional metal frame 20 through a laminating process, can be carried out at relatively low temperature, and is convenient to install, so that the risk of damaging a circuit due to heat is reduced. It can protect the chip from external solvents, moisture, shock, etc., while electrically insulating the chip from the external environment. It also blocks light, minimizing the effect of light on the circuit surface.
The plastic package material 90 is integrally filled and plastically packaged in gaps between the three-dimensional metal frame 20 and the chip 10 and between the three-dimensional metal frame 21 and the metal frame support bars 21, the gaps between the metal frame support bars 21 form flow guide channels of the plastic package material 90, only the outer surface of the heat dissipation layer 30 and the upper surfaces 223 of the metal pins are exposed, the plastic package material 90 arranged between the chip 10 and the heat dissipation layer 30 and between the chip and the metal pins 22 can effectively prevent short circuit caused by voltage breakdown, and reliability of products is improved.
In an alternative embodiment, the metal pins 22 and the three-dimensional metal frame 20 are in an integral structure, the metal pins 22 are in a concave arc column shape, and the radian R thereof is generated due to the difference of etching rates in the half-etching process of the three-dimensional metal frame 20, as shown in fig. 2, the actually required radian R is obtained by controlling the half-etching process. The concave arc shape of the metal pin 22 can also increase the bonding force between the metal pin 22 and the plastic package material 90, so as to achieve the purpose of increasing the reliability of the product.
In an alternative embodiment, the cylindrical surface of the metal pin 22 may also be a rough surface, and the roughness Ra ranges from: ra is 0.2 to 0.4, and the bonding force between the metal pins 22 and the plastic package material 90 can be increased, so that the purpose of increasing the reliability of the product is achieved.
In an alternative embodiment, the plastic sealing material 90 may be exposed at both sides of the metal frame body 21, as shown in fig. 4.
In an optional embodiment, the present invention further includes a conductive metal layer i 61 disposed on the upper surface 223 of the metal pin and a conductive metal layer iii 63 disposed on the outer surface of the heat dissipation layer 30, wherein the conductive metal layer i 61 and the conductive metal layer iii 63 are used for subsequent mounting of the packaged chip, so as to facilitate electrical connection and heat dissipation with other external devices.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the embodiments of the present invention are all covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (8)

1. A packaging structure applied to a planar power device comprises a chip (10), a heat dissipation layer (30), a three-dimensional metal frame (20) and a plastic packaging material (90),
the front surface of the chip (10) is provided with a plurality of under-chip metal bumps (11), one ends of the under-chip metal bumps (11) are connected with electrodes of the chip (10), and the other ends are provided with welding layers (12) to form I/O ends of the chip (10);
the heat dissipation layer (30) is arranged on the back of the chip (10), the three-dimensional metal frame (20) comprises a plurality of metal frame support bars (21) and metal pins (22), the metal frame support bars (21) are equal in length and are arranged on the same plane in parallel at equal intervals, the back of the metal frame support bars is an etching surface, and the metal pins (22) are arranged at two ends of the etching surface of each metal frame support bar (21);
the etching surface of the metal frame support bar (21) and the inner side of the metal pin (22) form a cavity (26);
the front surface of the chip (10) is arranged in the cavity (26) in an inverted mode, and the metal lug (11) under the chip is fixedly connected with the etching surface of the metal frame supporting strip (21) through the welding layer (12) and is electrically connected with the three-dimensional metal frame (20); the front surface of the three-dimensional metal frame (20) is provided with a protective film (40) with gum,
the plastic package material (90) is integrally filled and plastically packaged in gaps among the three-dimensional metal frame (20), the chip (10) and the metal frame supporting bars (21), flow guide channels of the plastic package material (90) are formed in the gaps among the metal frame supporting bars (21), and only the outer surface of the heat dissipation layer (30) and the upper surfaces (223) of the metal pins are exposed;
the upper surface (223) of metal pin sets up electrically conductive metal layer I (61), the surface of heat dissipation layer (30) sets up electrically conductive metal layer III (63).
2. The package structure according to claim 1, wherein the etched surface of the metal frame support bar (21) is a rough surface.
3. The package structure according to claim 1, wherein the metal leads (22) have a circular, rectangular or hexagonal cross-section.
4. The package structure of claim 1, wherein the metal leads (22) are in the shape of a concave arc column.
5. The package structure according to claim 1, wherein the cylindrical surface of the metal lead (22) is a rough surface, and the roughness Ra ranges from: ra is 0.2 to 0.4.
6. The package structure according to any one of claims 1 to 5, wherein the metal leads (22) are of a unitary structure with the three-dimensional metal frame (20).
7. The package structure according to claim 1, wherein a cross-sectional dimension of the heat dissipation layer (30) is not smaller than a cross-sectional dimension of the chip (10).
8. The package structure according to claim 1, characterized in that the soldering layer (12) is a Cu/Sn layer or a Ni/Au layer.
CN202221331840.2U 2022-05-31 2022-05-31 Packaging structure applied to planar power device Active CN218039187U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202221331840.2U CN218039187U (en) 2022-05-31 2022-05-31 Packaging structure applied to planar power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202221331840.2U CN218039187U (en) 2022-05-31 2022-05-31 Packaging structure applied to planar power device

Publications (1)

Publication Number Publication Date
CN218039187U true CN218039187U (en) 2022-12-13

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CN202221331840.2U Active CN218039187U (en) 2022-05-31 2022-05-31 Packaging structure applied to planar power device

Country Status (1)

Country Link
CN (1) CN218039187U (en)

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