CN102842548A - Square flat-type power metal oxide semi-conductor (MOS) chip packaging structure - Google Patents

Square flat-type power metal oxide semi-conductor (MOS) chip packaging structure Download PDF

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Publication number
CN102842548A
CN102842548A CN2012103020953A CN201210302095A CN102842548A CN 102842548 A CN102842548 A CN 102842548A CN 2012103020953 A CN2012103020953 A CN 2012103020953A CN 201210302095 A CN201210302095 A CN 201210302095A CN 102842548 A CN102842548 A CN 102842548A
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China
Prior art keywords
welding disk
chip
conductive welding
area
mosfet chip
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CN2012103020953A
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Chinese (zh)
Inventor
胡乃仁
杨小平
李国发
钟利强
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Suzhou Good Ark Electronics Co Ltd
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Suzhou Good Ark Electronics Co Ltd
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Priority to CN2012103020953A priority Critical patent/CN102842548A/en
Publication of CN102842548A publication Critical patent/CN102842548A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a square flat-type power metal oxide semi-conductor (MOS) chip packaging structure. An electricity-conducting base plate of the chip packaging structure comprises a heat-dissipation area and a base plate lead foot area. The base plate lead foot area comprises a plurality of drain electrode lead feet which are arranged at intervals. One end of each drain electrode lead foot is electrically connected with the end face of the heat-dissipation area. The heat-dissipation area is arranged under a metal-oxide-semiconductor field-effect transistor (MOSFET) chip and electrically connected with the lower surface of the MOSFET chip through an electricity-conducting welding material layer. A first electricity-conducting welding plate and a second electricity-conducting welding plate are arranged on the other side of the MOSFET chip. The first electricity-conducting welding plate and the second electricity-conducting welding plate respectively comprise a welding area and a lead foot area. The connecting portion between each welding area and each lead foot area is provided with a first bending part. An aluminum conductor belt is connected between field effect transistor of the MOSFET chip and the welding area of the first electricity-conducting welding plate in a crossing mode. The number of welding strips of the aluminum conductor belt and the field effect transistor of the MOSFET chip is at least two. The welding strips are arranged at intervals. The square flat-type power MOS chip packaging structure reduces ohm contacting resistance, improves indexes of electrical performance, and reduces heat production.

Description

Quad flat type power mos chip encapsulating structure
Technical field
The present invention relates to MOS chip technology field, be specifically related to the capable type power mos chip of a kind of quad flat encapsulating structure.
Background technology
Along with the fast development of electronic manufacturing technology, consumption electronic product is more and more to small-sized, portable trend development, and this space that has also caused the inside of these electronic products to can be used in the layout electricity component becomes more and more limited.In the case, the electricity component of employing certainly will be got over Bao Yuehao, and this also becomes present electronic component manufacturing development trend also.Square flat non-pin encapsulation (DFN) technology can satisfy this demand just.
Prior art is a kind of generalized section of typical DFN encapsulating structure shown in accompanying drawing 1, comprises chip 900, fin 920, lead frame 930, a plurality of lead 940, and the insulating cement 950 of parcel said structure.Chip 900 sticks on the fin 920, and lead frame 930 has the pin of a plurality of mutually insulateds, and the pad on chip 900 surfaces is connected lead frame 93 through lead 940.On the corresponding pin.Insulating cement 950 all wraps up said structure, and so that it is isolated with extraneous, only each pin with lead frame 930 is exposed in the air with fin 920 and chip 900 facing surfaces.The pin that lead frame 930 comes out is used to realize that packed chip 900 connects with extraneous electricity, and the heat that the effect that fin 920 comes out produces when being chip 900 work is dispersed in the environment through the surface that exposes and goes.
Summary of the invention
The object of the invention provides a kind of quad flat type power mos chip encapsulating structure, and this power mos chip encapsulating structure helps reducing ohmic contact resistance, has improved electrical performance indexes, also reduces the generation of heat simultaneously.
For achieving the above object; The technical scheme that the present invention adopts is: a kind of quad flat type power mos chip encapsulating structure, comprise MOSFET chip, epoxy resin layer, and said MOSFET chip upper surface is provided with source electrode and grid; Lower surface is provided with drain electrode; Also comprise conduction basal disc, first conductive welding disk and second conductive welding disk, said conduction basal disc is made up of radiating area and basal disc pin area, and this basal disc pin area is made up of several drain lead alternately; This drain lead one end is electrically connected with the radiating area end face, said radiating area under the MOSFET chip and with MOSFET chip lower surface between be electrically connected through the conductive solder layer; Said first conductive welding disk and second conductive welding disk are positioned at MOSFET chip opposite side, and first conductive welding disk and second conductive welding disk include weld zone and pin area, and the junction of weld zone and pin area has a bending part, thereby makes the weld zone be higher than pin area; One aluminium conductor band cross-over connection is between the weld zone of the source electrode of said MOSFET chip and first conductive welding disk, and the welding bar of the source electrode of said aluminium conductor band and MOSFET chip is at least 2 and alternately; One metal wire cross-over connection is between the weld zone of the grid of said MOSFET chip and second conductive welding disk.
Further improved plan is following in the technique scheme:
1, in the such scheme, said first conductive welding disk and second conductive welding disk weld zone and MOSFET chip separately is positioned at same horizontal plane.
2, in the such scheme, said aluminium conductor bandwidth thickness rate is 1:10 15.
3, in the such scheme, the arrangement mode of said at least 2 welding bars is for laterally arranging.
4, in the such scheme, the pin area of said first conductive welding disk is by at least four root utmost point pin set
Become.
5, in the such scheme, the pin area of said second conductive welding disk is made up of a gate lead.
6, in the such scheme, the number of said drain lead is four.
Because the technique scheme utilization, the present invention compared with prior art has advantage and effect:
1, conducts electricity basal disc in the packaging body of the present invention; It has had both conductive welding disk in the prior art, three component functions of fin and basic island simultaneously; The volume that had both helped further reduction of device; Also reduce the number of parts in the device, because radiating area and basal disc pin area are as a whole, improved the stability of electrical property simultaneously.
2, the junction of weld zone and pin area has a bending part in the packaging body of the present invention; Thereby make the weld zone be higher than pin area; And the grid of weld zone and MOSFET chip that has guaranteed first, second conductive welding disk is at same horizontal plane; Thereby effectively avoided owing to the thin technological deficiency of in use breaking easily of second metal wire that connects grid, thereby prolonged the useful life of product and improved reliability.
3, this basal disc pin area of the present invention is made up of several drain lead alternately; The pin area of first conductive welding disk is made up of at least four root utmost point pins; Fully take into account the big difference of the MOSFET chip relative grid current of drain electrode with source electrode; Thereby help reducing the generation of heat, and further improved electrical performance indexes.
4, cross-over connection has the aluminium conductor band between the weld zone of the source electrode of MOSFET chip according to the invention and first conductive welding disk; And the welding bar of the source electrode of said aluminium conductor band and MOSFET chip is at least 2 and alternately; Thereby this structural design helps reducing ohmic contact resistance; Improve electrical performance indexes, also reduced the generation of heat simultaneously.
Description of drawings
Fig. 1 is the prior art structural representation;
Fig. 2 is a power MOSFET package body structure sketch map of the present invention;
Fig. 3 is along the cutaway view of A-A line in the accompanying drawing 2.
In the above accompanying drawing: 1, MOSFET chip; 2, epoxy resin layer; 3, conduction basal disc; 31, radiating area; 32, basal disc pin area; 321, drain lead; 4, first conductive welding disk; 5, second conductive welding disk; 6, conductive solder layer; 7, weld zone; 8, pin area; 9, bending part; 10, aluminium conductor band; 11, metal wire; 12, welding bar.
Embodiment
Below in conjunction with embodiment the present invention is further described:
Embodiment 1: a kind of quad flat type power mos chip encapsulating structure; Comprise MOSFET chip 1, epoxy resin layer 2; Said MOSFET chip upper surface 1 is provided with source electrode and grid, and lower surface is provided with drain electrode, also comprises conduction basal disc 3, first conductive welding disk 4 and second conductive welding disk 5; Said conduction basal disc 3 is made up of radiating area 31 and basal disc pin area 32; This basal disc pin area 32 is made up of several drain lead 321 alternately, and these drain lead 321 1 ends are electrically connected with radiating area 31 end faces, said radiating area 31 under the MOSFET chip 1 and with MOSFET chip 1 lower surface between be electrically connected through conductive solder layer 6; Said first conductive welding disk 4 and second conductive welding disk 5 are positioned at MOSFET chip 1 opposite side; First conductive welding disk 4 and second conductive welding disk 5 include weld zone 7 and pin area 8; Weld zone 7 has a bending part 9 with the junction of pin area 8, thereby makes weld zone 7 be higher than pin area 8; 10 cross-over connections of one aluminium conductor band are between the weld zone 7 of the source electrode of said MOSFET chip 1 and first conductive welding disk 4, and the welding bar 12 of said aluminium conductor band 10 and the source electrode of MOSFET chip 1 is at least 2 and alternately; 11 cross-over connections of one metal wire are between the weld zone 7 of the grid of said MOSFET chip 1 and second conductive welding disk 5.
Above-mentioned first conductive welding disk 4 and second conductive welding disk 5 weld zone 7 separately is positioned at same horizontal plane with the MOSFET chip.
The pin area of above-mentioned first conductive welding disk 4 is made up of at least four root utmost point pins.
The number of above-mentioned drain lead 321 is four.
Embodiment 2: a kind of quad flat type power mos chip encapsulating structure; Comprise MOSFET chip 1, epoxy resin layer 2; Said MOSFET chip upper surface 1 is provided with source electrode and grid, and lower surface is provided with drain electrode, also comprises conduction basal disc 3, first conductive welding disk 4 and second conductive welding disk 5; Said conduction basal disc 3 is made up of radiating area 31 and basal disc pin area 32; This basal disc pin area 32 is made up of several drain lead 321 alternately, and these drain lead 321 1 ends are electrically connected with radiating area 31 end faces, said radiating area 31 under the MOSFET chip 1 and with MOSFET chip 1 lower surface between be electrically connected through conductive solder layer 6; Said first conductive welding disk 4 and second conductive welding disk 5 are positioned at MOSFET chip 1 opposite side; First conductive welding disk 4 and second conductive welding disk 5 include weld zone 7 and pin area 8; Weld zone 7 has a bending part 9 with the junction of pin area 8, thereby makes weld zone 7 be higher than pin area 8; 10 cross-over connections of one aluminium conductor band are between the weld zone 7 of the source electrode of said MOSFET chip 1 and first conductive welding disk 4, and the welding bar 12 of said aluminium conductor band 10 and the source electrode of MOSFET chip 1 is at least 2 and alternately; 11 cross-over connections of one metal wire are between the weld zone 7 of the grid of said MOSFET chip 1 and second conductive welding disk 5.
Above-mentioned aluminium conductor band 10 flakiness ratios are 1:10 15.
The arrangement mode of above-mentioned at least 2 welding bars 12 is for laterally arranging.
The pin area of above-mentioned second conductive welding disk 5 is made up of a gate lead.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.

Claims (7)

1. quad flat type power mos chip encapsulating structure; Comprise MOSFET chip (1), epoxy resin layer (2); Said MOSFET chip upper surface (1) is provided with source electrode and grid; Lower surface is provided with drain electrode; It is characterized in that: also comprise conduction basal disc (3), first conductive welding disk (4) and second conductive welding disk (5), said conduction basal disc (3) is made up of radiating area (31) and basal disc pin area (32), and this basal disc pin area (32) is made up of several drain lead (321) alternately; These drain lead (321) one ends are electrically connected with radiating area (31) end face, said radiating area (31) be positioned under the MOSFET chip (1) and with MOSFET chip (1) lower surface between be electrically connected through conductive solder layer (6); Said first conductive welding disk (4) and second conductive welding disk (5) are positioned at MOSFET chip (1) opposite side; First conductive welding disk (4) and second conductive welding disk (5) include weld zone (7) and pin area (8); Weld zone (7) has a bending part (9) with the junction of pin area (8), thereby makes weld zone (7) be higher than pin area (8); One aluminium conductor band (10) cross-over connection is between the weld zone (7) of the source electrode of said MOSFET chip (1) and first conductive welding disk (4), and the welding bar (12) of said aluminium conductor band (10) and the source electrode of MOSFET chip (1) is at least 2 and alternately; One metal wire (11) cross-over connection is between the weld zone (7) of the grid of said MOSFET chip (1) and second conductive welding disk (5).
2. power mos chip encapsulating structure according to claim 1 is characterized in that: said first conductive welding disk (4) and second conductive welding disk (5) weld zone (7) separately is positioned at same horizontal plane with the MOSFET chip.
3. power mos chip encapsulating structure according to claim 1 is characterized in that: said aluminium conductor band (10) flakiness ratio is 1:10 15.
4. power mos chip encapsulating structure according to claim 1 is characterized in that: the arrangement mode of said at least 2 welding bars (12) is for laterally arranging.
5. power mos chip encapsulating structure according to claim 1 is characterized in that: the pin area of said first conductive welding disk (4) is made up of at least four root utmost point pins.
6. power mos chip encapsulating structure according to claim 1 is characterized in that: the pin area of said second conductive welding disk (5) is made up of a gate lead.
7. power mos chip encapsulating structure according to claim 1 is characterized in that: the number of said drain lead (321) is four.
CN2012103020953A 2012-08-23 2012-08-23 Square flat-type power metal oxide semi-conductor (MOS) chip packaging structure Pending CN102842548A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108461995A (en) * 2018-03-22 2018-08-28 无锡工赢智能科技有限公司 High current power MOS packaging systems
CN114190009A (en) * 2021-11-19 2022-03-15 气派科技股份有限公司 Surface-mounted device packaging structure and upper plate welding method thereof

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Publication number Priority date Publication date Assignee Title
US20040063240A1 (en) * 2002-09-30 2004-04-01 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US20060237814A1 (en) * 2005-03-09 2006-10-26 Khalil Hosseini Semiconductor device having surface mountable external contact areas and method for producing the same
US20110272794A1 (en) * 2007-01-24 2011-11-10 Erwin Victor Cruz Pre-molded clip structure

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20040063240A1 (en) * 2002-09-30 2004-04-01 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US20060237814A1 (en) * 2005-03-09 2006-10-26 Khalil Hosseini Semiconductor device having surface mountable external contact areas and method for producing the same
US20110272794A1 (en) * 2007-01-24 2011-11-10 Erwin Victor Cruz Pre-molded clip structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108461995A (en) * 2018-03-22 2018-08-28 无锡工赢智能科技有限公司 High current power MOS packaging systems
CN108461995B (en) * 2018-03-22 2023-09-26 无锡工赢智能科技有限公司 High-current power MOS packaging device
CN114190009A (en) * 2021-11-19 2022-03-15 气派科技股份有限公司 Surface-mounted device packaging structure and upper plate welding method thereof

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