CN102842550A - Dual flat package (DFN) structure of power metal-oxide-semiconductor field effect transistor (MOSFE) chip - Google Patents

Dual flat package (DFN) structure of power metal-oxide-semiconductor field effect transistor (MOSFE) chip Download PDF

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Publication number
CN102842550A
CN102842550A CN2012103024263A CN201210302426A CN102842550A CN 102842550 A CN102842550 A CN 102842550A CN 2012103024263 A CN2012103024263 A CN 2012103024263A CN 201210302426 A CN201210302426 A CN 201210302426A CN 102842550 A CN102842550 A CN 102842550A
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China
Prior art keywords
welding disk
conductive welding
chip
mosfet chip
mosfe
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CN2012103024263A
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Chinese (zh)
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CN102842550B (en
Inventor
胡乃仁
杨小平
李国发
钟利强
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Suzhou Good Ark Electronics Co Ltd
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Suzhou Good Ark Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

The invention discloses a dual flat package (DFN) structure of a power metal-oxide-semiconductor field effect transistor (MOSFE) chip. The DFN structure of the power MOSFE chip comprises an electric conduction base, a first electric conduction pad and a second electric conduction pad, wherein the electric conduction base is composed of a heat dissipation area and a base pin area, and the base pin area is composed of a plurality of drain pins which are arranged at intervals. One ends of the drain pins are in electric connection with the end face of the heat dissipation area, and the heat dissipation area is arranged directly below an MOSFE chip and in electric connection with the lower surface of the MOSFE chip through a soft solder layer. The first electric conduction pad and the second electric conduction pad are placed on the other side of the MOSFE chip and provided with solder zones and pin zones, and bend portions are arranged on connection portions of the solder zones and the pin zones. Quality percentage content of the soft solder layer is lead 92.5%, tin 5% and silver 2.5%. The DFN structure of the power MOSFE chip is beneficial to reducing the size of devices and the number of components inside a package body. In addition, the DFN structure of the power MOSFE chip can improve heat dissipation efficiency of a device MOSFE chip. Thermal resistance is reduced by 75% compared with the prior art.

Description

The DFN encapsulating structure of power mosfet chip
Technical field
The present invention relates to MOSFET chip technology field, be specifically related to a kind of DFN encapsulating structure of power mosfet chip.
Background technology
Along with the development of electronic product, for example consumer electronics products such as notebook computer, mobile phone, mini CD, palmtop PC, CPU, digital camera more and more develop to miniaturization.For a short time do thinly along with doing of product, how the heat that millions of transistors produced among the worker IC distributes must not irrespective problem with regard to becoming one.In the prior art,, still can not avoid the trend of heat generation density increase though can reduce mode such as voltage and reduce caloric value through promoting worker IC processing procedure ability.Heat dissipation problem does not solve, and can make multiplexer spare because of the overheated reliability of products that has influence on, and seriously can shorten life of product even cause the product damage.
Prior art is a kind of generalized section of typical DFN encapsulating structure shown in accompanying drawing 1, comprises chip 900, fin 920, lead frame 930, a plurality of lead 940, and the insulating cement 950 of parcel said structure.Chip 900 sticks on the fin 920, and lead frame 930 has the pin of a plurality of mutually insulateds, and the pad on chip 900 surfaces is connected lead frame 93 through lead 940.On the corresponding pin.Insulating cement 950 all wraps up said structure, and so that it is isolated with extraneous, only each pin with lead frame 930 is exposed in the air with fin 920 and chip 900 facing surfaces.The pin that lead frame 930 comes out is used to realize that packed chip 900 connects with extraneous electricity, and the heat that the effect that fin 920 comes out produces when being chip 900 work is dispersed into through the surface that exposes and goes in the environment; Accompanying drawing two is another kind of typical encapsulating structure, and it is similarly pin and separates with fin, and pin exposes, and still exists volume to be unfavorable for the technical problem of dispelling the heat greatly.
Summary of the invention
The object of the invention provides a kind of DFN encapsulating structure of power mosfet chip, and this DFN encapsulating structure helps the volume of further reduction of device, reduces the number of parts in the packaging body simultaneously; And boost device MOSFET chip cooling efficient, thermal resistance are compared prior art and are reduced by 75%.
For achieving the above object, the technical scheme that the present invention adopts is: a kind of DFN encapsulating structure of power mosfet chip, comprise MOSFET chip, epoxy resin layer, and said MOSFET chip upper surface is provided with source electrode and grid, and lower surface is provided with drain electrode; Also comprise conduction basal disc, first conductive welding disk and second conductive welding disk; Said conduction basal disc is made up of radiating area and basal disc pin area; This basal disc pin area is made up of several drain lead alternately; This drain lead one end is electrically connected with the radiating area end face, said radiating area under the MOSFET chip and with MOSFET chip lower surface between be electrically connected through the soft soldering bed of material; Said first conductive welding disk and second conductive welding disk are positioned at MOSFET chip opposite side, and first conductive welding disk and second conductive welding disk include weld zone and pin area, and the junction of weld zone and pin area has a bending part, thereby makes the weld zone be higher than pin area; Some first metal wire cross-over connections are between the weld zone of the source electrode of said MOSFET chip and first conductive welding disk, and the second metal wire cross-over connection is between the weld zone of the grid of said MOSFET chip and second conductive welding disk; The said soft soldering bed of material is made up of the component of following quality percentage composition: lead 92.5%, tin 5%, silver 2.5%.
Further improved plan is following in the technique scheme:
1, in the such scheme, said first conductive welding disk and second conductive welding disk weld zone and MOSFET chip separately is positioned at same horizontal plane.
2, in the such scheme, the number of said first metal wire is at least four.
3, in the such scheme, the pin area of said first conductive welding disk is made up of at least four root utmost point pins.
4, in the such scheme, the pin area of said second conductive welding disk is made up of a gate lead.
5, in the such scheme, the number of said drain lead is four.
Because the technique scheme utilization, the present invention compared with prior art has advantage and effect:
1, conducts electricity basal disc in the DFN encapsulating structure of the present invention; It has had both conductive welding disk in the prior art, three component functions of fin and basic island simultaneously; The volume that had both helped further reduction of device; Also reduce the number of parts in the device, because radiating area and basal disc pin area are as a whole, improved the stability of electrical property simultaneously.
2, conduct electricity basal disc in the DFN encapsulating structure of the present invention; It has had both conductive welding disk in the prior art, three component functions of fin and basic island simultaneously; Said radiating area under the MOSFET chip and with MOSFET chip lower surface between be electrically connected and the said soft soldering bed of material is made up of the component of following quality percentage composition through the soft soldering bed of material: plumbous 92.5%; Tin 5%, silver 2.5% has further improved the heat dispersion of conduction basal disc.
3, the junction of weld zone and pin area has a bending part in the DFN encapsulating structure of the present invention; Thereby make the weld zone be higher than pin area; And the grid of weld zone and MOSFET chip that has guaranteed first, second conductive welding disk is at same horizontal plane; Thereby effectively avoided owing to the thin technological deficiency of in use breaking easily of second metal wire that connects grid, thereby prolonged the useful life of product and improved reliability.
4, the basal disc pin area is made up of several drain lead alternately in the DFN encapsulating structure of the present invention; The pin area of first conductive welding disk is made up of at least four root utmost point pins; Fully take into account the big difference of the MOSFET chip relative grid current of drain electrode with source electrode; Thereby help reducing the generation of heat, and further improved electrical performance indexes.
Description of drawings
Fig. 1 is a prior art structural representation one;
Fig. 2 is a prior art structural representation two;
Fig. 3 is the DFN encapsulating structure sketch map of power mosfet chip of the present invention;
Fig. 4 is along the cutaway view of A-A line in the accompanying drawing 3.
In the above accompanying drawing: 1, MOSFET chip; 2, epoxy resin layer; 3, conduction basal disc; 31, radiating area; 32, basal disc pin area; 321, drain lead; 4, first conductive welding disk; 5, second conductive welding disk; 6, the soft soldering bed of material; 7, weld zone; 8, pin area; 9, bending part; 10, first metal wire; 11, second metal wire.
Embodiment
Below in conjunction with embodiment the present invention is further described:
Embodiment 1: a kind of DFN encapsulating structure of power mosfet chip; Comprise MOSFET chip 1, epoxy resin layer 2; Said MOSFET chip upper surface 1 is provided with source electrode and grid, and lower surface is provided with drain electrode, also comprises conduction basal disc 3, first conductive welding disk 4 and second conductive welding disk 5; Said conduction basal disc 3 is made up of radiating area 31 and basal disc pin area 32; This basal disc pin area 32 is made up of several drain lead 321 alternately, and these drain lead 321 1 ends are electrically connected with radiating area 31 end faces, said radiating area 31 under the MOSFET chip 1 and with MOSFET chip 1 lower surface between be electrically connected through the soft soldering bed of material 6; Said first conductive welding disk 4 and second conductive welding disk 5 are positioned at MOSFET chip 1 opposite side; First conductive welding disk 4 and second conductive welding disk 5 include weld zone 7 and pin area 8; Weld zone 7 has a bending part 9 with the junction of pin area 8, thereby makes weld zone 7 be higher than pin area 8; Some first metal wire 10 cross-over connections are between the weld zone 7 of the source electrode of said MOSFET chip 1 and first conductive welding disk 4, and 11 cross-over connections of second metal wire are between the weld zone 7 of the grid of said MOSFET chip 1 and second conductive welding disk 5; The said soft soldering bed of material 6 is made up of the component of following quality percentage composition: lead 92.5%, tin 5%, silver 2.5%.
Above-mentioned first conductive welding disk 4 and second conductive welding disk 5 weld zone 7 separately is positioned at same horizontal plane with the MOSFET chip.
Embodiment 2: a kind of DFN encapsulating structure of power mosfet chip; Comprise MOSFET chip 1, epoxy resin layer 2; Said MOSFET chip upper surface 1 is provided with source electrode and grid, and lower surface is provided with drain electrode, also comprises conduction basal disc 3, first conductive welding disk 4 and second conductive welding disk 5; Said conduction basal disc 3 is made up of radiating area 31 and basal disc pin area 32; This basal disc pin area 32 is made up of several drain lead 321 alternately, and these drain lead 321 1 ends are electrically connected with radiating area 31 end faces, said radiating area 31 under the MOSFET chip 1 and with MOSFET chip 1 lower surface between be electrically connected through the soft soldering bed of material 6; Said first conductive welding disk 7 and second conductive welding disk 8 are positioned at MOSFET chip 1 opposite side; First conductive welding disk 4 and second conductive welding disk 5 include weld zone 7 and pin area 8; Weld zone 7 has a bending part 9 with the junction of pin area 8, thereby makes weld zone 7 be higher than pin area 8; Some first metal wire 10 cross-over connections are between the weld zone 7 of the source electrode of said MOSFET chip 1 and first conductive welding disk 4, and 11 cross-over connections of second metal wire are between the weld zone 7 of the grid of said MOSFET chip 1 and second conductive welding disk 5; The said soft soldering bed of material 6 is made up of the component of following quality percentage composition: lead 92.5%, tin 5%, silver 2.5%.
The number of above-mentioned first metal wire 10 is at least four.
The pin area of above-mentioned first conductive welding disk 4 is made up of at least four root utmost point pins.
The pin area of above-mentioned second conductive welding disk 5 is made up of a gate lead.
The number of above-mentioned drain lead 321 is four.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.

Claims (6)

1. the DFN encapsulating structure of a power mosfet chip; Comprise MOSFET chip (1), epoxy resin layer (2); Said MOSFET chip upper surface (1) is provided with source electrode and grid; Lower surface is provided with drain electrode; It is characterized in that: also comprise conduction basal disc (3), first conductive welding disk (4) and second conductive welding disk (5), said conduction basal disc (3) is made up of radiating area (31) and basal disc pin area (32), and this basal disc pin area (32) is made up of several drain lead (321) alternately; These drain lead (321) one ends are electrically connected with radiating area (31) end face, said radiating area (31) be positioned under the MOSFET chip (1) and with MOSFET chip (1) lower surface between be electrically connected through the soft soldering bed of material (6); Said first conductive welding disk (4) and second conductive welding disk (5) are positioned at MOSFET chip (1) opposite side; First conductive welding disk (4) and second conductive welding disk (5) include weld zone (7) and pin area (8); Weld zone (7) has a bending part (9) with the junction of pin area (8), thereby makes weld zone (7) be higher than pin area (8); Some first metal wires (10) cross-over connection is between the weld zone (7) of the source electrode of said MOSFET chip (1) and first conductive welding disk (4), and second metal wire (11) cross-over connection is between the weld zone (7) of the grid of said MOSFET chip (1) and second conductive welding disk (5); The said soft soldering bed of material (6) is made up of the component of following quality percentage composition: lead 92.5%, tin 5%, silver 2.5%.
2. DFN encapsulating structure according to claim 1 is characterized in that: said first conductive welding disk (4) and second conductive welding disk (5) weld zone (7) separately is positioned at same horizontal plane with the MOSFET chip.
3. DFN encapsulating structure according to claim 1 is characterized in that: the number of said first metal wire (10) is at least four.
4. DFN encapsulating structure according to claim 1 is characterized in that: the pin area of said first conductive welding disk (4) is made up of at least four root utmost point pins.
5. DFN encapsulating structure according to claim 1 is characterized in that: the pin area of said second conductive welding disk (5) is made up of a gate lead.
6. DFN encapsulating structure according to claim 1 is characterized in that: the number of said drain lead (321) is four.
CN201210302426.3A 2012-08-23 2012-08-23 The DFN encapsulating structure of power mosfet chip Active CN102842550B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617156A (en) * 2015-01-19 2015-05-13 苏州固锝电子股份有限公司 Rectifying chip for microelectronic device
CN109727943A (en) * 2019-02-27 2019-05-07 无锡新洁能股份有限公司 A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance
CN110556366A (en) * 2019-09-28 2019-12-10 华南理工大学 GaN-based cascaded power device and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512759A (en) * 2005-06-10 2009-08-19 万国半导体股份有限公司 Dfn semiconductor package having reduced electrical resistance
US20110272794A1 (en) * 2007-01-24 2011-11-10 Erwin Victor Cruz Pre-molded clip structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512759A (en) * 2005-06-10 2009-08-19 万国半导体股份有限公司 Dfn semiconductor package having reduced electrical resistance
US20110272794A1 (en) * 2007-01-24 2011-11-10 Erwin Victor Cruz Pre-molded clip structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617156A (en) * 2015-01-19 2015-05-13 苏州固锝电子股份有限公司 Rectifying chip for microelectronic device
CN104617156B (en) * 2015-01-19 2017-10-13 苏州固锝电子股份有限公司 Rectification chip for microelectronic component
CN108598179A (en) * 2015-01-19 2018-09-28 苏州固锝电子股份有限公司 Use for electronic products high current rectification chip
CN108598178A (en) * 2015-01-19 2018-09-28 苏州固锝电子股份有限公司 High stability microelectronic component
CN108598177A (en) * 2015-01-19 2018-09-28 苏州固锝电子股份有限公司 High yield rectifying device in high precision
CN108598178B (en) * 2015-01-19 2020-12-04 苏州固锝电子股份有限公司 Rectifying chip for microelectronic device
CN109727943A (en) * 2019-02-27 2019-05-07 无锡新洁能股份有限公司 A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance
CN110556366A (en) * 2019-09-28 2019-12-10 华南理工大学 GaN-based cascaded power device and preparation method thereof

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