CN202796930U - Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip - Google Patents
Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip Download PDFInfo
- Publication number
- CN202796930U CN202796930U CN2012204211972U CN201220421197U CN202796930U CN 202796930 U CN202796930 U CN 202796930U CN 2012204211972 U CN2012204211972 U CN 2012204211972U CN 201220421197 U CN201220421197 U CN 201220421197U CN 202796930 U CN202796930 U CN 202796930U
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- China
- Prior art keywords
- mosfet chip
- conductive pad
- area
- conductive
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/521—Structures or relative sizes of bond wires
- H10W72/527—Multiple bond wires having different sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/926—Multiple bond pads having different sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本实用新型公开一种用于MOSFET芯片的封装体，包括MOSFET芯片、环氧树脂层，导电基盘、第一导电焊盘和第二导电焊盘，所述导电基盘由散热区和基盘引脚区组成，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过导电焊料层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区；若干根第一金属线跨接于所述MOSFET芯片的源极与第一导电焊盘的焊接区之间，第二金属线跨接于所述MOSFET芯片的栅极与第二导电焊盘的焊接区之间。本实用新型封装体有利于进一步缩小器件的体积，同时减少封装体中部件的数目；且提升器件MOSFET芯片散热效率。
The utility model discloses a packaging body for a MOSFET chip, which comprises a MOSFET chip, an epoxy resin layer, a conductive substrate, a first conductive pad and a second conductive pad, and the conductive substrate consists of a heat dissipation area and a substrate The heat dissipation area is located directly under the MOSFET chip and is electrically connected to the lower surface of the MOSFET chip through a conductive solder layer; the first conductive pad and the second conductive pad are located on the other side of the MOSFET chip. Both a conductive pad and a second conductive pad include a welding area and a pin area; several first metal wires are connected between the source of the MOSFET chip and the welding area of the first conductive pad, and the second metal The wire is connected between the gate of the MOSFET chip and the welding area of the second conductive pad. The packaging body of the utility model is beneficial to further reducing the volume of the device, and at the same time reducing the number of parts in the packaging body; and improving the heat dissipation efficiency of the MOSFET chip of the device.
Description
Technical field
The utility model relates to MOSFET chip technology field, is specifically related to a kind of packaging body for the MOSFET chip.
Background technology
Along with the fast development of electronic manufacturing technology, consumption electronic product is more and more to small-sized, portable trend development, and this space that has also caused the within of these electronic products to be enough in the layout electricity component becomes more and more limited.In the case, the electricity component of employing certainly will be got over Bao Yuehao, and this also becomes present electronic components fabrication development trend also.Quad flat non-leaded chip package (QFN) technique can satisfy this demand just.
Be the generalized section of a kind of typical QFN encapsulating structure in the prior art shown in the accompanying drawing 1, comprise chip 900, fin 920, lead frame 930, a plurality of wire 940, and the insulating cement 950 of parcel said structure.Chip 900 sticks on the fin 920, and lead frame 930 has the pin of a plurality of mutually insulateds, and the pad on chip 900 surfaces is connected to lead frame 93 by wire 940.On the corresponding pin.Insulating cement 950 all wraps up said structure, with it with extraneous isolation, only each pin of lead frame 930 and fin 920 and chip 900 relative surfaces are exposed in the air.The pin that lead frame 930 comes out is used for realizing that packed chip 900 connects with extraneous electricity, and the heat that the effect that fin 920 comes out produces when being chip 900 work is dispersed in the environment by the surface that exposes and goes.
Summary of the invention
The utility model purpose provides a kind of packaging body for the MOSFET chip, and this packaging body is conducive to the volume of further reduction of device, reduces simultaneously the number of parts in the packaging body; And boost device MOSFET chip cooling efficient.
For achieving the above object, the technical solution adopted in the utility model is: a kind of packaging body for the MOSFET chip, comprise MOSFET chip, epoxy resin layer, described MOSFET chip upper surface is provided with source electrode and grid, lower surface is provided with drain electrode, also comprise conduction basal disc, the first conductive welding disk and the second conductive welding disk, described conduction basal disc is comprised of radiating area and basal disc pin area, described radiating area under the MOSFET chip and with MOSFET chip lower surface between be electrically connected by the conductive solder layer; Described the first conductive welding disk and the second conductive welding disk are positioned at MOSFET chip opposite side, and the first conductive welding disk and the second conductive welding disk include weld zone and pin area; Some the first metal wires are connected across between the weld zone of the source electrode of described MOSFET chip and the first conductive welding disk, and the second metal wire is connected across between the weld zone of the grid of described MOSFET chip and the second conductive welding disk.
Further improved plan is as follows in the technique scheme:
1, in the such scheme, the number of described the first metal wire is at least four.
2, in the such scheme, the pin area of described the first conductive welding disk is by at least four root utmost point pin set
Become.
3, in the such scheme, the pin area of described the second conductive welding disk is comprised of a gate lead.
Because technique scheme is used, the utility model compared with prior art has following advantages and effect:
1, conducts electricity basal disc in the utility model packaging body, it has had both conductive welding disk in the prior art, three component functions of fin and basic island simultaneously, the volume that both had been conducive to further reduction of device, also reduce the number of parts in the device, because radiating area and basal disc pin area are as a whole, improved the stability of electrical property simultaneously.
2, its basal disc pin area of the utility model packaging body is comprised of several drain lead alternately, the pin area of the first conductive welding disk is comprised of at least four root utmost point pins, fully take into account the large difference of the MOSFET chip relative grid current with source electrode of drain electrode, thereby be conducive to reduce the generation of heat, and further improved electrical performance indexes.
Description of drawings
Fig. 1 is the prior art structural representation;
Fig. 2 is the package body structure schematic diagram that the utility model is used for the MOSFET chip;
Fig. 3 is along the cutaway view of A-A line in the accompanying drawing 2.
In the above accompanying drawing: 1, MOSFET chip; 2, epoxy resin layer; 3, conduction basal disc; 31, radiating area; 32, basal disc pin area; 4, the first conductive welding disk; 5, the second conductive welding disk; 6, conductive solder layer; 7, weld zone; 8, pin area; 9, the first metal wire; 10, the second metal wire.
Embodiment
Below in conjunction with embodiment the utility model is further described:
Embodiment 1: a kind of packaging body for the MOSFET chip, comprise MOSFET chip 1, epoxy resin layer 2, described MOSFET chip upper surface 1 is provided with source electrode and grid, lower surface is provided with drain electrode, also comprise conduction basal disc 3, the first conductive welding disk 4 and the second conductive welding disk 5, described conduction basal disc 3 is comprised of radiating area 31 and basal disc pin area 32, described radiating area 31 under the MOSFET chip 1 and with MOSFET chip 1 lower surface between be electrically connected by conductive solder layer 6; Described the first conductive welding disk 7 and the second conductive welding disk 8 are positioned at MOSFET chip 1 opposite side, and the first conductive welding disk 4 and the second conductive welding disk 5 include weld zone 7 and pin area 8; Some the first metal wires 9 are connected across between the weld zone 7 of the source electrode of described MOSFET chip 1 and the first conductive welding disk 4, and the second metal wire 10 is connected across between the weld zone 7 of the grid of described MOSFET chip 1 and the second conductive welding disk 5.
The number of above-mentioned the first metal wire 9 is at least four.
The pin area of above-mentioned the first conductive welding disk 4 is comprised of at least four root utmost point pins.
The pin area of above-mentioned the second conductive welding disk 5 is comprised of a gate lead.
Above-described embodiment only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the personage who is familiar with technique can understand content of the present utility model and according to this enforcement, can not limit protection range of the present utility model with this.All equivalences of doing according to the utility model Spirit Essence change or modify, and all should be encompassed within the protection range of the present utility model.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204211972U CN202796930U (en) | 2012-08-23 | 2012-08-23 | Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204211972U CN202796930U (en) | 2012-08-23 | 2012-08-23 | Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202796930U true CN202796930U (en) | 2013-03-13 |
Family
ID=47824133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012204211972U Expired - Lifetime CN202796930U (en) | 2012-08-23 | 2012-08-23 | Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202796930U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219315A (en) * | 2013-03-22 | 2013-07-24 | 苏州固锝电子股份有限公司 | Schottky rectification chip packaging structure |
-
2012
- 2012-08-23 CN CN2012204211972U patent/CN202796930U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219315A (en) * | 2013-03-22 | 2013-07-24 | 苏州固锝电子股份有限公司 | Schottky rectification chip packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130313 |