CN202796930U - Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip - Google Patents

Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip Download PDF

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Publication number
CN202796930U
CN202796930U CN2012204211972U CN201220421197U CN202796930U CN 202796930 U CN202796930 U CN 202796930U CN 2012204211972 U CN2012204211972 U CN 2012204211972U CN 201220421197 U CN201220421197 U CN 201220421197U CN 202796930 U CN202796930 U CN 202796930U
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CN
China
Prior art keywords
mosfet chip
welding disk
electric conduction
conductive welding
packaging body
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Expired - Lifetime
Application number
CN2012204211972U
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Chinese (zh)
Inventor
胡乃仁
杨小平
李国发
钟利强
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Suzhou Good Ark Electronics Co Ltd
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Suzhou Good Ark Electronics Co Ltd
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Priority to CN2012204211972U priority Critical patent/CN202796930U/en
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Publication of CN202796930U publication Critical patent/CN202796930U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The utility model discloses a packaging body for a metal-oxide-semiconductor field effect transistor (MOSFET) chip. The packaging body comprises the MOSFET chip, an epoxy resin layer, an electric conduction base disc, a first electric conduction pad and a second electric conduction pad, the electric conduction base disc is composed of a heat dissipation area and a base disc pin area, and the heat dissipation area is located under the MOSFET chip and electrically connected with a lower surface of the MOSFET chip through an electric conduction welding flux layer. The first electric conduction pad and the second electric conduction pad are located on the other side of the MOSFET chip, and the first electric conduction pad and the second electric conduction pad both comprise a welding area and a pin area. A plurality of first metal wires are bridged between a source electrode of the MOSFET chip and the welding area of the first electric conduction pad, and second metal wires are bridged between a grid electrode of the MOSFET chip and the welding area of the second electric conduction pad. The packaging body is favorable for further reduction of size of devices, simultaneously decreases quantity of middle pieces, and promotes heat dissipation efficiency of the MOSFET chip of the devices.

Description

The packaging body that is used for the MOSFET chip
Technical field
The utility model relates to MOSFET chip technology field, is specifically related to a kind of packaging body for the MOSFET chip.
Background technology
Along with the fast development of electronic manufacturing technology, consumption electronic product is more and more to small-sized, portable trend development, and this space that has also caused the within of these electronic products to be enough in the layout electricity component becomes more and more limited.In the case, the electricity component of employing certainly will be got over Bao Yuehao, and this also becomes present electronic components fabrication development trend also.Quad flat non-leaded chip package (QFN) technique can satisfy this demand just.
Be the generalized section of a kind of typical QFN encapsulating structure in the prior art shown in the accompanying drawing 1, comprise chip 900, fin 920, lead frame 930, a plurality of wire 940, and the insulating cement 950 of parcel said structure.Chip 900 sticks on the fin 920, and lead frame 930 has the pin of a plurality of mutually insulateds, and the pad on chip 900 surfaces is connected to lead frame 93 by wire 940.On the corresponding pin.Insulating cement 950 all wraps up said structure, with it with extraneous isolation, only each pin of lead frame 930 and fin 920 and chip 900 relative surfaces are exposed in the air.The pin that lead frame 930 comes out is used for realizing that packed chip 900 connects with extraneous electricity, and the heat that the effect that fin 920 comes out produces when being chip 900 work is dispersed in the environment by the surface that exposes and goes.
Summary of the invention
The utility model purpose provides a kind of packaging body for the MOSFET chip, and this packaging body is conducive to the volume of further reduction of device, reduces simultaneously the number of parts in the packaging body; And boost device MOSFET chip cooling efficient.
For achieving the above object, the technical solution adopted in the utility model is: a kind of packaging body for the MOSFET chip, comprise MOSFET chip, epoxy resin layer, described MOSFET chip upper surface is provided with source electrode and grid, lower surface is provided with drain electrode, also comprise conduction basal disc, the first conductive welding disk and the second conductive welding disk, described conduction basal disc is comprised of radiating area and basal disc pin area, described radiating area under the MOSFET chip and with MOSFET chip lower surface between be electrically connected by the conductive solder layer; Described the first conductive welding disk and the second conductive welding disk are positioned at MOSFET chip opposite side, and the first conductive welding disk and the second conductive welding disk include weld zone and pin area; Some the first metal wires are connected across between the weld zone of the source electrode of described MOSFET chip and the first conductive welding disk, and the second metal wire is connected across between the weld zone of the grid of described MOSFET chip and the second conductive welding disk.
Further improved plan is as follows in the technique scheme:
1, in the such scheme, the number of described the first metal wire is at least four.
2, in the such scheme, the pin area of described the first conductive welding disk is by at least four root utmost point pin set
Become.
3, in the such scheme, the pin area of described the second conductive welding disk is comprised of a gate lead.
Because technique scheme is used, the utility model compared with prior art has following advantages and effect:
1, conducts electricity basal disc in the utility model packaging body, it has had both conductive welding disk in the prior art, three component functions of fin and basic island simultaneously, the volume that both had been conducive to further reduction of device, also reduce the number of parts in the device, because radiating area and basal disc pin area are as a whole, improved the stability of electrical property simultaneously.
2, its basal disc pin area of the utility model packaging body is comprised of several drain lead alternately, the pin area of the first conductive welding disk is comprised of at least four root utmost point pins, fully take into account the large difference of the MOSFET chip relative grid current with source electrode of drain electrode, thereby be conducive to reduce the generation of heat, and further improved electrical performance indexes.
Description of drawings
Fig. 1 is the prior art structural representation;
Fig. 2 is the package body structure schematic diagram that the utility model is used for the MOSFET chip;
Fig. 3 is along the cutaway view of A-A line in the accompanying drawing 2.
In the above accompanying drawing: 1, MOSFET chip; 2, epoxy resin layer; 3, conduction basal disc; 31, radiating area; 32, basal disc pin area; 4, the first conductive welding disk; 5, the second conductive welding disk; 6, conductive solder layer; 7, weld zone; 8, pin area; 9, the first metal wire; 10, the second metal wire.
Embodiment
Below in conjunction with embodiment the utility model is further described:
Embodiment 1: a kind of packaging body for the MOSFET chip, comprise MOSFET chip 1, epoxy resin layer 2, described MOSFET chip upper surface 1 is provided with source electrode and grid, lower surface is provided with drain electrode, also comprise conduction basal disc 3, the first conductive welding disk 4 and the second conductive welding disk 5, described conduction basal disc 3 is comprised of radiating area 31 and basal disc pin area 32, described radiating area 31 under the MOSFET chip 1 and with MOSFET chip 1 lower surface between be electrically connected by conductive solder layer 6; Described the first conductive welding disk 7 and the second conductive welding disk 8 are positioned at MOSFET chip 1 opposite side, and the first conductive welding disk 4 and the second conductive welding disk 5 include weld zone 7 and pin area 8; Some the first metal wires 9 are connected across between the weld zone 7 of the source electrode of described MOSFET chip 1 and the first conductive welding disk 4, and the second metal wire 10 is connected across between the weld zone 7 of the grid of described MOSFET chip 1 and the second conductive welding disk 5.
The number of above-mentioned the first metal wire 9 is at least four.
The pin area of above-mentioned the first conductive welding disk 4 is comprised of at least four root utmost point pins.
The pin area of above-mentioned the second conductive welding disk 5 is comprised of a gate lead.
Above-described embodiment only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the personage who is familiar with technique can understand content of the present utility model and according to this enforcement, can not limit protection range of the present utility model with this.All equivalences of doing according to the utility model Spirit Essence change or modify, and all should be encompassed within the protection range of the present utility model.

Claims (4)

1. packaging body that is used for the MOSFET chip, comprise MOSFET chip (1), epoxy resin layer (2), described MOSFET chip upper surface (1) is provided with source electrode and grid, lower surface is provided with drain electrode, it is characterized in that: also comprise conduction basal disc (3), the first conductive welding disk (4) and the second conductive welding disk (5), described conduction basal disc (3) is comprised of radiating area (31) and basal disc pin area (32), described radiating area (31) be positioned under the MOSFET chip (1) and with MOSFET chip (1) lower surface between be electrically connected by conductive solder layer (6); Described the first conductive welding disk (7) and the second conductive welding disk (8) are positioned at MOSFET chip (1) opposite side, and the first conductive welding disk (4) and the second conductive welding disk (5) include weld zone (7) and pin area (8); Some the first metal wires (9) are connected across between the weld zone (7) of the source electrode of described MOSFET chip (1) and the first conductive welding disk (4), and the second metal wire (10) is connected across between the weld zone (7) of the grid of described MOSFET chip (1) and the second conductive welding disk (5).
2. packaging body according to claim 1, it is characterized in that: the number of described the first metal wire (9) is at least four.
3. packaging body according to claim 1, it is characterized in that: the pin area of described the first conductive welding disk (4) is comprised of at least four root utmost point pins.
4. packaging body according to claim 1, it is characterized in that: the pin area of described the second conductive welding disk (5) is comprised of a gate lead.
CN2012204211972U 2012-08-23 2012-08-23 Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip Expired - Lifetime CN202796930U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012204211972U CN202796930U (en) 2012-08-23 2012-08-23 Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012204211972U CN202796930U (en) 2012-08-23 2012-08-23 Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219315A (en) * 2013-03-22 2013-07-24 苏州固锝电子股份有限公司 Schottky rectification chip packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219315A (en) * 2013-03-22 2013-07-24 苏州固锝电子股份有限公司 Schottky rectification chip packaging structure

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Granted publication date: 20130313

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