CN204558445U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
- Publication number
- CN204558445U CN204558445U CN201520263438.9U CN201520263438U CN204558445U CN 204558445 U CN204558445 U CN 204558445U CN 201520263438 U CN201520263438 U CN 201520263438U CN 204558445 U CN204558445 U CN 204558445U
- Authority
- CN
- China
- Prior art keywords
- conducting strip
- semiconductor package
- lead frame
- connecting portion
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 239000002131 composite material Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
- H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
The utility model discloses a semiconductor packaging structure contains first lead frame, first semiconductor component, second lead frame, first conducting strip and insulating conducting strip. The first semiconductor device is disposed on the first lead frame. The first semiconductor element has a bottom connection portion, a top connection portion, a bottom surface, and a top surface. The top and bottom surfaces are opposite. The bottom connecting part and the top connecting part are respectively positioned on the bottom surface and the top surface. The bottom connecting part is electrically connected with the first lead frame. The second lead frame is insulated from the first lead frame. The first conducting sheet is arranged on the top surface and is electrically connected with the top connecting part and the second lead frame. The insulating heat-conducting sheet is arranged on the first conductive sheet. According to the utility model discloses a semiconductor package structure, because can be equipped with the conducting strip that has insulating property on the first conducting strip, so can be under the prerequisite that satisfies the heat dissipation demand, prevent that the semiconductor component after the encapsulation from producing unnecessary electric connection with other components.
Description
Technical field
The utility model relates to a kind of encapsulating structure, particularly a kind of semiconductor package.
Background technology
Along with the development that electronic product makes rapid progress, the application of semiconductor wafer and function are also flourish.Semiconductor wafer is provided with usually the circuit of many precisions, so need encapsulated semiconductor wafer to protect semiconductor wafer.
In order to available protecting semiconductor wafer, producer can adopt encapsulating structure usually, carrys out complete coated semiconductor wafer.Encapsulating structure also must possess enough mechanical strengths, to avoid semiconductor wafer impaired because of collision.Therefore, encapsulating structure normally made by the resin material with high mechanical properties, such as epoxy resin.Because the coefficient of heat conduction of these encapsulating materials itself is not high, so be difficult to provide good radiating effect.
In order to provide good radiating effect, inventor of the present utility model announces in No. M388730 application at TaiWan, China new patent, propose a kind of encapsulating structure of Improvement type, it just arranges sheet metal on the semiconductor wafer, with the effect taking into account heat radiation and be electrically connected.
But, when staff is moving this encapsulating structure or carrying out aft-loaded airfoil, and when touching sheet metal or cause other electric conducting materials to fall on sheet metal, easily make semiconductor wafer and other elements produce unnecessary electric connection.
Utility model content
Given this, the purpose of this utility model is to provide a kind of semiconductor package, thus prevents the semiconductor element after encapsulating and other elements from producing unnecessary electric connection.
In order to achieve the above object, according to an execution mode of the present utility model, a kind of semiconductor package comprises the first lead frame, the first semiconductor element, the second lead frame, the first conducting strip and insulating heat-conductive sheet.First semiconductor element is arranged on the first lead frame.First semiconductor element has end connecting portion, top connecting portion, bottom surface and end face.End face and bottom surface be back to.End connecting portion lays respectively at bottom surface and end face with top connecting portion.End connecting portion is electrically connected the first lead frame.Second lead frame insulate mutually with the first lead frame.First conducting strip is arranged on end face, and is electrically connected top connecting portion and the second lead frame.Insulating heat-conductive sheet is arranged on the first conducting strip.
Preferably, in technique scheme, semiconductor package also comprises the second conducting strip, and insulating heat-conductive sheet is located between the first conducting strip and the second conducting strip, and insulate the first conducting strip and the second conducting strip.
Preferably, in technique scheme, semiconductor package also comprises the second conducting strip, and insulating heat-conductive sheet contacts the first conducting strip and the second conducting strip, and separates the first conducting strip and the second conducting strip.
Preferably, in technique scheme, semiconductor package also comprises auxiliary heat conduction sheet, and auxiliary heat conduction sheet is arranged on the second conducting strip, and the surface area of auxiliary heat conduction sheet is greater than the surface area of the second conducting strip.
Preferably, in technique scheme, auxiliary heat conduction sheet is welded on the second conducting strip.
Preferably, in technique scheme, semiconductor package also comprises the second semiconductor element, and it is arranged on the second conducting strip, and is electrically connected the second conducting strip.
Preferably, in technique scheme, semiconductor package also comprises intermediary's conductive part, and it runs through insulating heat-conductive sheet, and is electrically connected the first conducting strip and the second conducting strip.
Preferably, in technique scheme, the first conducting strip comprises: main body and extension.Main body is positioned at above the top connecting portion of the first semiconductor element.Extension extends downward the second lead frame from main body, and connects the second lead frame.
Preferably, in technique scheme, semiconductor package also comprises conducting resinl, and it is adhered between the end face of the first conducting strip and the first semiconductor element.
Preferably, in technique scheme, semiconductor package also comprises solder layer, and it is located between the bottom surface of the first lead frame and the first semiconductor element.
By above-mentioned execution mode, the first conducting strip can be provided with the conducting strip with insulation characterisitic, so can, under the prerequisite meeting radiating requirements, prevent the semiconductor element after encapsulating and other elements from producing unnecessary electric connection.
The above is only for the effect etc. setting forth problem to be solved in the utility model, the technological means of dealing with problems and produce, and detail of the present utility model is introduced in detail by execution mode hereafter and relevant drawings.
Accompanying drawing explanation
For above and other object of the present utility model, feature, advantage and embodiment can be become apparent, appended the description of the drawings is as follows:
Fig. 1 is the generalized section of the semiconductor package according to the utility model execution mode;
Fig. 2 is the generalized section of the semiconductor package according to another execution mode of the utility model;
Fig. 3 is the generalized section of the semiconductor package according to another execution mode of the utility model;
Fig. 4 is the generalized section of the semiconductor package according to another execution mode of the utility model; And
Fig. 5 is the generalized section of the semiconductor package according to another execution mode of the utility model.
Embodiment
Below will disclose multiple execution mode of the present utility model with accompanying drawing, as clearly stated, many concrete details will be explained in the following description.But those skilled in the art should recognize, in the utility model some embodiments, these concrete details are also non-essential, therefore shall not be applied to restriction the utility model.In addition, for simplifying for the purpose of accompanying drawing, some known usual structures and element describe in the mode simply illustrated in the accompanying drawings.
Fig. 1 is the generalized section of the semiconductor package according to the utility model execution mode.As shown in Figure 1, semiconductor package comprises composite sheet group 100, first semiconductor element 200, first lead frame 510 and the second lead frame 520.First semiconductor element 200 is arranged at the first lead frame 510.First semiconductor element 200 has bottom surface 201, end connecting portion 202, end face 203 and top connecting portion 204.Bottom surface 201 and end face 203 be back to.End connecting portion 202 is positioned at bottom surface 201, and pushes up connecting portion 204 and be positioned at end face 203.End connecting portion 202 is than pushing up connecting portion 204 closer to the first lead frame 510, and end connecting portion 202 is electrically connected the first lead frame 510.Second lead frame 520 insulate with the first lead frame 510 phase.
Composite sheet group 100 is arranged on the end face 203 of the first semiconductor element 200, and composite sheet group 100 comprises the first conducting strip 110 and insulating heat-conductive sheet 130.First conducting strip 110 is arranged on end face 203, and insulating heat-conductive sheet 130 is arranged on the first conducting strip 110.In other words, the first conducting strip 110 is between insulating heat-conductive sheet 130 and the first semiconductor element 200, and insulating heat-conductive sheet 130 covers the first conducting strip 110.First conducting strip 110 is electrically connected top connecting portion 204 and the second lead frame 520.
Configured by said elements, due to the first conducting strip 110 can be provided with insulating heat-conductive sheet 130, so can, under the prerequisite meeting radiating requirements, prevent the first semiconductor element 200 from producing unnecessary electric connection with other elements outside semiconductor package.For example, the first conducting strip 110 can be sheet metal, and such as: copper sheet, but the utility model is not as limit; Insulating heat-conductive sheet 130 can be potsherd, but the utility model is not as limit.Because potsherd and copper sheet all have high thermal conductivity coefficient, so the heat that the first semiconductor element 200 produces can quickly move through the high copper sheet of conductive coefficient and potsherd is passed to external environment, separately because potsherd is insulation, even if so there is electric conducting material to fall on potsherd, also can not be electrically connected the first semiconductor element 200, and the work of the first semiconductor element 200 can not be affected.
In some embodiments, semiconductor package also comprises conducting resinl 300.Conducting resinl 300 is adhered between the first conducting strip 110 and the end face 203 of the first semiconductor element 200.Furthermore, conducting resinl 300 is adhered between the top connecting portion 204 and the first conducting strip 110 of end face 203.Thus, conducting resinl 300 can be electrically connected and fix the top connecting portion 204 of the first conducting strip 110 and the first semiconductor element 200.In other embodiments, also can without conducting resinl 300 between the first conducting strip 110 and top connecting portion 204, but contact with each other.
In some embodiments, semiconductor package also comprises solder layer 400.Solder layer 400 is located between the bottom surface 201 of the first semiconductor element 200 and the first lead frame 510.Furthermore, solder layer 400 is between end connecting portion 202 and the first lead frame 510.Thus, solder layer 400 can be electrically connected and fix end connecting portion 202 and the first lead frame 510.In other embodiments, also can the solderless bed of material 400 between the first lead frame 510 and end connecting portion 202, but contact with each other.
In some embodiments, the second lead frame 520 and the first lead frame 510 are positioned at same horizontal plane in fact, and this horizontal plane is positioned at below the first semiconductor element 200.First lead frame 510 is separated mutually with the second lead frame 520, makes the first lead frame 510 and the second lead frame 520 energy mutually insulated.First conducting strip 110 comprises main body 112 and extension 114.Main body 112 is positioned at above the top connecting portion 204 of the first semiconductor element 200.Extension 114 extends downward the second lead frame 520 from main body 112, and connects the second lead frame 520.Thus, even if the second lead frame 520 is positioned at the horizontal plane below the first semiconductor element 200, and the first conducting strip 110 is positioned at above the first semiconductor element 200, and the first conducting strip 110 still can be electrically connected the second lead frame 520.
In some embodiments, the first semiconductor element 200 can be power metal-oxide semiconductor (powerMPS) or power MOSFET answers transistor (power MOSFET) constant power element, but the utility model is not as limit.When the first semiconductor element 200 is above-mentioned power component, except being provided with the top connecting portion 204 of electric connection second lead frame 520 on its end face 203, end connecting portion 202, top connecting portion 204 and this unshowned connecting portion also additionally can be provided with another connecting portion (not shown), so can be respectively three electrodes (as grid, drain electrode and source electrode) of the first semiconductor element 200.
In some embodiments, composite sheet group 100 can comprise the second conducting strip 120 further.Insulating heat-conductive sheet 130 is located between the first conducting strip 110 and the second conducting strip 120, and first conducting strip 110 and the second conducting strip 120 that insulate.Whereby, producer can do the application of various extendibility to this semiconductor package, such as: on the second conducting strip 120, extra soldered conducting strip is with heat radiation ability; Or other semiconductor elements are additionally set on the second conducting strip 120 to realize three-dimensional stacking semiconductor package.
Specifically, insulating heat-conductive sheet 130 is between the first conducting strip 110 and the second conducting strip 120, and contact the first conducting strip 110 and the second conducting strip 120, thus, the heat that the first semiconductor element 200 is operationally produced can conduct to the first conducting strip 110, insulating heat-conductive sheet 130 and the second conducting strip 120 in thermo-conducting manner.In addition, insulating heat-conductive sheet 130 separates the first conducting strip 110 and the second conducting strip 120, insulate with the second conducting strip 120 phase to make the first conducting strip 110.Whereby, even if when having unnecessary electric conducting material to drop on the second conducting strip 120, the first semiconductor element 200 also can not be electrically connected, and affects the work of the first semiconductor element 200.In some embodiments, the second conducting strip 120 can be copper sheet, but the utility model is not as limit.
Fig. 2 is the generalized section of the semiconductor package according to another execution mode of the utility model.As shown in Figure 2, the Main Differences between present embodiment and Fig. 1 illustrated embodiment is: the semiconductor package of present embodiment comprises auxiliary heat conduction sheet 600 further.Auxiliary heat conduction sheet 600 is arranged on the second conducting strip 120.The surface area of auxiliary heat conduction sheet 600 is greater than the surface area of the second conducting strip 120.Thus, even if the heat-sinking capability that composite sheet group 100 provides is not inconsistent demand, because auxiliary heat conduction sheet 600 has relatively large area, so heat radiation can be helped further, to improve the integral heat sink ability of semiconductor package.
Furthermore, auxiliary heat conduction sheet 600 can be welded on the second conducting strip 120, and fixes with the second conducting strip 120.Specifically, the second conducting strip 120 can comprise lower surface 122 and upper surface 124.Lower surface 122 and upper surface 124 be back to.Lower surface 122 is toward insulating heat-conductive sheet 130.Upper surface 124 is towards auxiliary heat conduction sheet 600.Auxiliary heat conduction sheet 600 is welded on the upper surface 124 of the second conducting strip 120, to fix with the second conducting strip 120.In this embodiment, because the second conducting strip 120 is conductor (as copper sheet), so be comparatively easy to welding compared to insulating heat-conductive sheet 130, second conducting strip 120, be welded on upper surface 124 so auxiliary heat conduction sheet 600 can be beneficial to.In some embodiments, auxiliary heat conduction sheet 600 can be sheet metal (as copper sheet), be beneficial to welding, but the utility model is not as limit.
Fig. 3 is the generalized section of the semiconductor package according to another execution mode of the utility model.As shown in Figure 3, Main Differences between present embodiment and Fig. 1 illustrated embodiment is: the first conducting strip 110 and the second conducting strip 120 are electrically connected, in order to producer, other semiconductor elements or other electronic components are arranged on the second conducting strip 120, and realize three-dimensional stacking semiconductor package.Furthermore, composite sheet group 100a also can comprise intermediary's conductive part 140.Intermediary's conductive part 140 runs through insulating heat-conductive sheet 130, and is electrically connected the first conducting strip 110 and the second conducting strip 120.In other words, intermediary's conductive part 140 can from the downside of the second conducting strip 120 to downward-extension, and the first conducting strip 110 running through insulating heat-conductive sheet 130 and connect below insulating heat-conductive sheet 130, thus realize the structure of guide hole (Via Hole).
Fig. 4 is the generalized section of the semiconductor package according to another execution mode of the utility model.As shown in Figure 4, the Main Differences between present embodiment and Fig. 3 illustrated embodiment is: the semiconductor package of present embodiment comprises composite sheet group 100 and the second semiconductor element 700 further.Second semiconductor element 700 is arranged on second conducting strip 120 of composite sheet group 100a, and is electrically connected the second conducting strip 120.Composite sheet group 100 is arranged on the second semiconductor element 700, with the effect providing the second semiconductor element 700 to dispel the heat and be electrically connected.Second semiconductor element 700 is roughly the same with the first semiconductor element 200.Specifically, the second semiconductor element 700 has bottom surface 701, end connecting portion 702, end face 703 and top connecting portion 704.Bottom surface 701 and end face 703 be back to.End connecting portion 702 is positioned at bottom surface 701, and pushes up connecting portion 704 and be positioned at end face 703.End connecting portion 702 is electrically connected second conducting strip 120 of the composite sheet group 100a of below, and pushes up the first conducting strip 110 that connecting portion 704 is electrically connected the composite sheet group 100 of top.First conducting strip 110 is electrically connected the second lead frame 520.
Due in composite sheet group 100a, first conducting strip 110 is electrically connected the second conducting strip 120 by intermediary's conductive part 140, so the second conducting strip 120 can provide the end connecting portion 702 of voltage to the second semiconductor element 700, and drive the second semiconductor element 700.Whereby, present embodiment can realize three-dimensional stacking semiconductor package.
Should be appreciated that, the composite sheet group 100 above the second semiconductor element 700 is identical with aforementioned embodiments, so not repeated description.Separately should be appreciated that, present embodiment only illustrate by two semiconductor elements stacking semiconductor package, but in other execution modes, also carry out the semiconductor element of stacking two or more (as three, four, five etc.) by same principle.
In some embodiments, the second semiconductor element 700 can be power metal-oxide semiconductor (powerMPS) or power MOSFET answers transistor (power MOSFET) constant power element, but the utility model is not as limit.When the second semiconductor element 700 is above-mentioned power component, except being provided with the top connecting portion 704 of electric connection second lead frame 520 on its end face 703, end connecting portion 702, top connecting portion 704 and this unshowned connecting portion also additionally can be provided with another connecting portion (not shown), so can be respectively three electrodes (as grid, drain electrode and source electrode) of the second semiconductor element 700.
Fig. 5 is the generalized section of the semiconductor package according to another execution mode of the utility model.As shown in Figure 5, the Main Differences between present embodiment and Fig. 4 illustrated embodiment is: the semiconductor package of present embodiment comprises auxiliary heat conduction sheet 600 further.Auxiliary heat conduction sheet 600 is arranged on the second conducting strip 120 of the composite sheet group 100 above the second semiconductor element 700.The surface area of auxiliary heat conduction sheet 600 is greater than the surface area of the second conducting strip 120.Thus, even if the heat-sinking capability that composite sheet group 100 provides is not enough to the radiating requirements dealing with the second semiconductor element 700, because auxiliary heat conduction sheet 600 has relatively large area, so the heat radiation of the second semiconductor element 700 can be helped further.In some embodiments, auxiliary heat conduction sheet 600 can be welded on the upper surface 124 of the second conducting strip 120.
Although the utility model with execution mode openly as above; so it is not intended to limit the utility model; any those skilled in the art; not departing from spirit and scope of the present utility model; can do various different selection and amendment, therefore protection range of the present utility model limited by claims and equivalents thereof.
Claims (10)
1. a semiconductor package, is characterized in that, described semiconductor package comprises:
First lead frame;
First semiconductor element, it is arranged on described first lead frame, and described first semiconductor element has end connecting portion, top connecting portion, bottom surface and end face, described end face and described bottom surface be back to, connecting portion of the described end and described top connecting portion lay respectively at described bottom surface and described end face, and connecting portion of the described end is electrically connected described first lead frame;
Second lead frame, it insulate mutually with described first lead frame;
First conducting strip, it is arranged on described end face, and is electrically connected described top connecting portion and described second lead frame; And
Insulating heat-conductive sheet, it is arranged on described first conducting strip.
2. semiconductor package as claimed in claim 1, it is characterized in that, described semiconductor package also comprises the second conducting strip, and described insulating heat-conductive sheet is located between described first conducting strip and described second conducting strip, and insulate described first conducting strip and described second conducting strip.
3. semiconductor package as claimed in claim 1, it is characterized in that, described semiconductor package also comprises the second conducting strip, described insulating heat-conductive sheet described first conducting strip of contact and described second conducting strip, and separates described first conducting strip and described second conducting strip.
4. semiconductor package as claimed in claim 2 or claim 3, it is characterized in that, described semiconductor package also comprises auxiliary heat conduction sheet, and described auxiliary heat conduction sheet is arranged on described second conducting strip, and the surface area of described auxiliary heat conduction sheet is greater than the surface area of described second conducting strip.
5. semiconductor package as claimed in claim 4, it is characterized in that, described auxiliary heat conduction sheet is welded on described second conducting strip.
6. semiconductor package as claimed in claim 2 or claim 3, it is characterized in that, described semiconductor package also comprises the second semiconductor element, and it is arranged on described second conducting strip, and is electrically connected described second conducting strip.
7. semiconductor package as claimed in claim 6, it is characterized in that, described semiconductor package also comprises intermediary's conductive part, and it runs through described insulating heat-conductive sheet, and is electrically connected described first conducting strip and described second conducting strip.
8. semiconductor package as claimed in claim 1, it is characterized in that, described first conducting strip comprises:
Main body, it is positioned at above the described top connecting portion of described first semiconductor element; And
Extension, it extends downward described second lead frame from described main body, and connects described second lead frame.
9. semiconductor package as claimed in claim 1, it is characterized in that, described semiconductor package also comprises conducting resinl, and it is adhered between the described end face of described first conducting strip and described first semiconductor element.
10. semiconductor package as claimed in claim 1, it is characterized in that, described semiconductor package also comprises solder layer, and it is located between the described bottom surface of described first lead frame and described first semiconductor element.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104203889 | 2015-03-16 | ||
| TW104203889U TWM505697U (en) | 2015-03-16 | 2015-03-16 | Semiconductor package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204558445U true CN204558445U (en) | 2015-08-12 |
Family
ID=53833526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520263438.9U Active CN204558445U (en) | 2015-03-16 | 2015-04-28 | Semiconductor packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN204558445U (en) |
| TW (1) | TWM505697U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI828503B (en) * | 2022-12-30 | 2024-01-01 | 創世電股份有限公司 | Semiconductor power component and semiconductor power package structure |
-
2015
- 2015-03-16 TW TW104203889U patent/TWM505697U/en unknown
- 2015-04-28 CN CN201520263438.9U patent/CN204558445U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWM505697U (en) | 2015-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8183094B2 (en) | Method of manufacturing a semiconductor device having a semiconductor chip and resin sealing portion | |
| CN105006453B (en) | Encapsulating structure | |
| JP6120704B2 (en) | Semiconductor device | |
| CN104620372B (en) | Semiconductor device | |
| KR102154874B1 (en) | Power semiconductor module and method for producing a power semiconductor module | |
| JP6685884B2 (en) | Semiconductor module | |
| JP2013219267A (en) | Power module | |
| CN103996667B (en) | Semiconductor device with bypass functionality and method thereof | |
| US10672677B2 (en) | Semiconductor package structure | |
| US9006881B2 (en) | Semiconductor device | |
| GB2567746A (en) | Semiconductor device | |
| CN201946588U (en) | Packaging structure for power semiconductors | |
| US8921989B2 (en) | Power electronics modules with solder layers having reduced thermal stress | |
| CN204558445U (en) | Semiconductor packaging structure | |
| CN106783753A (en) | Semiconductor devices | |
| JP2015220295A (en) | Power module and manufacturing method of the same | |
| JP2015023226A (en) | Wide gap semiconductor device | |
| CN208368501U (en) | IGBT module encapsulating structure and cooling system | |
| CN206432253U (en) | Semiconductor devices | |
| JP2017069351A (en) | Semiconductor device | |
| CN102842550A (en) | Dual flat package (DFN) structure of power metal-oxide-semiconductor field effect transistor (MOSFE) chip | |
| CN218647940U (en) | Power module | |
| JP6274019B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2012238737A (en) | Semiconductor module and manufacturing method therefor | |
| JP2011176087A (en) | Semiconductor module, and power conversion apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |