CN201946588U - Packaging structure for power semiconductors - Google Patents

Packaging structure for power semiconductors Download PDF

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Publication number
CN201946588U
CN201946588U CN2010206889539U CN201020688953U CN201946588U CN 201946588 U CN201946588 U CN 201946588U CN 2010206889539 U CN2010206889539 U CN 2010206889539U CN 201020688953 U CN201020688953 U CN 201020688953U CN 201946588 U CN201946588 U CN 201946588U
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CN
China
Prior art keywords
semiconductor chip
substrate
encapsulating structure
electrically connected
power semiconductor
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Expired - Lifetime
Application number
CN2010206889539U
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Chinese (zh)
Inventor
朱克干
吴德皇
宋淑伟
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BYD Co Ltd
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BYD Co Ltd
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Priority to CN2010206889539U priority Critical patent/CN201946588U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Abstract

The utility model discloses a packaging structure for power semiconductors, which comprises an insulation substrate with electric conduction circuits, a second substrate, a first lead foot and a second lead foot, wherein a first surface which bears a first semiconductor chip is arranged on the insulation substrate, a second surface which bears a second semiconductor chip is arranged on the second substrate, the first lead foot is electrically connected with the first semiconductor chip, and the second lead foot is electrically connected with the second semiconductor chip. The insulation substrate with electric conduction circuits, the first semiconductor chip, the second substrate, the second semiconductor chip, the portion of the first lead foot and the portion of the second lead foot are sealed inside resins. The semiconductor chips are loaded by the insulation substrate with electric conduction circuits in the packaging structure, thereby solving the problem of circuit disturbance caused by metal lead frames. The insulation substrate is capable of distributing multilayer wires, thereby further enabling wires distribution of the electric conduction circuits to be easy and improving use ratio of space.

Description

A kind of encapsulating structure of power semiconductor
Technical field
The utility model relates to the integrated circuit encapsulation field, relates in particular to a kind of encapsulating structure of power semiconductor.
Background technology
In present most of IPM(Intelligent Power Module, Intelligent Power Module) encapsulation internal structure all take lead frame and DBC(Direct Bonded Copper basically, cover the copper ceramic substrate) mixing version.The inside IGBT driver part (IGBT chip for driving, gate electrode resistance etc.) of these IPM products all is placed on the lead frame, because these lead frames are metal materials, when placing these as the power device of IGBT driver part, unavoidably can cause the interference of circuit, and in welding resistance, also will between resistance and lead frame, add an insulating barrier.So, when the internal circuit of design IPM encapsulation, if the substrate that the version of only using lead frame to mix with DBC plate (covering the copper ceramic substrate) is built as circuit will run into problems such as circuit interference, conducting wire difficult wiring and space availability ratio are low.
As shown in Figure 1, be present main flow IPM inside modules general frame figure.It is made up of three parts: band IGBT drive components and parts lead frame 1, be welded with IGBT and FRD(Fast Recovery Diode, fast recovery diode) the DBC plate or the lead frame 2 of lead frame 3, the band pin that is connected with 3.Such frame models all is put into the design pressure of the overwhelming majority on the lead frame 1, and promptly the driving components and parts of IGBT such as chip for driving, gate electrode resistance, electric capacity etc. all are transplanted to the welding of making contact above the lead frame 1.But because lead frame 1 itself is that metal material has conductive characteristic, so can have influence on the work that the IGBT of the welding of making contact in the above drives components and parts.
Summary of the invention
The technical problem that the utility model solves is all to utilize lead frame bearing semiconductor chip in the prior art, makes circuit serious interference, conducting wire difficult wiring and the low problem of space availability ratio.
For solving the problems of the technologies described above, the utility model provides following technical scheme:
A kind of encapsulating structure of power semiconductor comprises: have the insulated substrate of conducting wire, described insulated substrate has first surface, loads first semiconductor chip on the described first surface; Second substrate, described second substrate has second surface, and described second surface loads second semiconductor chip; First pin is electrically connected with described first semiconductor chip; Second pin is electrically connected with described second semiconductor chip; Described insulated substrate, first semiconductor chip, second substrate, second semiconductor chip, the part of first pin and the part of second pin with conducting wire is sealed in the resin.
Further, described insulated substrate with conducting wire comprises printed circuit board (PCB).
Preferably, described second substrate is a ceramic substrate.
Further, described ceramic substrate second surface facing surfaces is coated with heat dissipating layer.
Preferably, described heat dissipating layer is the copper layer.
Preferably, described second substrate is the lead frame that is coated with insulating barrier.
Further, described first semiconductor chip and second semiconductor chip are electrically connected.
Preferably, described first semiconductor chip and second semiconductor chip are electrically connected by wiring.
Further, described second semiconductor chip is IGBT and fast recovery diode.
Further, described first semiconductor chip comprises the chip for driving of IGBT.
Compared with prior art the utlity model has following beneficial effect: the encapsulating structure of a kind of power semiconductor that the utility model embodiment provides, utilization has the insulated substrate bearing semiconductor chip of conducting wire, solved the problem of the caused circuit interference of lead frame of metal, because insulated substrate can multilayer wiring, further make the conducting wire wiring easily and improved space availability ratio.
Description of drawings
Fig. 1 is an Intelligent Power Module inner body frame diagram in the prior art.
Fig. 2 is the encapsulating structure frame diagram of embodiment of the invention power semiconductor.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Fig. 2 is the encapsulating structure frame diagram of embodiment of the invention power semiconductor; A kind of encapsulating structure of power semiconductor comprises: have the insulated substrate 20 of conducting wire, described insulated substrate has first surface, loads first semiconductor chip 21 on the described first surface; Second substrate 30, described second substrate has second surface, and described second surface loads second semiconductor chip 31; First pin 10 is electrically connected with described first semiconductor chip 21; Second pin 40 is electrically connected with described second semiconductor chip 31; Described insulated substrate 20, first semiconductor chip 21, second substrate 30, second semiconductor chip 31, the part of first pin 10 and the part of second pin 40 with conducting wire is sealed in the resin.The present embodiment utilization has the insulated substrate bearing semiconductor chip of conducting wire, solved the problem of the caused circuit interference of lead frame of metal, because insulated substrate can multilayer wiring, further make the conducting wire wiring easily and improved space availability ratio.
In the present embodiment, the insulated substrate 20 with conducting wire comprises printed circuit board (PCB), has solved the problem of the caused circuit interference of lead frame of metal effectively; First semiconductor chip 21 of printed circuit board (PCB) carrying is the chip for driving of IGBT, also comprises the gate electrode resistance, gate pole electric capacity of IGBT etc.; This printed circuit board (PCB) can carry out multilayer wiring according to user's request, can farthest utilize the space, and makes wiring be more prone to.Second substrate adjacent with printed circuit board (PCB) is ceramic substrate, and the second surface facing surfaces of loading second semiconductor chip 31 with ceramic substrate is coated with heat dissipating layer, and for good heat radiation, this heat dissipating layer can be the copper layer; According to user's needs, this heat dissipating layer also can be other heat sink material.In other embodiment, second substrate can be for being coated with the lead frame of insulating barrier; This lead frame is a metal material, also can realize heat sinking function preferably.
In the present embodiment, second semiconductor chip of the second surface of second substrate carrying is IGBT and fast recovery diode; IGBT chip for driving on this IGBT and fast recovery diode and the printed circuit board (PCB) etc. is electrically connected; The mode of this electrical connection can be electrically connected by wiring.
In the present embodiment, the part signal of telecommunication of the gate electrode resistance of the chip for driving of IGBT, IGBT, gate pole electric capacity etc. carries out signal by first pin 10 and the outside of resin-encapsulated housing and is electrically connected in first semiconductor chip, and the chip for driving of this IGBT, the gate electrode resistance of IGBT and gate pole electric capacity are electrically connected by wiring with first pin 10.Part in IGBT and the fast recovery diode is electrically connected by wiring with second pin 40, the another part in IGBT and the fast recovery diode and second pin 40 weld by pad, specifically need which type of electric connection mode, the user can decide according to the encapsulation of actual chips; The part signal of telecommunication in this IGBT and the fast recovery diode carries out signal by second pin 40 with the outside of resin-encapsulated housing and is electrically connected.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.

Claims (10)

1. the encapsulating structure of a power semiconductor is characterized in that, comprising:
Insulated substrate with conducting wire, described insulated substrate has first surface, loads first semiconductor chip on the described first surface;
Second substrate, described second substrate has second surface, and described second surface loads second semiconductor chip;
First pin is electrically connected with described first semiconductor chip;
Second pin is electrically connected with described second semiconductor chip;
Described insulated substrate, first semiconductor chip, second substrate, second semiconductor chip, the part of first pin and the part of second pin with conducting wire is sealed in the resin.
2. the encapsulating structure of power semiconductor according to claim 1 is characterized in that, described insulated substrate with conducting wire further comprises printed circuit board (PCB).
3. the encapsulating structure of power semiconductor according to claim 1 is characterized in that, described second substrate is a ceramic substrate.
4. the encapsulating structure of power semiconductor according to claim 3 is characterized in that, described ceramic substrate second surface facing surfaces is coated with heat dissipating layer.
5. the encapsulating structure of power semiconductor according to claim 4 is characterized in that, described heat dissipating layer is the copper layer.
6. the encapsulating structure of power semiconductor according to claim 1 is characterized in that, described second substrate is the lead frame that is coated with insulating barrier.
7. the encapsulating structure of power semiconductor according to claim 1 is characterized in that, described first semiconductor chip and second semiconductor chip are electrically connected.
8. the encapsulating structure of power semiconductor according to claim 7 is characterized in that, described first semiconductor chip and second semiconductor chip are electrically connected by wiring.
9. the encapsulating structure of power semiconductor according to claim 1 is characterized in that, described second semiconductor chip is IGBT and fast recovery diode.
10. the encapsulating structure of power semiconductor according to claim 1 is characterized in that, described first semiconductor chip comprises the chip for driving of IGBT.
CN2010206889539U 2010-12-30 2010-12-30 Packaging structure for power semiconductors Expired - Lifetime CN201946588U (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103313527A (en) * 2012-03-13 2013-09-18 无锡华润安盛科技有限公司 Furnace-through fixture for reflow soldering
CN103887257A (en) * 2012-12-20 2014-06-25 浙江大学 Low parasitic inductance power electronic module packaging structure
CN103954804A (en) * 2014-04-10 2014-07-30 中国科学院电工研究所 Copper clad ceramic substrate used for testing of power semiconductor chips
CN104052244A (en) * 2013-03-14 2014-09-17 珠海格力电器股份有限公司 Power module
CN110783315A (en) * 2018-07-25 2020-02-11 英飞凌科技股份有限公司 Semiconductor package having electromagnetic shielding structure and method of manufacturing the same
CN116581110A (en) * 2023-05-16 2023-08-11 深圳市盛元半导体有限公司 Full-bridge power module based on gallium nitride chip packaging

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103313527A (en) * 2012-03-13 2013-09-18 无锡华润安盛科技有限公司 Furnace-through fixture for reflow soldering
CN103313527B (en) * 2012-03-13 2016-08-03 无锡华润安盛科技有限公司 A kind of furnace tool excessively for reflow soldering
CN103887257A (en) * 2012-12-20 2014-06-25 浙江大学 Low parasitic inductance power electronic module packaging structure
CN104052244A (en) * 2013-03-14 2014-09-17 珠海格力电器股份有限公司 Power module
CN104052244B (en) * 2013-03-14 2019-12-13 珠海格力电器股份有限公司 Power module
CN103954804A (en) * 2014-04-10 2014-07-30 中国科学院电工研究所 Copper clad ceramic substrate used for testing of power semiconductor chips
CN103954804B (en) * 2014-04-10 2016-08-24 中国科学院电工研究所 A kind of power semiconductor chip is tested with covering copper ceramic substrate
CN110783315A (en) * 2018-07-25 2020-02-11 英飞凌科技股份有限公司 Semiconductor package having electromagnetic shielding structure and method of manufacturing the same
CN116581110A (en) * 2023-05-16 2023-08-11 深圳市盛元半导体有限公司 Full-bridge power module based on gallium nitride chip packaging
CN116581110B (en) * 2023-05-16 2024-05-10 深圳市盛元半导体有限公司 Full-bridge power module based on gallium nitride chip packaging

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Granted publication date: 20110824

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