CN207637783U - Substrate for high-power semiconductor packaging and semiconductor packaging structure - Google Patents
Substrate for high-power semiconductor packaging and semiconductor packaging structure Download PDFInfo
- Publication number
- CN207637783U CN207637783U CN201721738604.1U CN201721738604U CN207637783U CN 207637783 U CN207637783 U CN 207637783U CN 201721738604 U CN201721738604 U CN 201721738604U CN 207637783 U CN207637783 U CN 207637783U
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- substrate
- wiring layer
- layer
- power semiconductor
- metal wiring
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5366—Shapes of wire connectors the bond wires having kinks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a base plate and semiconductor package structure for high power semiconductor package, wherein, base plate for high power semiconductor package includes the graphite layer and is used for installing the metal wiring layer of chip, and metal wiring layer passes through the insulating binder to be fixed in one side on graphite layer. The utility model discloses an insulating binder bonds the graphite layer and fixes in the below of metal wiring layer, can make between graphite layer and the metal wiring layer electrical insulation and stable connection to make the graphite layer stably absorb the heat that the chip that sets up on the metal wiring layer produced. The utility model discloses a high power semiconductor packaging structure has good heat dispersion, avoids the high heat flux density in the high power semiconductor packaging structure too high and leads to adopting this high power semiconductor packaging structure's equipment to break down.
Description
Technical Field
The utility model relates to a semiconductor technology, concretely relates to high power semiconductor encapsulation is with base plate and contain the semiconductor packaging structure of this high power semiconductor encapsulation with base plate.
Background
With the rapid development of integrated circuits, especially very large scale integrated circuits, the size of the high power semiconductor package structure is smaller and smaller, and at the same time, the power of the chip in the high power semiconductor package structure is larger and larger, so that the heat flux density (i.e. the heat passing through per unit time in a cross section of a unit area) in the high power semiconductor package structure is increased. As the heat flux density continues to increase, failure to effectively thermally design and thermally manage can easily result in the chip or system being improperly used due to excessive temperatures. The problem of heat generation has been identified as one of three major problems faced in the design of high power semiconductor structures. Meanwhile, heat dissipation of the chip is important. The substrate is used as a carrier of the chip, and the heat generated by the chip when the chip is subjected to a large current needs to be absorbed and dissipated. Therefore, the heat conduction capability of the substrate is important.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a high power semiconductor packaging substrate and semiconductor packaging structure that heat dispersion is good.
To achieve the purpose, the utility model adopts the following technical proposal:
in one aspect, the substrate for high-power semiconductor packaging comprises a graphite layer and a metal wiring layer for mounting a chip, wherein the metal wiring layer is fixed on one side of the graphite layer through an insulating adhesive.
As a preferable scheme of the substrate for high-power semiconductor packaging, a metal heat dissipation layer is arranged on one side of the graphite layer, which is far away from the metal wiring layer.
As a preferable mode of the substrate for high-power semiconductor packaging, the metal heat dissipation layer is fixed on the graphite layer by an adhesive.
As a preferable mode of the substrate for high power semiconductor package, the insulating adhesive is an epoxy resin material having thermal conductivity.
As a preferable scheme of the substrate for high-power semiconductor packaging, the graphite layer is composed of a plurality of graphite blocks attached to the metal wiring layer, and the graphite blocks correspond to the positions, used for mounting the chips, on the metal wiring layer; or,
the graphite block corresponds to a position on the metal wiring layer for mounting the chip with relatively high power.
As a preferable scheme of the substrate for high-power semiconductor packaging, the coverage area of the graphite block on the metal wiring layer is equal to the coverage area of the corresponding chip on the metal wiring layer.
As a preferred scheme of the substrate for high-power semiconductor packaging, the metal heat dissipation layer is composed of a plurality of metal heat dissipation blocks attached to the graphite layer, and the metal heat dissipation blocks correspond to the positions, used for mounting the chips, on the metal wiring layer; or,
the metal heat dissipation block corresponds to a position on the metal wiring layer for mounting the chip with relatively large power.
As a preferable scheme of the substrate for high-power semiconductor packaging, the coverage area of the metal heat dissipation block on the graphite layer is equal to the coverage area of the corresponding chip on the metal wiring layer.
In another aspect, a semiconductor package structure is provided, which includes a substrate, a chip and a metal terminal, wherein the chip and the metal terminal are disposed on the substrate, and the chip is connected to the metal terminal through a metal wire, and the substrate is the substrate for high power semiconductor package.
As a preferable mode of the semiconductor package structure, the chip and the metal terminal are respectively bonded to the metal wiring layer of the substrate by a conductive adhesive material.
The utility model has the advantages that: the utility model discloses an insulating binder bonds graphite layer and fixes the below at metal wiring layer, can make between graphite layer and the metal wiring layer electrical insulation and stable connection, makes the graphite layer stably absorb the heat that the chip that sets up on the metal wiring layer produced, makes high power semiconductor packaging structure have good heat dispersion, avoids the high heat flux density in the high power semiconductor packaging structure too high and leads to adopting the equipment of this high power semiconductor packaging structure to break down.
Drawings
Fig. 1 is a cross-sectional view of a high power semiconductor package substrate according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view of a high power semiconductor package substrate according to another embodiment of the present invention.
Fig. 3 is a cross-sectional view of a semiconductor package structure according to an embodiment of the present invention.
Fig. 4 is a cross-sectional view of a semiconductor package structure according to another embodiment of the present invention.
In the figure:
1. a graphite layer; 2. a metal wiring layer; 3. an insulating binder; 4. a metal heat dissipation layer; 5. an adhesive;
10. a substrate; 11. a metal wiring layer; 20. a chip; 30. a metal terminal; 40. a metal wire.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
In the description of the present invention, it is to be understood that the terms "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the term "fixed" is to be understood in a broad sense, e.g., as either a fixed connection or a removable connection, or as an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the word "over" a first feature or feature in a second feature may include the word "over" or "over" the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under" a second feature may include a first feature that is directly under and obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In an embodiment of the present invention, as shown in fig. 1, the substrate for high power semiconductor package includes a graphite layer 1 and a metal wiring layer 2 for mounting a chip, and the metal wiring layer 2 is fixed on one side of the graphite layer 1 by an insulating adhesive 3. For a high-power semiconductor, the power of a chip mounted on the metal wiring layer 2 is generally high, and the heat generated in the working process is high, in this embodiment, the graphite layer 1 is bonded and fixed below the metal wiring layer 2 by using the insulating adhesive 3, so that the graphite layer 1 and the metal wiring layer 2 can be electrically insulated and stably connected, the graphite layer 1 can stably absorb the heat generated by the chip arranged on the metal wiring layer 2, and the problem that the equipment adopting the high-power semiconductor packaging structure fails due to the excessively high heat flux density in the high-power semiconductor packaging structure is avoided.
In this embodiment, the graphite layer 1 has good unidirectional thermal conductivity along the X-Y axis of the graphite crystal, so that the substrate for high power semiconductor package has good heat dissipation performance.
Alternatively, the insulating adhesive 3 is an epoxy resin material with thermal conductivity, so that heat generated by the chip can be smoothly transferred to the graphite layer 1 through the insulating adhesive 3, and the heat can be diffused out through the graphite layer 1.
In another embodiment of the present invention, as shown in fig. 3, one side of the graphite layer 1 away from the metal wiring layer 2 is further provided with a metal heat dissipation layer 4, and the heat absorbed by the graphite layer 1 can be diffused out through the metal heat dissipation layer 4, so as to avoid the heat from being accumulated on the graphite layer 1 and affecting the normal operation of the chip.
Specifically, the metal heat dissipation layer 4 is fixed on the graphite layer 1 through the adhesive 5, so that the metal heat dissipation layer 4 is stably fixed below the graphite layer 1.
In other embodiments of the present invention, the metal heat dissipation layer 4 has a groove, and the graphite layer 1 is located in the groove, so that the substrate for packaging a high power semiconductor can be further improved to have good heat dissipation performance.
The utility model discloses an in preferred embodiment, graphite layer 1 comprises a plurality of attached graphite blocks on metal wiring layer 2, and the position that is used for installing the chip on graphite block and the metal wiring layer 2 is corresponding, can save graphite layer 1's material on the basis that guarantees that the chip has good radiating effect to reduce the manufacturing cost of high power semiconductor encapsulation substrate.
Furthermore, the graphite block corresponds to the position of the metal wiring layer 2 for mounting a chip with relatively high power, that is, the graphite block only dissipates heat of the high-power chip, so that the material of the graphite layer 1 can be further saved.
The coverage area of the graphite block on the metal wiring layer 2 is equal to the coverage area of the corresponding chip on the metal wiring layer 2, so that the material consumption of the graphite layer 1 is reduced as much as possible, and the material cost of the substrate for high-power semiconductor packaging is reduced.
In another preferred embodiment of the present invention, the metal heat dissipation layer 4 is composed of a plurality of metal heat dissipation blocks attached to the graphite layer 1 (not shown in the figure), and the position of the chip on the metal heat dissipation block and the metal wiring layer 2 corresponds to each other, so that the material of the metal heat dissipation layer 4 can be saved on the basis of ensuring the heat transfer on the graphite layer 1 to the metal heat dissipation layer 4.
Furthermore, the metal heat dissipation block corresponds to the position on the metal wiring layer 2 for mounting the chip with relatively high power, that is, the metal heat dissipation block is only arranged for the chip with relatively high power, so that the normal work of the chip can be prevented from being influenced by overheating of the chip, and the material cost of the substrate for high-power semiconductor packaging can be further reduced. The arrangement position of the metal heat dissipation block can be combined with the arrangement position of the graphite layer 1 in any embodiment, so that the material cost of the high-power semiconductor packaging substrate can be further reduced on the basis of ensuring the heat dissipation effect of the high-power semiconductor packaging substrate.
Optionally, the area covered by the metal heat slug on the graphite layer 1 is equal to the area covered by the corresponding chip on the metal wiring layer 2.
As shown in fig. 3 and 4, the embodiment of the present invention further provides a semiconductor package structure, which includes a substrate 10, a chip 20 and a metal terminal 30, wherein the chip 20 and the metal terminal 30 are all disposed on the substrate 10, the chip 20 is connected to the metal terminal 30 through a metal wire 40, and the substrate 10 is the substrate for high power semiconductor package of any of the above embodiments. The heat generated by the chip 20 in the semiconductor package structure can be diffused out through the substrate 10, so that the influence of the excessive heat flux density in the semiconductor package structure on the normal use of the semiconductor package structure can be avoided.
Wherein the chip 20 and the metal terminal 30 are respectively adhered to the metal wiring layer 11 of the substrate 10 by a conductive adhesive material.
The semiconductor package structure of the present embodiment further includes an injection molding package (not shown), in which the chip 20, the metal wires 40 and a portion of the metal terminals 30 are packaged.
It should be noted that the above embodiments are only preferred embodiments of the present invention and the technical principles applied, and any changes or substitutions which can be easily conceived by those skilled in the art within the technical scope of the present invention are covered by the protection scope of the present invention.
The present invention has been described above with reference to specific embodiments, but the present invention is not limited to these specific embodiments. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description. In addition, the above embodiments "one embodiment", "another embodiment", and the like represent different embodiments, and all or part of them may be combined into one embodiment.
Claims (10)
1. The substrate for the high-power semiconductor package is characterized by comprising a graphite layer and a metal wiring layer for mounting a chip, wherein the metal wiring layer is fixed on one side of the graphite layer through an insulating adhesive.
2. The substrate for high power semiconductor package according to claim 1, wherein a side of the graphite layer remote from the metal wiring layer is provided with a metal heat dissipation layer.
3. The substrate for high power semiconductor package according to claim 2, wherein the metal heat dissipation layer is fixed to the graphite layer by an adhesive.
4. The substrate for high power semiconductor package according to claim 1, wherein the insulating adhesive is an epoxy material having thermal conductivity.
5. The substrate for high power semiconductor package according to claim 1, wherein the graphite layer is composed of a plurality of graphite blocks attached to the metal wiring layer, the graphite blocks corresponding to positions on the metal wiring layer for mounting the chips; or,
the graphite block corresponds to a position on the metal wiring layer for mounting the chip with relatively high power.
6. The substrate for high power semiconductor package according to claim 5, wherein a coverage area of the graphite block on the metal wiring layer is equal to a coverage area of the corresponding chip on the metal wiring layer.
7. The substrate for high power semiconductor package according to any one of claims 2 to 5, wherein the metal heat dissipation layer is composed of a plurality of metal heat dissipation blocks attached to the graphite layer, and the metal heat dissipation blocks correspond to the positions on the metal wiring layer for mounting the chip; or,
the metal heat dissipation block corresponds to a position on the metal wiring layer for mounting the chip with relatively large power.
8. The substrate for high power semiconductor package according to claim 7, wherein a coverage area of the metal heat slug on the graphite layer is equal to a coverage area of the corresponding chip on the metal wiring layer.
9. A semiconductor packaging structure, comprising a substrate, a chip and a metal terminal, wherein the chip and the metal terminal are arranged on the substrate, and the chip is connected with the metal terminal through a metal wire, characterized in that the substrate is the substrate for high-power semiconductor packaging according to any one of claims 1 to 8.
10. The semiconductor package structure according to claim 9, wherein the chip and the metal terminal are respectively bonded to the metal wiring layer of the substrate by a conductive adhesive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721738604.1U CN207637783U (en) | 2017-12-12 | 2017-12-12 | Substrate for high-power semiconductor packaging and semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721738604.1U CN207637783U (en) | 2017-12-12 | 2017-12-12 | Substrate for high-power semiconductor packaging and semiconductor packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN207637783U true CN207637783U (en) | 2018-07-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201721738604.1U Active CN207637783U (en) | 2017-12-12 | 2017-12-12 | Substrate for high-power semiconductor packaging and semiconductor packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112263A (en) * | 2019-05-13 | 2019-08-09 | 电子科技大学中山学院 | Substrate for high-power LED packaging, substrate manufacturing method and packaging structure |
| CN113410191A (en) * | 2020-03-17 | 2021-09-17 | 三菱电机株式会社 | Mounting structure of power semiconductor module |
-
2017
- 2017-12-12 CN CN201721738604.1U patent/CN207637783U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112263A (en) * | 2019-05-13 | 2019-08-09 | 电子科技大学中山学院 | Substrate for high-power LED packaging, substrate manufacturing method and packaging structure |
| CN113410191A (en) * | 2020-03-17 | 2021-09-17 | 三菱电机株式会社 | Mounting structure of power semiconductor module |
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