CN207637783U - A kind of high power semiconductor base plate for packaging and semiconductor package - Google Patents
A kind of high power semiconductor base plate for packaging and semiconductor package Download PDFInfo
- Publication number
- CN207637783U CN207637783U CN201721738604.1U CN201721738604U CN207637783U CN 207637783 U CN207637783 U CN 207637783U CN 201721738604 U CN201721738604 U CN 201721738604U CN 207637783 U CN207637783 U CN 207637783U
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- Prior art keywords
- wiring layer
- chip
- high power
- power semiconductor
- metal wiring
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of high power semiconductor base plate for packaging and semiconductor package, wherein, high power semiconductor base plate for packaging includes graphite linings and the metal wiring layer for chip, and metal wiring layer is fixed on the side of graphite linings by insulating adhesive.Graphite linings are adhesively fixed on the lower section of metal wiring layer using insulating adhesive by the utility model, can make to be electrically insulated and be stably connected between graphite linings and metal wiring layer, the heat generated to the chip for making graphite linings stable absorption be arranged on metal wiring layer.The high power semiconductor encapsulating structure of the utility model has good heat dissipation performance, avoids the heat flow density in high power semiconductor encapsulating structure excessively high and leads to the device fails using the high power semiconductor encapsulating structure.
Description
Technical field
The utility model is related to semiconductor technologies, and in particular to a kind of high power semiconductor base plate for packaging and include the height
The semiconductor package of power semiconductor package substrate.
Background technology
With the rapid development of integrated circuit especially super large-scale integration, the body of high power semiconductor encapsulating structure
Product is smaller and smaller, and at the same time, the power of the chip in high power semiconductor encapsulating structure is increasing, so as to cause Gao Gong
Heat flow density (i.e. in the section of unit area unit interval by heat) in rate semiconductor package increasingly improves.With
The continuous improvement for heat flow density, easily lead to if it cannot carry out effectively thermal design and heat management chip or system by
It is excessively high in temperature and be unable to normal use.Heating problem has been confirmed to be high power semiconductor structure design is faced three and has asked greatly
One of topic.At the same time, the heat dissipation of chip is particularly important.And supporting body of the substrate as chip, it needs chip because holding
The heat absorption that is generated by high current simultaneously distributes.Therefore, the capacity of heat transmission of substrate is particularly important.
Utility model content
The purpose of this utility model is to provide a kind of good high power semiconductor base plate for packaging of heat dissipation performance and half
Conductor package structure.
For this purpose, the utility model uses following technical scheme：
On the one hand, a kind of high power semiconductor base plate for packaging, including graphite linings and the metal for chip are provided
Wiring layer, the metal wiring layer are fixed on the side of the graphite linings by insulating adhesive.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the graphite linings are far from the metal wiring layer
Side be provided with metallic radiating layer.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the metallic radiating layer is fixed by adhesive
In the graphite linings.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the insulating adhesive is with thermal conductivity
Epoxide resin material.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the graphite linings are attached to the gold by several
Belong to the graphite block composition on wiring layer, the graphite block is opposite for installing the position of the chip on the metal wiring layer
It answers；Alternatively,
The graphite block is opposite with the relatively large position of the chip of installation power is used on the metal wiring layer
It answers.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the graphite block is on the metal wiring layer
Area coverage be equal to corresponding area coverage of the chip on the metal wiring layer.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the metallic radiating layer is attached to institute by several
The metal heat-dissipation block composition in graphite linings is stated, in the metal heat-dissipation block and the metal wiring layer is used to that the chip to be installed
Position is corresponding；Alternatively,
The metal heat-dissipation block and the position that the relatively large chip of installation power is used on the metal wiring layer
It is corresponding.
As a kind of preferred embodiment of high power semiconductor base plate for packaging, the metal heat-dissipation block is in the graphite linings
Area coverage be equal to corresponding area coverage of the chip on the metal wiring layer.
On the other hand, a kind of semiconductor package, including substrate, chip and metal terminal, the chip and institute are provided
State metal terminal setting on the substrate, the chip is connect by plain conductor with the metal terminal, wherein the base
Plate is the high power semiconductor base plate for packaging.
As a kind of preferred embodiment of semiconductor package, the chip and the metal terminal are viscous by conduction respectively
Condensation material is bonded on the metal wiring layer of the substrate.
The beneficial effects of the utility model：Graphite linings are adhesively fixed on hardware cloth by the utility model using insulating adhesive
The lower section of line layer can make to be electrically insulated and be stably connected between graphite linings and metal wiring layer, and graphite linings stable absorption is made to be arranged
The heat that chip on metal wiring layer generates, makes high power semiconductor encapsulating structure have good heat dissipation performance, avoids
Heat flow density in high power semiconductor encapsulating structure is excessively high and causes to send out using the equipment of the high power semiconductor encapsulating structure
Raw failure.
Description of the drawings
Fig. 1 is the sectional view of the high power semiconductor base plate for packaging of one embodiment of the utility model.
Fig. 2 is the sectional view of the high power semiconductor base plate for packaging of another embodiment of the utility model.
Fig. 3 is the sectional view of the semiconductor package of one embodiment of the utility model.
Fig. 4 is the sectional view of the semiconductor package of another embodiment of the utility model.
In figure：
1, graphite linings；2, metal wiring layer；3, insulating adhesive；4, metallic radiating layer；5, adhesive；
10, substrate；11, metal wiring layer；20, chip；30, metal terminal；40, plain conductor.
Specific implementation mode
Further illustrate the technical solution of the utility model below with reference to the accompanying drawings and specific embodiments.
In the description of the present invention, it should be understood that the orientation or positional relationship of the instructions such as term "inner", "outside"
To be based on the orientation or positional relationship shown in the drawings, it is merely for convenience of describing the present invention and simplifying the description, without referring to
Show or imply that signified device or element must have a particular orientation, with specific azimuth configuration and operation, therefore cannot manage
Solution is limitations of the present invention.
In the description of the present invention, unless otherwise clearly defined and limited, term " fixation " shall be understood in a broad sense,
For example, it may be being fixedly connected, it may be a detachable connection, or integral；It can be mechanical connection, can also be to be electrically connected
It connects；Can be directly connected, can also indirectly connected through an intermediary, can be two components interiors connection or two portions
The interaction relationship of part.For the ordinary skill in the art, above-mentioned term can be understood in this reality with concrete condition
With the concrete meaning in novel.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features are in direct contact, and can also not be to be in direct contact but lead to including the first and second features
Cross the other characterisation contact between them.Moreover, fisrt feature includes that fisrt feature is special second in the "upper" of second feature
Right over sign and oblique upper, or be merely representative of fisrt feature level height and be higher than second feature.Fisrt feature second feature it
"lower" includes fisrt feature immediately below second feature and obliquely downward, or to be merely representative of fisrt feature level height special less than second
Sign.
In an embodiment of the utility model, as shown in Figure 1, high power semiconductor base plate for packaging includes graphite linings 1
With the metal wiring layer 2 for chip, metal wiring layer 2 is fixed on the side of graphite linings 1 by insulating adhesive 3.It is right
For high power semiconductor, the power for being mounted on the chip on the metal wiring layer 2 is usually larger, is generated in the course of work
Heat is larger, and graphite linings 1 are adhesively fixed on the lower section of metal wiring layer 2 using insulating adhesive 3 by the present embodiment, can make stone
It is electrically insulated and is stably connected between layer of ink 1 and metal wiring layer 2,1 stable absorption of graphite linings is made to be arranged on metal wiring layer 2
The heat that chip generates, is avoided the heat flow density in high power semiconductor encapsulating structure excessively high and causes partly to be led using the high power
The device fails of body encapsulating structure.
In the present embodiment, graphite linings 1 have the good unidirectional heat conductivity along its graphite crystal X-Y axial directions, to make
High power semiconductor base plate for packaging has good heat dissipation performance.
Optionally, insulating adhesive 3 is the epoxide resin material with thermal conductivity, and the heat that chip generates can be made to pass through
Insulating adhesive 3 is smoothly transferred in graphite linings 1, and heat diffusion is gone out by graphite linings 1.
In another embodiment of the utility model, as shown in figure 3, side of the graphite linings 1 far from metal wiring layer 2 is also set up
There is metallic radiating layer 4, the heat diffusion that graphite linings 1 absorb can be gone out by metallic radiating layer 4, heat is avoided to be gathered in stone
Chip normal work is influenced in layer of ink 1.
Specifically, metallic radiating layer 4 is fixed on by adhesive 5 in graphite linings 1, is ensured that metallic radiating layer 4 is stablized and is fixed
Below graphite linings 1.
In the other embodiment of the utility model, there is metallic radiating layer 4 groove, graphite linings 1 to be located in the groove,
High power semiconductor base plate for packaging, which can be further increased, has good heat dissipation performance.
In one preferred embodiment of the utility model, graphite linings 1 are by several graphite blocks being attached on metal wiring layer 2
Composition, graphite block is corresponding with the position of chip is used on metal wiring layer 2, is ensureing chip with great heat radiation effect
On the basis of can save the materials of graphite linings 1, to reduce the production cost of high power semiconductor base plate for packaging.
Further, graphite block is corresponding with the position of the relatively large chip of installation power is used on metal wiring layer 2,
I.e. graphite block only radiates to high-power chip, therefore can further save the materials of graphite linings 1.
Wherein, area coverage of the graphite block on metal wiring layer 2 is equal to corresponding chip covering on metal wiring layer 2
Capping accumulates, and to be reduced as far as the materials of graphite linings 1, reduces the materials cost of high power semiconductor base plate for packaging.
In another preferred embodiment of the utility model, metallic radiating layer 4 is by several metals being attached in graphite linings 1
Radiating block forms (not shown), and metal heat-dissipation block is corresponding with the position of chip is used on metal wiring layer 2, is protecting
The materials of metallic radiating layer 4 can be saved on the basis of heat transfer to metallic radiating layer 4 in card graphite linings 1.
Further, metal heat-dissipation block and the position phase that the relatively large chip of installation power is used on metal wiring layer 2
It is corresponding, i.e., metal heat-dissipation block is set only for power larger chip, had not only been avoided that chip overheating influenced its normal work, but also energy
Further decrease the materials cost of high power semiconductor base plate for packaging.The position of the metal heat-dissipation block can be with above-mentioned
The position of graphite linings 1 in one embodiment is combined, in the heat dissipation effect for ensureing high power semiconductor base plate for packaging
On the basis of can further decrease its materials cost.
Optionally, area coverage of the metal heat-dissipation block in graphite linings 1 is equal to corresponding chip on metal wiring layer 2
Area coverage.
As shown in Figure 3 and Figure 4, the embodiments of the present invention also provide a kind of semiconductor package, the semiconductor package
Assembling structure includes substrate 10, chip 20 and metal terminal 30, and chip 20 and metal terminal 30 are respectively provided on the substrate 10, chip 20
It is connect with metal terminal 30 by plain conductor 40, wherein substrate 10 is that the high power semiconductor of any of the above-described embodiment encapsulates
Use substrate.The heat that the semiconductor package chips 20 generate can be spread out by substrate 10, so as to avoid
Heat flow density in semiconductor package is excessive and influences its normal use.
Wherein, chip 20 and metal terminal 30 are bonded in the metal wiring layer 11 of substrate 10 by conductive bonding material respectively
On.
The semiconductor package of the present embodiment further includes injection molding packaging body (not shown), chip 20, plain conductor
40 and part metals terminal 30 be packaged in the injection molding packaging body.
It is to be understood that above-mentioned specific implementation mode is only the preferred embodiment and institute's application technology of the utility model
Principle, in technical scope disclosed in the utility model, what any one skilled in the art was readily apparent that
Change or replacement should all be covered within the protection scope of the present utility model.
The utility model is illustrated above by specific embodiment, but the utility model is not limited to these tools
The embodiment of body.It will be understood by those skilled in the art that various modifications, equivalent replacement, variation can also be done to the utility model
Etc..But these transformation should be all within the protection scope of the utility model without departing from the spirit of the utility model.
In addition, some terms used in present specification and claims are not limitation, it is only for convenient for description.This
Outside, " one embodiment " of the above many places, " another embodiment " etc. indicate different embodiments, naturally it is also possible to by its whole
Or part combines in one embodiment.
Claims (10)
1. a kind of high power semiconductor base plate for packaging, which is characterized in that the hardware cloth including graphite linings and for chip
Line layer, the metal wiring layer are fixed on the side of the graphite linings by insulating adhesive.
2. high power semiconductor base plate for packaging according to claim 1, which is characterized in that the graphite linings are far from described
The side of metal wiring layer is provided with metallic radiating layer.
3. high power semiconductor base plate for packaging according to claim 2, which is characterized in that the metallic radiating layer passes through
Adhesive is fixed in the graphite linings.
4. high power semiconductor base plate for packaging according to claim 1, which is characterized in that the insulating adhesive is tool
There is the epoxide resin material of thermal conductivity.
5. high power semiconductor base plate for packaging according to claim 1, which is characterized in that if the graphite linings are by dry doubling
The graphite block being attached on the metal wiring layer forms, for installing the chip on the graphite block and the metal wiring layer
Position it is corresponding；Alternatively,
The graphite block is corresponding with the relatively large position of the chip of installation power is used on the metal wiring layer.
6. high power semiconductor base plate for packaging according to claim 5, which is characterized in that the graphite block is in the gold
Belong to the area coverage on wiring layer and is equal to corresponding area coverage of the chip on the metal wiring layer.
7. according to claim 2 to 5 any one of them high power semiconductor base plate for packaging, which is characterized in that the metal
Heat dissipating layer is made of several metal heat-dissipation blocks being attached in the graphite linings, the metal heat-dissipation block and the metal wiring layer
On it is corresponding for installing the position of the chip；Alternatively,
The metal heat-dissipation block is opposite with the relatively large position of the chip of installation power is used on the metal wiring layer
It answers.
8. high power semiconductor base plate for packaging according to claim 7, which is characterized in that the metal heat-dissipation block is in institute
It states the area coverage in graphite linings and is equal to corresponding area coverage of the chip on the metal wiring layer.
9. a kind of semiconductor package, including substrate, chip and metal terminal, the chip and metal terminal setting exist
On the substrate, the chip is connect by plain conductor with the metal terminal, which is characterized in that the substrate is wanted for right
Seek 1 to 8 any one of them high power semiconductor base plate for packaging.
10. semiconductor package according to claim 9, which is characterized in that the chip and the metal terminal point
It is not bonded on the metal wiring layer of the substrate by conductive bonding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721738604.1U CN207637783U (en) | 2017-12-12 | 2017-12-12 | A kind of high power semiconductor base plate for packaging and semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721738604.1U CN207637783U (en) | 2017-12-12 | 2017-12-12 | A kind of high power semiconductor base plate for packaging and semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207637783U true CN207637783U (en) | 2018-07-20 |
Family
ID=62863239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721738604.1U Active CN207637783U (en) | 2017-12-12 | 2017-12-12 | A kind of high power semiconductor base plate for packaging and semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207637783U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112263A (en) * | 2019-05-13 | 2019-08-09 | 电子科技大学中山学院 | Substrate for high-power LED packaging, substrate manufacturing method and packaging structure |
-
2017
- 2017-12-12 CN CN201721738604.1U patent/CN207637783U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112263A (en) * | 2019-05-13 | 2019-08-09 | 电子科技大学中山学院 | Substrate for high-power LED packaging, substrate manufacturing method and packaging structure |
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