CN207719180U - A kind of power semiconductor package substrate and semiconductor package - Google Patents

A kind of power semiconductor package substrate and semiconductor package Download PDF

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Publication number
CN207719180U
CN207719180U CN201721738691.0U CN201721738691U CN207719180U CN 207719180 U CN207719180 U CN 207719180U CN 201721738691 U CN201721738691 U CN 201721738691U CN 207719180 U CN207719180 U CN 207719180U
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China
Prior art keywords
semiconductor package
heat dissipating
dissipating layer
power semiconductor
chip
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Application number
CN201721738691.0U
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Chinese (zh)
Inventor
江汉
江一汉
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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Priority to CN201721738691.0U priority Critical patent/CN207719180U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model discloses a kind of power semiconductor package substrate and semiconductor package, wherein, power semiconductor package substrate includes heat dissipating layer and integral lead wire frame, integral lead wire frame is bonded in the one side of heat dissipating layer by insulating adhesive, integral lead wire frame includes the frame body for chip and the lead terminal that is connect with the periphery of frame body, and lead terminal extends partially into the edge for protruding from heat dissipating layer.Heat dissipating layer is adhesively fixed on the lower section of integral lead wire frame using insulating adhesive by the utility model, it can make to be electrically insulated and be stably connected between heat dissipating layer and integral lead wire frame, the heat diffusion that the chip being arranged on integral lead wire frame generates is gone out using heat dissipating layer, avoids the heat flow density in semiconductor package excessively high and leads to the device fails using the semiconductor package.The production cost of the power semiconductor package substrate of the utility model is low, may replace expensive ceramic substrate on the market.

Description

A kind of power semiconductor package substrate and semiconductor package
Technical field
The utility model is related to semiconductor technologies, and in particular to a kind of power semiconductor package substrate and include the power The semiconductor package of base plate for encapsulating semiconductor.
Background technology
With the rapid development of integrated circuit especially super large-scale integration, the body of high power semiconductor encapsulating structure Product is smaller and smaller, and at the same time, the power of the chip in high power semiconductor encapsulating structure is increasing, so as to cause Gao Gong Heat flow density (i.e. in the section of unit area unit interval by heat) in rate semiconductor package increasingly improves.With The continuous improvement for heat flow density, easily lead to if it cannot carry out effectively thermal design and heat management chip or system by It is excessively high in temperature and be unable to normal use.Heating problem has been confirmed to be high power semiconductor structure design is faced three and has asked greatly One of topic.At the same time, the heat dissipation of chip is particularly important.And supporting body of the substrate as chip, it needs chip because holding The heat absorption that is generated by high current simultaneously distributes.Therefore, the capacity of heat transmission of substrate is particularly important.
To solve the heat dissipation problem of high-power chip, occur a kind of ceramic substrate on the market at present, however the substrate at This height.Therefore, there is an urgent need for design a kind of good heat dissipation effect and substrate at low cost.
Utility model content
The power semiconductor package base good and at low cost the purpose of this utility model is to provide a kind of heat dissipation performance Plate and semiconductor package.
For this purpose, the utility model uses following technical scheme：
On the one hand, a kind of power semiconductor package substrate, including heat dissipating layer and integral lead wire frame be provided, described one Body formula lead frame is bonded in the one side of the heat dissipating layer by insulating adhesive, and the integral lead wire frame includes being used for The frame body of chip and the lead terminal being connect with the periphery of the frame body, the lead terminal extend partially into Protrude from the edge of the heat dissipating layer.
As a kind of preferred embodiment of power semiconductor package substrate, the heat dissipating layer is graphite material.
As a kind of preferred embodiment of power semiconductor package substrate, the heat dissipating layer is metal material.
As a kind of preferred embodiment of power semiconductor package substrate, the insulating adhesive is the ring with thermal conductivity Oxygen resin material.
As a kind of preferred embodiment of power semiconductor package substrate, the heat dissipating layer is attached to the frame by several Radiating block composition on ontology, the radiating block are corresponding for installing the position of the chip on the frame body.
As a kind of preferred embodiment of power semiconductor package substrate, the radiating block covering on the frame body Capping product is equal to corresponding area coverage of the chip on the frame body.
As a kind of preferred embodiment of power semiconductor package substrate, the heat dissipating layer is used for on the frame body The position of the relatively large chip of installation power is corresponding.
As a kind of preferred embodiment of power semiconductor package substrate, the heat dissipating layer covering on the frame body Capping product is equal to corresponding area coverage of the chip on the frame body.
On the other hand, a kind of semiconductor package is provided, including substrate and the frame sheet in the substrate is set Chip on body, the chip are connect by plain conductor with the lead terminal of the substrate, and the substrate is described Power semiconductor package substrate.
As a kind of preferred embodiment of semiconductor package, the chip is bonded in the frame by conductive bonding material On frame ontology.
The beneficial effects of the utility model：Heat dissipating layer is adhesively fixed on integral type by the utility model using insulating adhesive The lower section of lead frame can make to be electrically insulated and be stably connected between heat dissipating layer and integral lead wire frame, will using heat dissipating layer The heat diffusion that the chip being arranged on integral lead wire frame generates is gone out, and the heat flow density in semiconductor package is avoided It is excessively high and lead to the device fails using the semiconductor package.The power semiconductor package substrate of the utility model Production cost it is low, may replace expensive ceramic substrate on the market.The power semiconductor package substrate of the utility model Stable structure, and production efficiency is high.
Description of the drawings
Fig. 1 is the sectional view of the power semiconductor package substrate of the utility model embodiment.
Fig. 2 is the sectional view of the semiconductor package of the utility model embodiment.
In figure：
1, heat dissipating layer；2, integral lead wire frame；21, frame body；22, lead terminal；3, insulating adhesive；
10, substrate；20, chip；30, plain conductor.
Specific implementation mode
Further illustrate the technical solution of the utility model below with reference to the accompanying drawings and specific embodiments.
In the description of the present invention, it should be understood that the orientation or positional relationship of the instructions such as term "inner", "outside" To be based on the orientation or positional relationship shown in the drawings, it is merely for convenience of describing the present invention and simplifying the description, without referring to Show or imply that signified device or element must have a particular orientation, with specific azimuth configuration and operation, therefore cannot manage Solution is limitations of the present invention.
In the description of the present invention, unless otherwise clearly defined and limited, term " fixation " shall be understood in a broad sense, For example, it may be being fixedly connected, it may be a detachable connection, or integral；It can be mechanical connection, can also be to be electrically connected It connects；Can be directly connected, can also indirectly connected through an intermediary, can be two components interiors connection or two portions The interaction relationship of part.For the ordinary skill in the art, above-mentioned term can be understood in this reality with concrete condition With the concrete meaning in novel.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it "lower" may include that the first and second features are in direct contact, and can also not be to be in direct contact but lead to including the first and second features Cross the other characterisation contact between them.Moreover, fisrt feature includes that fisrt feature is special second in the "upper" of second feature Right over sign and oblique upper, or be merely representative of fisrt feature level height and be higher than second feature.Fisrt feature second feature it "lower" includes fisrt feature immediately below second feature and obliquely downward, or to be merely representative of fisrt feature level height special less than second Sign.
In an embodiment of the utility model, as shown in Figure 1, power semiconductor package substrate includes 1 He of heat dissipating layer Integral lead wire frame 2, integral lead wire frame 2 are bonded in the one side of heat dissipating layer 1 by insulating adhesive 3, and integral type is drawn Wire frame 2 includes the frame body 21 for chip and the lead terminal 22 that is connect with the periphery of frame body 21, lead Terminal 22 extends partially into the edge for protruding from heat dissipating layer 1.The present embodiment can be improved by using integral lead wire frame 2 The structural stability and production efficiency of power semiconductor package substrate；For high power semiconductor, it is mounted on the frame The power of chip on ontology 21 is usually larger, and the heat generated in the course of work is larger, and the present embodiment uses insulating adhesive 3 Heat dissipating layer 1 is adhesively fixed on to the lower section of integral lead wire frame 2, can be made between heat dissipating layer 1 and integral lead wire frame 2 It is electrically insulated and is stably connected with, gone out the heat diffusion that the chip being arranged on integral lead wire frame 2 generates using heat dissipating layer 1 It goes, avoids the heat flow density in semiconductor package excessively high and lead to that event occurs using the equipment of the semiconductor package Barrier.The production cost of the power semiconductor package substrate of the present embodiment is low, may replace expensive ceramic substrate on the market.
Wherein, heat dissipating layer 1 is graphite material, and graphite material has the good unidirectional heat along its graphite crystal X-Y axial directions Conductibility, to make power semiconductor package substrate that there is good heat dissipation performance.
In another embodiment of the utility model, heat dissipating layer 1 is metal material, such as aluminium sheet, iron plate, copper coin, stainless Steel plate etc. can equally make power semiconductor package substrate have good heat dissipation performance.
Preferably, the heat dissipating layer of the present embodiment includes graphite linings and metal layer (not shown), and graphite linings are located at metal Between layer and integral lead wire frame 2, and graphite linings are fixed on the back side of integral lead wire frame 2 by insulating adhesive 3, gold Belong to layer and side of the graphite linings far from integral lead wire frame 2 be fixed on by adhesive, the structure design by graphite linings heat conduction and Metal layer heat dissipation is combined, and can further increase the heat dissipation performance of power semiconductor package substrate.
Wherein, insulating adhesive 3 is the epoxide resin material with thermal conductivity.Epoxide resin material is coated in heat dissipating layer 1 On, then by integral lead wire frame 2 on heat dissipating layer 1, the close connection of the two is made by pressing, waits for that epoxide resin material is consolidated After change, you can make 2 strong bond of integral lead wire frame on heat dissipating layer 1.Certainly, for other insulation with thermal conductivity Adhesives is equally applicable.
In one preferred embodiment of the utility model, heat dissipating layer 1 is by several radiating blocks being attached on frame body 21 (not shown) is formed, radiating block is corresponding for the position of chip on frame body 21, is ensureing that chip has The materials of heat dissipating layer 1 can be saved on the basis of great heat radiation effect.
Wherein, area coverage of the radiating block on frame body 21 is equal to corresponding chip covering on frame body 21 Capping accumulates, to be reduced as far as the materials of heat dissipating layer 1, to reduce the materials cost of power semiconductor package substrate.
In the further preferred embodiment of the utility model, heat dissipating layer 1 on frame body 21 be used for installation power phase It is corresponding to the position of larger chip, i.e., heat dissipating layer 1 is set only for power larger chip, had both been avoided that chip overheating shadow Its normal work is rung, and the materials cost of power semiconductor package substrate can be further decreased.
Wherein, area coverage of the heat dissipating layer 1 on frame body 21 is equal to corresponding chip covering on frame body 21 Capping accumulates.
As shown in Fig. 2, the embodiments of the present invention also provide a kind of semiconductor package, including substrate 10 and setting Chip 20 on the frame body of substrate 10, chip 20 are connect by plain conductor 30 with the lead terminal on substrate 10, base Plate 10 is the power semiconductor package substrate of any of the above-described embodiment.The heat that the semiconductor package chips 20 generate It can be spread out by substrate 10, to avoid that the heat flow density in semiconductor package is excessive and influencing it normally makes With.
Wherein, chip 20 is bonded in by conductive bonding material on the frame body 12 of substrate 10.
In other embodiments, chip 20 can also be welded on by solder on frame body.
The semiconductor package of the present embodiment further includes injection molding packaging body (not shown), chip 20, plain conductor 40 and part lead terminal be packaged in the injection molding packaging body.
It is to be understood that above-mentioned specific implementation mode is only the preferred embodiment and institute's application technology of the utility model Principle, in technical scope disclosed in the utility model, what any one skilled in the art was readily apparent that Change or replacement should all be covered within the protection scope of the present utility model.
The utility model is illustrated above by specific embodiment, but the utility model is not limited to these tools The embodiment of body.It will be understood by those skilled in the art that various modifications, equivalent replacement, variation can also be done to the utility model Etc..But these transformation should be all within the protection scope of the utility model without departing from the spirit of the utility model. In addition, some terms used in present specification and claims are not limitation, it is only for convenient for description.This Outside, " one embodiment " of the above many places, " another embodiment " etc. indicate different embodiments, naturally it is also possible to by its whole Or part combines in one embodiment.

Claims (10)

1. a kind of power semiconductor package substrate, which is characterized in that including heat dissipating layer and integral lead wire frame, the one Formula lead frame is bonded in the one side of the heat dissipating layer by insulating adhesive, and the integral lead wire frame includes for pacifying The frame body of cartridge chip and the lead terminal being connect with the periphery of the frame body, the lead terminal extend partially into convex For the edge of the heat dissipating layer.
2. power semiconductor package substrate according to claim 1, which is characterized in that the heat dissipating layer is graphite material Material.
3. power semiconductor package substrate according to claim 1, which is characterized in that the heat dissipating layer is metal material Material.
4. power semiconductor package substrate according to claim 1, which is characterized in that the insulating adhesive be with The epoxide resin material of thermal conductivity.
5. power semiconductor package substrate according to claim 1, which is characterized in that the heat dissipating layer is by several attachings Radiating block composition on the frame body, the radiating block and the position for installing the chip on the frame body It is corresponding.
6. power semiconductor package substrate according to claim 5, which is characterized in that the radiating block is in the frame Area coverage on ontology is equal to corresponding area coverage of the chip on the frame body.
7. power semiconductor package substrate according to claim 1, which is characterized in that the heat dissipating layer and the frame Position on ontology for the relatively large chip of installation power is corresponding.
8. power semiconductor package substrate according to claim 7, which is characterized in that the heat dissipating layer is in the frame Area coverage on ontology is equal to corresponding area coverage of the chip on the frame body.
9. a kind of semiconductor package, including substrate and the chip that is arranged on the frame body of the substrate, it is described Chip is connect by plain conductor with the lead terminal of the substrate, which is characterized in that the substrate be claim 1 to 8 any one of them power semiconductor package substrates.
10. semiconductor package according to claim 9, which is characterized in that the chip passes through conductive bonding material It is bonded on the frame body.
CN201721738691.0U 2017-12-12 2017-12-12 A kind of power semiconductor package substrate and semiconductor package Active CN207719180U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201721738691.0U CN207719180U (en) 2017-12-12 2017-12-12 A kind of power semiconductor package substrate and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201721738691.0U CN207719180U (en) 2017-12-12 2017-12-12 A kind of power semiconductor package substrate and semiconductor package

Publications (1)

Publication Number Publication Date
CN207719180U true CN207719180U (en) 2018-08-10

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CN201721738691.0U Active CN207719180U (en) 2017-12-12 2017-12-12 A kind of power semiconductor package substrate and semiconductor package

Country Status (1)

Country Link
CN (1) CN207719180U (en)

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