CN218299797U - Multi-chip sealed semiconductor packaging structure - Google Patents

Multi-chip sealed semiconductor packaging structure Download PDF

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Publication number
CN218299797U
CN218299797U CN202121659319.7U CN202121659319U CN218299797U CN 218299797 U CN218299797 U CN 218299797U CN 202121659319 U CN202121659319 U CN 202121659319U CN 218299797 U CN218299797 U CN 218299797U
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China
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chip
base island
pin assembly
silicon
effect transistor
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CN202121659319.7U
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Chinese (zh)
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曹周
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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Abstract

The utility model discloses a semiconductor packaging structure that multicore piece closed and sealed belongs to semiconductor packaging technical field. The multi-chip sealed semiconductor packaging structure comprises: a lead frame including a first base island, a second base island, and a third base island; the silicon-based field effect transistor chip is fixed on the first base island; a gallium nitride chip fixed to the second base island; the gallium nitride chip is electrically connected with the silicon-based field effect transistor chip; the control chip is fixed on the third base island; the control chip is electrically connected with the silicon-based field effect transistor chip; and the packaging body is used for packaging the lead frame, the silicon-based field effect transistor chip, the gallium nitride chip and the control chip. According to the multi-chip sealed semiconductor packaging structure, the gallium nitride chip, the silicon-based field effect transistor chip and the control chip are sealed to the same packaging structure, so that better performance can be realized, the packaging area is small, the packaging resistance is low, and the cost is saved.

Description

Multi-chip sealed semiconductor packaging structure
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a semiconductor packaging structure that multicore piece closed and sealed.
Background
The third generation semiconductor material has the characteristics of wider forbidden band width, higher thermal conductivity, higher radiation resistance, higher electron saturation drift rate and the like, so the third generation semiconductor is more suitable for manufacturing high-temperature, high-frequency, radiation-resistant and high-power electronic devices. The existing devices made of the third-generation semiconductor material are generally independently packaged to form a packaging structure; when the third generation semiconductor packaging structure is applied to electronic products, the third generation semiconductor packaging structure needs to be electrically connected with other independently packaged semiconductor packaging structures.
However, this results in a larger volume of the whole electronic product, which is not favorable for the miniaturization design of the electronic product; in addition, the resistance is increased, and the electrical and thermal properties of the electronic product are reduced.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an aim at: the multi-chip sealed semiconductor packaging structure is used for sealing a gallium nitride chip and other chips, can realize better performance, can reduce the packaging area, can reduce the packaging resistance and can save the cost.
In order to achieve the purpose, the utility model adopts the following technical proposal:
a multi-chip encapsulated semiconductor package structure, comprising:
a lead frame including a first base island, a second base island, and a third base island;
the silicon-based field effect transistor chip is fixed on the first base island;
a gallium nitride chip fixed to the second base island; the gallium nitride chip is electrically connected with the silicon-based field effect transistor chip;
a control chip fixed to the third base island; the control chip is electrically connected with the silicon-based field effect transistor chip;
and the packaging body is used for packaging the lead frame, the silicon-based field effect transistor chip, the gallium nitride chip and the control chip.
Preferably, the second base island and the third base island are respectively provided on two adjacent sides of the first base island.
Preferably, the first base island includes a first side portion and a second side portion which are adjacent to each other, and the lead frame includes a first lead assembly connected to the first side portion and a second lead assembly connected to the second side portion; the first pin assembly comprises one or more pins and the second pin assembly comprises one or more pins; the first pin assembly and the second pin assembly are used for supporting the first base island;
the third base island comprises a third edge part and a fourth edge part which are adjacent, and the lead frame comprises a third pin assembly connected with the third edge part and a fourth pin assembly connected with the fourth edge part; the third pin assembly comprises one or more pins and the fourth pin assembly comprises one or more pins; the third and fourth pin assemblies are configured to support the third base island.
Preferably, the front surface of the silicon-based field effect transistor chip is provided with a first source electrode and a first grid electrode, and the back surface of the silicon-based field effect transistor chip is provided with a first drain electrode; the back surface of the silicon-based field effect transistor chip is combined with the first base island through a conductive combination material, and the first drain electrode is electrically connected with the first base island; the first grid is electrically connected with the control chip through an electric connector;
the lead frame comprises a first output pin assembly, the first output pin assembly comprises one or more pins, and the first source is electrically connected with the first output pin assembly.
Preferably, the lead frame comprises a second output pin assembly, and the second output pin assembly comprises one or more pins; the front surface of the gallium nitride chip is provided with a first electrode, a second electrode and a third electrode; the back surface of the gallium nitride chip is fixed on the second base island through a bonding material; the first electrode is electrically connected to the first base island through an electrical connector, and the second electrode is electrically connected to the second output pin assembly through an electrical connector.
Preferably, an edge of one side of the second base island, which is far away from the first base island, is a fifth edge, and the second output pin assembly is arranged beside the fifth edge;
a pin in the second output pin assembly is a first high-voltage pin, and the first high-voltage pin can bear voltage below 700V; a first electrical spacing is provided between the first high voltage pin and the fifth side portion.
Preferably, the lead frame comprises a second high-voltage pin, and the second high-voltage pin is electrically connected with the control chip; the second high-voltage pin can bear voltage below 700V;
a second electrical spacing is provided between the second high voltage pin and the third base island, and a third electrical spacing is provided between the second high voltage pin and an adjacent pin.
Preferably, a plurality of half etching grooves are formed in the front surface of the lead frame, and/or a plurality of half etching grooves are formed in the back surface of the lead frame; the semi-etched grooves are filled with the packaging material of the packaging body.
Preferably, one side of the first base island, which is far away from the silicon-based field effect transistor chip, is a first back surface, one side of the second base island, which is far away from the gallium nitride chip, is a second back surface, and one side of the third base island, which is far away from the control chip, is a third back surface; the peripheral edge of the first back surface, the peripheral edge of the second back surface, and the peripheral edge of the third back surface form the half-etched grooves, respectively.
Preferably, one side of the first base island, which is far away from the silicon-based field effect transistor chip, exposes the package, one side of the second base island, which is far away from the gallium nitride chip, exposes the package, and one side of the third base island, which is far away from the control chip, exposes the package.
The beneficial effects of the utility model are that: according to the multi-chip sealed semiconductor packaging structure, the gallium nitride chip, the silicon-based field effect transistor chip and the control chip are sealed to the same packaging structure, so that better performance can be realized, the packaging area is small, the miniaturized design of a product is facilitated, the packaging resistance is low, and the cost can be saved.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Fig. 1 is a schematic diagram illustrating a distribution of a base island and pins of a lead frame of a semiconductor package structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating an internal structure of a semiconductor package structure according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a back side structure of a semiconductor package structure according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating the arrangement of the half-etching grooves on the back surface of the lead frame according to the embodiment of the present invention (in the figure, the pattern filling portion is the half-etching groove arrangement position);
fig. 5 is a schematic view of the arrangement of the half-etching grooves on the front surface of the lead frame according to the embodiment of the present invention (the pattern filling portion is the half-etching groove arrangement position in the figure);
in the figure: 10. a lead frame; 11. a first base island; 111. a first edge portion; 112. a second edge portion; 12. a second base island; 121. a fifth side portion; 13. a third base island; 131. a third edge portion; 132. a fourth edge portion; 141. a first pin assembly; 142. a second pin assembly; 143. a third pin assembly; 144. a fourth pin assembly; 145. a fifth pin assembly; 146. a sixth pin assembly; 151. a first output pin assembly; 152. a second output pin assembly; 16. a second high voltage pin; 20. a silicon-based field effect transistor chip; 21. a first source electrode; 22. a first gate electrode; 30. a gallium nitride chip; 31. a first electrode; 32. a second electrode; 33. a third electrode; 40. a control chip; 50. a package body; 90. and (4) semi-etching a groove.
Detailed Description
In order to make the technical problems, technical solutions and technical effects achieved by the present invention more clear, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, unless otherwise explicitly specified or limited, the terms "connected" and "fixed" are to be understood broadly, e.g. as being fixedly connected, detachably connected or integrated; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The utility model provides a semiconductor packaging structure that multicore piece closed and sealed, it encapsulates control chip 40, gallium nitride chip 30 and silica-based field effect transistor chip 20 to same packaging structure in, reducible packaging area improves electronic product's integrated level, reduces the connection length of electric connector between the chip, can practice thrift the cost when reducing encapsulation resistance.
The utility model discloses a semiconductor packaging structure that multicore piece closed and sealed can be applied to in the quick charger, like the quick charger of cell-phone.
As shown in fig. 1-5, in an embodiment of the multi-chip semiconductor package structure of the present invention, the package structure includes a lead frame 10, a silicon-based field effect transistor chip 20, a gallium nitride chip 30 (GaN chip), a control chip 40 and a package 50;
the lead frame 10 includes a first base island 11, a second base island 12, and a third base island 13;
the silicon-based field effect transistor chip 20 is fixed on the first base island 11; the gallium nitride chip 30 is fixed on the second base island 12; the control chip 40 is fixed on the third base island 13;
the control chip 40 is electrically connected to the silicon-based FET chip 20, and the silicon-based FET chip 20 is electrically connected to the GaN chip 30.
Wherein, the gallium nitride is a third generation semiconductor material.
In this embodiment, the silicon-based fet chip 20 is an MOS fet chip.
In this embodiment, the first base island 11, the second base island 12, and the third base island 13 are electrically insulated from each other on the bottom surface. That is, three independent islands are used to carry three different chips.
The utility model discloses a packaging structure, through the silicon-based field effect transistor chip 20 switch of control chip 40 control, the silicon-based field effect transistor chip 20 control gallium nitride chip 30 switch of rethread. By packaging the three chips into the same packaging structure, higher integration level can be realized in a small packaging area, which is beneficial to the miniaturization design of electronic products. Carry out the scheme of interconnect again for independent encapsulation of current a plurality of chips, the utility model discloses a plurality of chips interconnect in same packaging structure, can reduce electric connector's length, when reducing encapsulation resistance, can practice thrift the cost. And moreover, the resistance is reduced, and the heat generated during operation is also reduced, so that the thermal performance of the packaging structure and the electronic product is favorably improved.
It should be noted that the present invention at least includes a silicon-based fet chip 20, a gan chip 30 and a control chip 40. In other embodiments, the number of chips may be increased according to actual requirements.
In an embodiment, in order to reduce the package area of the package structure and reduce the package resistance, the lead frame 10 and the three chips are laid out as follows:
the second base island 12 and the third base island 13 are respectively arranged at two adjacent sides of the first base island 11; thus, the control chip 40 and the gallium nitride chip 30, which are respectively required to be electrically connected with the silicon-based field effect transistor chip 20, are respectively distributed on two adjacent sides of the silicon-based field effect transistor chip 20, so that the connection distance of interconnection between the chips can be effectively reduced, and the packaging resistance is reduced.
In this embodiment, as shown in fig. 2, the control chip 40 is disposed at the upper right corner, the silicon-based fet chip 20 and the gallium nitride chip 30 are disposed at the left side, and the gallium nitride chip 30 is disposed at the lower side of the silicon-based fet chip 20.
In other embodiments, the control chip 40 may be disposed on the left side of the silicon-based fet chip 20, and the gan chip 30 may be disposed on the upper side of the silicon-based fet chip 20. Of course, the control chip 40 and the gan chip 30 may be disposed in other manners as long as the two chips are disposed on two adjacent sides of the silicon-based fet chip 20.
By adopting the mode to arrange the three chips, the minimum packaging area can be realized on the basis that the packaging structure is of a square structure, and the packaging resistance is effectively reduced compared with the situation that the three chips are arranged side by side. The square packaging structure has stronger universality.
In one embodiment, to improve the stability of the first base island 11, at least two sides of the first base island 11 are physically connected to the pins, so that the pins support the first base island 11.
In this embodiment, the first base island 11 includes a first side portion 111 and a second side portion 112 which are adjacent to each other; the lead frame 10 includes a first lead assembly 141 and a second lead assembly 142, the first lead assembly 141 includes one or more leads, and the second lead assembly 142 includes one or more leads; the first edge 111 is connected to the first lead assembly 141 to support one side of the first base island 11 through the first lead assembly 141, and the second edge 112 is connected to the second lead assembly 142 to support the other side of the first base island 11 through the second lead assembly 142.
In this embodiment, the first lead assembly 141 includes three leads, and the second lead assembly 142 includes one lead.
In other embodiments, the number of pins in the first pin assembly 141 and the second pin assembly 142 may be adjusted according to specific requirements.
In this embodiment, the first base island 11 is a rectangular base island, the first side 111 is a side of the first base island 11 on the side away from the third base island 13, and the second side 112 is a side of the first base island 11 on the side away from the second base island 12.
In one embodiment, in order to improve the stability of the third base island 13, at least two sides of the second base island 12 are physically connected to the pins, so that the pins support the third base island 13.
In this embodiment, the third base island 13 includes a third side 131 and a fourth side 132 adjacent to each other; the lead frame 10 includes a third lead assembly 143 and a fourth lead assembly 144, the third lead assembly 143 includes one or more leads, and the fourth lead assembly 144 includes one or more leads; the third side portion 131 is connected to the third lead assembly 143 to support one side of the third base island 13 through the third lead assembly 143, and the fourth side portion 132 is connected to the fourth lead assembly 144 to support the other side of the third base island 13 through the fourth lead assembly 144.
In this embodiment, the third pin assembly 143 includes one pin, and the fourth pin assembly 144 includes two pins.
In other embodiments, the number of pins in the third pin assembly 143 and the fourth pin assembly 144 can be adjusted according to specific requirements.
In this embodiment, the third base island 13 is a quadrilateral base island, the third edge 131 is an edge of the third base island 13 on the side away from the second base island 12, and the fourth edge 132 is an edge of the third base island 13 on the side away from the first base island 11.
In one embodiment, the electrodes of the silicon-based fet chip 20 are arranged as follows:
the silicon-based field effect transistor chip 20 includes a front surface and a back surface opposite to each other, wherein the front surface is provided with a first source 21 and a first gate 22, and the back surface is provided with a first drain;
the back surface of the silicon-based field effect transistor chip 20 is combined with the first base island 11 through a conductive combination material, and the first drain electrode is electrically connected with the first base island 11; the first grid 22 is electrically connected with the control chip 40 through an electric connector, and the voltage output to the first grid 22 through the control chip 40 is different, so that the switch of the silicon-based field effect transistor chip 20 is controlled.
In this embodiment, the lead frame 10 includes a first output pin assembly 151, the first output pin assembly 151 includes one or more pins, and the first source 21 is electrically connected to the pins in the first output pin assembly 151.
In one embodiment, the electrodes of the gallium nitride chip 30 are configured as follows:
the lead frame 10 includes a second output pin assembly 152;
the gallium nitride chip 30 comprises a first electrode 31, a second electrode 32 and a third electrode 33, the electrodes of the gallium nitride chip 30 are all arranged on the front surface, the back surface thereof is electrodeless to be led out, and the back surface thereof is combined with the second base island 12;
the first electrode 31 is connected with the first base island 11 through an electric connector to realize the electric connection between the gallium nitride chip 30 and the silicon-based field effect transistor chip 20, so that the control of the gallium nitride chip 30 by the silicon-based field effect transistor chip 20 is realized;
second electrode 32 is electrically connected to second output pin assembly 152 via an electrical connection; the second output pin assembly 152 includes one or more pins;
third electrode 33 is electrically connected to fifth pin assembly 145 via an electrical connection; the fifth pin assembly 145 includes one or more pins.
In this embodiment, the second output pin assembly 152 includes a plurality of pins, and the plurality of pins are large current output pins of the gallium nitride chip 30, and the more the number of the pins is led out, the more uniform the current distribution is, and the more reliable the current distribution is.
In this embodiment, the plurality of pins in the second output pin assembly 152 are high voltage pins of the gan chip 30, and the high voltage pins are designed to carry a voltage within 700V. Wherein, the high-voltage pin can be designed to bear the voltage within 650V.
In one embodiment, the three electrodes of the gan chip 12 are a source, a drain and a gate.
In one embodiment, as shown in fig. 1-3, on the basis that the second output pin assembly 152 is designed as a high-voltage pin, in order to ensure the electrical safety of components near the high-voltage pin, a first electrical interval E1 is designed between the second output pin assembly 152 and the second base island 12.
In the present exemplary embodiment, the first electrical spacing E1 is designed to be greater than 0.9mm.
In this embodiment, the pin in the second output pin assembly 152 is a first high voltage pin; the edge of the second base island 12 on the side away from the first base island 11 is a fifth edge 121, the second output pin assembly 152 is disposed on the side of the fifth edge 121 away from the first base island 11, and the first electrical interval E1 is: the space between the first high voltage pin and the fifth edge 121.
In one embodiment, the first electrical spacing E1 is designed to be 1.2mm.
In one embodiment, in order to meet the circuit requirement, the lead frame 10 is further provided with a second high voltage pin 16, the second high voltage pin 16 is electrically connected to the control chip 40, and the second high voltage pin 16 is designed to carry a voltage within 700V; wherein the high voltage pin can also be designed to carry a voltage within 650V.
In this embodiment, on the basis that the second high-voltage pin 16 is designed as a high-voltage pin, in order to ensure electrical safety of a component near the second high-voltage pin 16, a second electrical interval E2 is provided between the second high-voltage pin 16 and the third base island 13, and a third electrical interval E3 is provided between the second high-voltage pin 16 and an adjacent pin; the second electrical spacing E2 is greater than 0.9mm and the third electrical spacing E3 is greater than 0.9mm.
In one exemplary embodiment, the second electrical spacing E2, the third electrical spacing E3 is designed to be 1.2mm.
In one embodiment, to scientifically align the pins, the second high voltage pin 16 is provided by:
the edge of the third base island 13 on the side away from the second base island 12 is a third edge 131, and the edge of the third base island 13 on the side away from the first base island 11 is a fourth edge 132; the second high-voltage pin 16 is arranged beside the fourth side 132; the spacing between the second high voltage pin 16 and the fourth side 132 is a second electrical spacing E2.
In this embodiment, the fourth pin assembly 144 includes two fourth pins; the second high-voltage pin 16 is disposed between two fourth pins, and an interval between the second high-voltage pin 16 and an adjacent fourth pin is a third electrical interval E3.
In other embodiments, the second high voltage pin 16 may also be disposed beside the third side 131.
In one embodiment, the lead frame 10 further includes a sixth pin assembly 146, the sixth pin assembly 146 includes one or more pins, and the pins in the sixth pin assembly 146 are electrically connected to the control chip 40.
The pins in the sixth pin assembly 146 may be physically connected to the third base island 13 according to actual requirements, so as to support the third base island 13.
In one embodiment, the package body 50 is formed by curing an encapsulant, and in order to enhance the package strength between the lead frame 10 and the encapsulant and avoid delamination of the encapsulant near the front and back sides of the lead frame 10, the lead frame 10 is configured as follows:
as shown in fig. 4 and 5, a plurality of front half etching grooves 90 are formed on the front and/or back of the lead frame 10 by a half etching process, so that when the packaging material is used for plastic packaging, the packaging material can be filled into the half etching grooves 90, the packaging material and the lead frame 10 are combined more firmly, the bonding strength is higher, the lead frame 10 and a chip are reliably protected by the packaging material, the later-stage packaging structure can be effectively prevented from cracking, and the packaging reliability is improved.
The surface of the half-etched lead frame 10 in the etching process has a first-level surface with a concave etching part, and a lower-level surface has a product with a shallow depth and different material thicknesses, and different requirements are required for etching the lower-level surface.
In one embodiment, the back side of the island and the peripheral edge regions of the back sides of all the leads are half-etched on the basis of the structure requiring half-etching of the lead frame 10.
In this embodiment, a side of the first base island 11 departing from the silicon-based field effect transistor chip 20 is a first back surface, a side of the second base island 12 departing from the gallium nitride chip 30 is a second back surface, and a side of the third base island 13 departing from the third power chip is a third back surface; the peripheral edge of the first back surface, the peripheral edge of the second back surface, and the peripheral edge of the third back surface form a half-etching groove 90, respectively.
The half-etched grooves 90 formed in the bottom surface of the lead frame 10 are designed to satisfy the first, second, and third electrical intervals.
In this embodiment, on the basis of the structure requiring half etching of the lead frame 10, dot-like and circle-like half etching is performed on the front surface of the base island and the internal partial regions of the front surfaces of all the leads.
In this embodiment, the regions of the front half-etched grooves 90 are staggered from the regions of the back half-etched grooves 90, thereby further improving the bonding strength between the encapsulant and the lead frame 10.
In one embodiment, the depth of the front and back half-etch trenches 90 is half the material thickness.
In one embodiment, as shown in fig. 3, in order to improve the heat dissipation performance of the package structure and ensure the reliability of the product, three base islands are exposed, that is: the side of the first base island 11, which faces away from the silicon-based field effect transistor chip 20, exposes the package 50, the side of the second base island 12, which faces away from the gallium nitride chip 30, exposes the package 50, and the side of the third base island 13, which faces away from the control chip 40, exposes the package 50.
It should be noted that, in the pin assembly of the present invention, the number of the bonding regions exposed by the packaged chip is defined, and the same pin assembly includes a plurality of pins, but the plurality of pins can also be connected through the same base (e.g., the second output pin assembly 152 in fig. 1).
In one embodiment, the electrical connection between the chips and the pins are realized through metal connecting wires; when large current needs to be carried, connection can be carried out through a plurality of metal connecting wires.
Of course, the electrical connection between the chips and the leads can also be realized by a metal sheet (such as copper foil).
The utility model provides a bonding material can be soldering tin or other materials.
The utility model provides an encapsulating material can be epoxy material or other materials.
In one embodiment, the package structure is a QFN quad flat non-leaded package structure.
In one embodiment, the finished package structure has a planar dimension of 5mm × 5mm to 10mm × 10mm.
In an embodiment, the finished planar dimensions of the encapsulation structure are 8mm by 8mm.
In the description herein, it is to be understood that the terms "upper", "lower", "left", "right", and the like are used in a descriptive sense and with reference to the illustrated orientation or positional relationship, and are used for convenience in description and simplicity in operation, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in one or more embodiments or examples of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it will be understood by those skilled in the art that the specification as a whole and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
The technical principle of the present invention is described above with reference to specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without any inventive effort, which would fall within the scope of the present invention.

Claims (10)

1. A multi-chip encapsulated semiconductor package structure, comprising:
a lead frame (10) including a first base island (11), a second base island (12), and a third base island (13);
a silicon-based field effect transistor chip (20) secured to the first base island (11);
a gallium nitride chip (30) fixed to the second base island (12); the gallium nitride chip (30) is electrically connected with the silicon-based field effect transistor chip (20);
a control chip (40) fixed to the third base island (13); the control chip (40) is electrically connected with the silicon-based field effect transistor chip (20);
a package (50) encapsulating the lead frame (10), the silicon-based field effect transistor chip (20), the gallium nitride chip (30), and the control chip (40).
2. The multi-chip encapsulated semiconductor package structure of claim 1, wherein the second base island (12) and the third base island (13) are respectively disposed on two adjacent sides of the first base island (11).
3. The multi-chip encapsulated semiconductor package structure according to claim 1, wherein the first base island (11) comprises a first side portion (111) and a second side portion (112) which are adjacent to each other, the lead frame (10) comprises a first lead assembly (141) connected to the first side portion (111) and a second lead assembly (142) connected to the second side portion (112); the first pin assembly (141) comprises one or more pins and the second pin assembly (142) comprises one or more pins; the first pin assembly (141) and the second pin assembly (142) are used for supporting the first base island (11);
the third base island (13) comprises a third side part (131) and a fourth side part (132) which are adjacent, the lead frame (10) comprises a third pin assembly (143) connected with the third side part (131) and a fourth pin assembly (144) connected with the fourth side part (132); the third pin assembly (143) comprises one or more pins and the fourth pin assembly (144) comprises one or more pins; the third pin assembly (143) and the fourth pin assembly (144) are for supporting the third base island (13).
4. The multi-chip encapsulated semiconductor package structure of claim 1, wherein the silicon-based field effect transistor chip (20) has a first source (21) and a first gate (22) on the front surface thereof, and a first drain on the back surface thereof; the back surface of the silicon-based field effect transistor chip (20) is combined with the first base island (11) through a conductive combination material, and the first drain electrode is electrically connected with the first base island (11); the first grid (22) is electrically connected with the control chip (40) through an electric connector;
the lead frame (10) comprises a first output pin assembly (151), the first output pin assembly (151) comprises one or more pins, and the first source (21) is electrically connected with the first output pin assembly (151).
5. The multi-chip encapsulated semiconductor package structure of claim 1, wherein the lead frame (10) comprises a second output pin assembly (152), the second output pin assembly (152) including one or more pins therein; a first electrode (31), a second electrode (32) and a third electrode (33) are arranged on the front surface of the gallium nitride chip (30); the back surface of the gallium nitride chip (30) is fixed on the second base island (12) through a bonding material; the first electrode (31) is electrically connected to the first base island (11) by an electrical connector, and the second electrode (32) is electrically connected to the second output pin assembly (152) by an electrical connector.
6. The multi-chip encapsulated semiconductor package structure according to claim 5, wherein an edge of the second base island (12) on a side facing away from the first base island (11) is a fifth edge (121), and the second output pin assembly (152) is disposed beside the fifth edge (121);
a pin in the second output pin assembly (152) is a first high voltage pin, and the first high voltage pin can bear voltage below 700V; a first electrical separation is provided between the first high voltage pin and the fifth edge (121).
7. The multi-chip package encapsulated semiconductor package structure of claim 1, wherein the lead frame (10) comprises a second high voltage pin (16), the second high voltage pin (16) being electrically connected to the control chip (40); the second high voltage pin (16) can carry a voltage below 700V;
the second high-voltage pin (16) and the third base island (13) have a second electrical interval therebetween, and the second high-voltage pin (16) and an adjacent pin have a third electrical interval therebetween.
8. The multi-chip close-packed semiconductor package structure according to claim 1, wherein the front surface of the lead frame (10) is formed with a plurality of half-etched grooves (90), and/or the back surface of the lead frame (10) is formed with a plurality of half-etched grooves (90); the semi-etched grooves (90) are filled with the packaging material of the packaging body (50).
9. The multi-chip encapsulated semiconductor package structure according to claim 8, wherein a side of the first base island (11) facing away from the silicon-based field effect transistor chip (20) is a first back surface, a side of the second base island (12) facing away from the gallium nitride chip (30) is a second back surface, and a side of the third base island (13) facing away from the control chip (40) is a third back surface; the peripheral edge of the first back surface, the peripheral edge of the second back surface, and the peripheral edge of the third back surface form the half-etching grooves (90), respectively.
10. The multi-chip encapsulated semiconductor package structure according to claim 1, wherein a side of the first base island (11) facing away from the silicon-based field effect transistor chip (20) exposes the package body (50), a side of the second base island (12) facing away from the gallium nitride chip (30) exposes the package body (50), and a side of the third base island (13) facing away from the control chip (40) exposes the package body (50).
CN202121659319.7U 2021-07-20 2021-07-20 Multi-chip sealed semiconductor packaging structure Active CN218299797U (en)

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