CN216902939U - Packaging structure of high-voltage chip - Google Patents
Packaging structure of high-voltage chip Download PDFInfo
- Publication number
- CN216902939U CN216902939U CN202220506865.5U CN202220506865U CN216902939U CN 216902939 U CN216902939 U CN 216902939U CN 202220506865 U CN202220506865 U CN 202220506865U CN 216902939 U CN216902939 U CN 216902939U
- Authority
- CN
- China
- Prior art keywords
- voltage chip
- copper
- outer pin
- chip
- copper pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
Abstract
The utility model provides a packaging structure of a high-voltage chip, which comprises the high-voltage chip, a first copper pad connected with the back surface of the high-voltage chip, a first outer pin connected with the first copper pad, and a second outer pin connected with the active surface of the high-voltage chip, wherein a copper film layer is arranged between the high-voltage chip and the first copper pad, and the high-voltage chip is connected with the first copper pad through the copper film layer; the packaging structure is characterized in that a packaging body is arranged, the high-voltage chip, the first copper pad, the first outer pin, the second outer pin and the copper film layer are all arranged in the packaging body, and the first outer pin and the second outer pin are exposed out of the outer surface of the packaging body.
Description
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a packaging structure of a high-voltage chip.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a function requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate frames (Lead frames) through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrates through superfine metal (gold, tin, copper, aluminum and the like) wires or conductive resin to form required circuits; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures such as inspection, testing, packaging and Packing, and finally warehousing and shipping.
In the prior art, the structure of a high voltage chip is more specific, as shown in fig. 1, fig. 1 is a schematic structural diagram of the high voltage chip in the prior art, a circle of recessed regions are respectively arranged at the edge around the active surface and the edge around the back surface of the high voltage chip, and the structure of the high voltage chip is designed into such a shape so as to enable the chip to resist high voltage.
When the back surface of a chip is adhered to a first copper pad connected with pins, the chip is usually adhered to the first copper pad by using a glue dispensing method, but glue easily overflows from the periphery of the chip and reaches a recessed annular region at the periphery of the back surface of the chip, and even when the glue is excessive or the adhering pressure is too high, the glue is easily extruded and contacts with the side wall and the active surface of the chip, as shown in fig. 2 and 3, fig. 2 is a structural schematic diagram of the overflow of a small dose of glue, and fig. 3 is a structural schematic diagram of the overflow of a multi-dose of glue.
SUMMERY OF THE UTILITY MODEL
The utility model provides a packaging structure of a high-voltage chip, which avoids failure caused by electric leakage of the high-voltage chip.
The technical scheme adopted by the utility model is as follows:
the packaging structure of the high-voltage chip comprises the high-voltage chip, a first copper pad connected with the back of the high-voltage chip, a first outer pin connected with the first copper pad, and a second outer pin connected with the active surface of the high-voltage chip, wherein a copper thin film layer is arranged between the high-voltage chip and the first copper pad, and the high-voltage chip is connected with the first copper pad through the copper thin film layer; the high-voltage chip, the first copper pad, the first outer pin, the second outer pin and the copper film layer are all arranged in the packaging body, and the first outer pin and the second outer pin are exposed on the outer surface of the packaging body.
Furthermore, the copper film layer is electroplated on the back surface of the high-voltage chip in an electroplating mode.
Furthermore, the active surface of the high-voltage chip is connected with the second outer pin through a metal wire.
Furthermore, a rewiring layer is arranged on the active surface of the high-voltage chip, and the high-voltage chip is connected with the second outer pin through the rewiring layer.
Furthermore, the second external pin is connected with the rewiring layer through a metal channel.
Furthermore, a channel is formed between the second outer pin on the encapsulating body and the redistribution layer in a laser through hole mode, and the metal channel is formed on the inner wall of the channel in an electroplating mode.
Furthermore, a second copper pad is arranged between the metal channel and the second outer pin, and the metal channel is connected with the second outer pin through the second copper pad.
Compared with the prior art, the utility model has the following beneficial effects: the high-voltage chip is connected with the first copper pad through the back connection of the high-voltage chip, the first outer pin is connected with the first copper pad, the second outer pin is connected with the active surface of the high-voltage chip, a copper film layer is arranged between the high-voltage chip and the first copper pad, the high-voltage chip is connected with the first copper pad through the copper film layer, the phenomenon of chip electric leakage can be effectively avoided, safety and reliability are achieved, the quality and the reliability of a chip packaging body are improved, the high-voltage chip is pressed on the first copper pad through the copper film layer, the copper film layer cannot be extruded to the side wall and the active surface of the chip, the active surface or the side wall of the chip is effectively prevented from being conducted with the back, and therefore the phenomenon of chip electric leakage is avoided.
Drawings
FIG. 1 is a schematic diagram of a high voltage chip in the prior art;
FIG. 2 is a schematic view of a prior art structure for spilling a small amount of glue;
FIG. 3 is a schematic diagram illustrating a structure of multi-dose glue overflow in the prior art;
FIG. 4 is a schematic diagram of a package structure of an embodiment of a high voltage chip according to the utility model;
fig. 5 is a schematic diagram of a package structure of another embodiment of a high voltage chip according to the utility model.
Detailed Description
The present invention will now be described in connection with particular embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functionality throughout.
The directional phrases used in this disclosure include, for example: upper, lower, left, right, front, rear, inner, outer, front, rear, side, etc. are directions with reference to the drawings only, and the embodiments described below by referring to the drawings and directional terms used are exemplary only for explaining the present invention, and are not to be construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials that one of ordinary skill in the art would recognize for other processes and/or uses of other materials.
Fig. 4 is a schematic diagram of a package structure of a high voltage chip according to an embodiment of the utility model.
The utility model provides a packaging structure of high voltage chip, includes high voltage chip 10, the first copper pad 20 of being connected with the back of high voltage chip 10, the first outer pin 30 of being connected with first copper pad 20, the second outer pin 40 of being connected with the active face of high voltage chip 10 is equipped with copper thin layer 50 between high voltage chip 10 and the first copper pad 20, and copper thin layer 50 is electroplated the back of high voltage chip 10 through the mode of electroplating.
The high-voltage chip 10 is connected with the first copper pad 20 through the copper film layer 50; an encapsulation body 60 is arranged, the high-voltage chip 10, the first copper pad 20, the first outer pin 30, the second outer pin 40 and the copper film layer 50 are all arranged in the encapsulation body 60, and the first outer pin 30 and the second outer pin 40 are exposed on the outer surface of the encapsulation body 60.
In this embodiment, the redistribution layer a2 is disposed on the active surface of the high-voltage chip 10, and the high-voltage chip 10 and the second outer lead 40 are connected by the redistribution layer a 2. In other embodiments, the active surface of the high voltage chip 10 is connected to the second outer lead 40 by a metal wire a1, as shown in fig. 5, fig. 5 is a schematic view of a package structure of another embodiment of the high voltage chip according to the utility model.
In this embodiment, the second outer pin 40 is connected to the redistribution layer a2 by providing a metal via a3, a via 61 is formed between the second outer pin 40 and the redistribution layer a2 on the encapsulant 60 by a laser via, a metal via a3 is formed on the inner wall of the via 61 by electroplating, a second copper pad 70 is provided between the metal via a3 and the second outer pin 40, and the metal via a3 is connected to the second outer pin 40 by the second copper pad 70.
The high-voltage chip packaging structure comprises a first copper pad 20 connected with the back of a high-voltage chip 10, a first outer pin 30 connected with the first copper pad 20, a second outer pin 40 connected with the active surface of the high-voltage chip 10, a copper film layer 50 arranged between the high-voltage chip 10 and the first copper pad 20, the high-voltage chip 10 is connected with the first copper pad 20 through the copper film layer 50, the phenomenon of chip electric leakage can be effectively avoided, safety and reliability are achieved, the quality and the reliability of a chip packaging body are improved, the high-voltage chip 10 is pressed on the first copper pad 20 through the copper film layer 50, the copper film layer 50 cannot be extruded to the side wall and the active surface of the chip, the active surface or the side wall of the chip is effectively prevented from being conducted with the back, and the phenomenon of chip electric leakage is avoided.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the utility model, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. The packaging structure of the high-voltage chip is characterized by comprising a high-voltage chip (10), a first copper pad (20) connected with the back surface of the high-voltage chip (10), a first outer pin (30) connected with the first copper pad (20), and a second outer pin (40) connected with the active surface of the high-voltage chip (10), wherein a copper thin film layer (50) is arranged between the high-voltage chip (10) and the first copper pad (20), and the high-voltage chip (10) is connected with the first copper pad (20) through the copper thin film layer (50); an encapsulating body (60) is arranged, the high-voltage chip (10), the first copper pad (20), the first outer pin (30), the second outer pin (40) and the copper film layer (50) are all arranged in the encapsulating body (60), and the first outer pin (30) and the second outer pin (40) are exposed on the outer surface of the encapsulating body (60).
2. The high-voltage chip package structure according to claim 1, wherein the copper thin film layer (50) is electroplated to the back surface of the high-voltage chip (10) by electroplating.
3. The package structure of a high-voltage chip according to claim 1, wherein the active surface of the high-voltage chip (10) is connected to the second outer lead (40) through a metal wire (a 1).
4. The package structure of a high-voltage chip according to claim 1, wherein a redistribution layer (a2) is disposed on the active surface of the high-voltage chip (10), and the high-voltage chip (10) and the second external lead (40) are connected through the redistribution layer (a 2).
5. The package structure of a high voltage chip according to claim 4, wherein the second outer lead (40) is connected to the redistribution layer (a2) by a metal via (a 3).
6. The package structure of a high voltage chip according to claim 5, wherein a via (61) is formed between the second outer lead (40) on the encapsulating body (60) and the redistribution layer (a2) by means of a laser via, and the metal via (a3) is formed on the inner wall of the via (61) by means of electroplating.
7. The package structure of a high voltage chip according to claim 6, wherein a second copper pad (70) is disposed between the metal via (a3) and the second outer lead (40), and the metal via (a3) is connected to the second outer lead (40) through the second copper pad (70).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220506865.5U CN216902939U (en) | 2022-03-09 | 2022-03-09 | Packaging structure of high-voltage chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220506865.5U CN216902939U (en) | 2022-03-09 | 2022-03-09 | Packaging structure of high-voltage chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216902939U true CN216902939U (en) | 2022-07-05 |
Family
ID=82189980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220506865.5U Active CN216902939U (en) | 2022-03-09 | 2022-03-09 | Packaging structure of high-voltage chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216902939U (en) |
-
2022
- 2022-03-09 CN CN202220506865.5U patent/CN216902939U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6541307B2 (en) | Multimedia chip package | |
| CN216902939U (en) | Packaging structure of high-voltage chip | |
| US6221697B1 (en) | Chip scale package and manufacturing method thereof | |
| CN114597197A (en) | Packaging structure of high-voltage chip | |
| US20030189250A1 (en) | Semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof and a method of fabricating the semiconductor package | |
| CN112563233B (en) | Planar packaging part and production method thereof | |
| CN113793810A (en) | Chip glue overflow prevention packaging method and packaging structure | |
| CN100539122C (en) | The packaging body of system in package | |
| CN111755397A (en) | Packaging structure of multi-base-island lead frame and packaging method thereof | |
| KR200169583Y1 (en) | Ball grid array package | |
| CN216928549U (en) | wBGA packaging structure of front-mounted chip | |
| CN212848364U (en) | Packaging structure of multi-base-island lead frame | |
| US20030201546A1 (en) | Resin-sealed semiconductor device | |
| CN214956854U (en) | Chip packaging structure | |
| US20230411317A1 (en) | Chip package | |
| CN114613686A (en) | Method for preventing chip back and packaging body from layering | |
| CN112466830A (en) | Chip packaging structure | |
| CN114664666A (en) | Semiconductor packaging method for improving conduction performance | |
| CN114361045A (en) | Deep hole processing method based on semiconductor packaging | |
| CN112103280A (en) | Chip packaging structure, chip packaging method and digital isolator | |
| TW202236560A (en) | Semiconductor package structure and leadframe | |
| KR100345163B1 (en) | Ball grid array package | |
| CN112614787A (en) | Packaging method for chip packaging | |
| CN111816624A (en) | Wafer-level chip packaging structure and packaging process thereof | |
| KR200292411Y1 (en) | Leadframe for Small Die Pad Package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Anhui Xingtai Financial Leasing Co.,Ltd. Assignor: Hefei Silicon Microelectronics Technology Co.,Ltd. Contract record no.: X2023980036895 Denomination of utility model: A Packaging Structure for High Voltage Chips Granted publication date: 20220705 License type: Exclusive License Record date: 20230627 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A Packaging Structure for High Voltage Chips Effective date of registration: 20230628 Granted publication date: 20220705 Pledgee: Anhui Xingtai Financial Leasing Co.,Ltd. Pledgor: Hefei Silicon Microelectronics Technology Co.,Ltd. Registration number: Y2023980046373 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |