CN216928549U - wBGA packaging structure of front-mounted chip - Google Patents

wBGA packaging structure of front-mounted chip Download PDF

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Publication number
CN216928549U
CN216928549U CN202220214928.XU CN202220214928U CN216928549U CN 216928549 U CN216928549 U CN 216928549U CN 202220214928 U CN202220214928 U CN 202220214928U CN 216928549 U CN216928549 U CN 216928549U
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CN
China
Prior art keywords
chip
substrate
wbga
front surface
packaging
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Active
Application number
CN202220214928.XU
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Chinese (zh)
Inventor
陆海琴
张霞
高云
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Taiji Semiconductor Suzhou Co ltd
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Taiji Semiconductor Suzhou Co ltd
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Priority to CN202220214928.XU priority Critical patent/CN216928549U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The utility model relates to a wBGA (ball grid array) packaging structure of a normally installed chip, which comprises a substrate and a chip; the chip is pasted on the front surface of the substrate with the front surface facing upwards, a routing gasket is arranged on the front surface of the chip, the routing gasket on the chip is electrically connected with the front surface of the substrate through a bonding wire, the chip is packaged on the substrate through insulating resin, and a plurality of solder balls are arranged on the back surface of the substrate; the scheme does not need to flip the chip, and is a single packaging interconnection technology which can be directly attached to the substrate and separated through wire bonding, injection filling, ball mounting and cutting; the semiconductor process flow is consistent with the flow of a common BGA, and special control is not needed; and the chip does not need to pass through RDL, the chip used for wBGA is not limited, and the packaging cost is relatively economic.

Description

wBGA packaging structure of front-mounted chip
Technical Field
The utility model relates to a wBGA (ball grid array) packaging structure of a normally installed chip, belonging to the technical field of semiconductor packaging.
Background
A Windows-ball matrix array (wBGA) is a more traditional package structure, as shown in fig. 1, including a substrate 1, an epoxy glue 2, a chip 3, a bonding pad 4, a bonding wire 5, an insulating resin 6, and a solder ball 7.
The conventional process is to flip and paste the chip on the substrate by using epoxy resin glue, bond wires at the Windows position of the substrate, then perform injection molding, filling, ball mounting, cutting and separating a single package. In the conventional wBGA structure, the wire bonding pads of the chip are all in the middle area of the chip, and even if the wire bonding pads of the chip are not in the middle, the wire bonding pads of the chip are redistributed to the middle of the chip in an RDL (re-routing) manner.
The re-Routing (RDL) is to change the contact position of the originally designed IC circuit (I/Opad) through the wafer level metal routing process and the bump process, so that the IC can be suitable for different packaging types. The wafer level metal wiring process is to coat an insulating protective layer on the IC, define a new wire pattern by exposure and development, and then manufacture a new metal circuit by electroplating technology to connect the original aluminum pad and a new bump or gold pad, so as to achieve the purpose of redistribution of the circuit.
The RDL process is expensive, has no cost advantage and has no competitiveness, and the wafer manufacturing process is increased, the delivery period is prolonged, and the whole delivery period is long.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome the defects of the prior art and provide a wBGA packaging structure of a normal chip.
In order to achieve the purpose, the utility model adopts the technical scheme that: a wBGA packaging structure of a normal chip comprises a substrate and a chip; the chip is pasted on the front face of the substrate with the front face upward, a routing gasket is arranged on the front face of the chip, the routing gasket on the chip is electrically connected with the front face of the substrate through a bonding wire, the chip is packaged on the substrate through insulating resin, and a plurality of solder balls are arranged on the back face of the substrate.
Preferably, the chip is attached to the substrate through a die attach film.
Preferably, the substrate has a window structure, the chip is disposed at the window structure of the substrate, and the chip adhesive film cover the window structure of the substrate.
Preferably, the bonding pad is located at the edge of the front surface of the chip.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages:
the wBGA packaging structure of the normally-installed chip does not need to flip the chip, and can be directly attached to a substrate and then separated into single packaging interconnection technologies through lead bonding, injection molding filling, ball mounting and cutting; the semiconductor process flow is consistent with the flow of a common BGA, and special control is not needed; and the chip does not need to pass through RDL, the chip used for wBGA is not limited, and the packaging cost is relatively economic.
Drawings
The technical scheme of the utility model is further explained by combining the accompanying drawings as follows:
FIG. 1 is a schematic diagram of a prior art structure of the present invention;
fig. 2 is a schematic diagram of a wBGA package structure of a normal chip according to the present invention.
Detailed Description
The utility model is described in further detail below with reference to the figures and the embodiments.
As shown in fig. 2, the wBGA package structure of the present invention includes a substrate 1 and a chip 3; the chip 3 is right-side up and is pasted on the front surface of the substrate 1 through the chip bonding film 2, the front surface of the chip 3 is provided with the routing gasket 4, the routing gasket 4 is located at the edge of the front surface of the chip 3, and the routing gasket 4 on the chip 3 is electrically connected with the front surface of the substrate 1 through the bonding wire 5.
The substrate 1 is provided with a window structure, the chip 3 is arranged at the window structure of the substrate 1, and the chip 3 and the chip bonding film 2 cover the window structure of the substrate 1; the chip 3 is encapsulated on the substrate 1 through an insulating resin 6, and a plurality of solder balls 7 are arranged on the back surface of the substrate 1.
The scheme only emphasizes the scheme that chip routing pads are arranged on two sides and are used for wBGA packaging; during processing, the wafer is not required to be cut firstly, and then epoxy resin glue is brushed; the chip bonding film can be directly pasted on the wafer and then cut together, so that the efficiency is improved, and the cost is reduced.
The above is only a specific application example of the present invention, and the protection scope of the present invention is not limited in any way. The technical solutions formed by using equivalent transformation or equivalent substitution are all within the protection scope of the present invention.

Claims (4)

1. A wBGA packaging structure of a normal chip comprises a substrate (1) and a chip (3); the method is characterized in that: the chip (3) is pasted on the front face of the substrate (1) with the front face facing upwards, a routing gasket (4) is arranged on the front face of the chip (3), the routing gasket (4) on the chip (3) is electrically connected with the front face of the substrate (1) through a bonding wire (5), the chip (3) is packaged on the substrate (1) through insulating resin (6), and a plurality of solder balls (7) are arranged on the back face of the substrate (1).
2. The flip-chip wBGA package of claim 1, wherein: the chip (3) is adhered to the substrate (1) through the chip adhesive film (2).
3. The flip-chip wBGA package structure of claim 2, wherein: the substrate (1) is provided with a window opening structure, the chip (3) is arranged at the window opening structure of the substrate (1), and the chip (3) and the chip bonding film (2) cover the window opening structure of the substrate (1).
4. The flip-chip wBGA package of claim 1, wherein: the routing gasket (4) is positioned at the edge of the front surface of the chip (3).
CN202220214928.XU 2022-01-26 2022-01-26 wBGA packaging structure of front-mounted chip Active CN216928549U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220214928.XU CN216928549U (en) 2022-01-26 2022-01-26 wBGA packaging structure of front-mounted chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220214928.XU CN216928549U (en) 2022-01-26 2022-01-26 wBGA packaging structure of front-mounted chip

Publications (1)

Publication Number Publication Date
CN216928549U true CN216928549U (en) 2022-07-08

Family

ID=82264618

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202220214928.XU Active CN216928549U (en) 2022-01-26 2022-01-26 wBGA packaging structure of front-mounted chip

Country Status (1)

Country Link
CN (1) CN216928549U (en)

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