CN209766418U - High-performance elastic calculation packaging chip - Google Patents

High-performance elastic calculation packaging chip Download PDF

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Publication number
CN209766418U
CN209766418U CN201920776708.4U CN201920776708U CN209766418U CN 209766418 U CN209766418 U CN 209766418U CN 201920776708 U CN201920776708 U CN 201920776708U CN 209766418 U CN209766418 U CN 209766418U
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CN
China
Prior art keywords
chip
hec
interface
sub
main control
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Expired - Fee Related
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CN201920776708.4U
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Chinese (zh)
Inventor
吴君安
杨延辉
向志宏
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Beijing Super Dimension Computing Technology Co Ltd
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Beijing Super Dimension Computing Technology Co Ltd
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Priority to CN201920776708.4U priority Critical patent/CN209766418U/en
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

The utility model relates to a encapsulation chip that high performance elasticity calculated, include: the packaging structure comprises an HEC main control chip, n HEC sub-chips, a packaging substrate, an adhesive layer, a semiconductor bonding alloy wire and packaging filler. The HEC master control chip and the n HEC chips have pads. N superposed HEC sub-chips are arranged on the upper surface of the HEC main control chip; and the upper surfaces and the lower surfaces of the two adjacent HEC sub-chips are bonded through an adhesive layer. And the lowermost HEC sub-chip and the HEC main control chip are bonded through an adhesive layer. And the HEC main control chip and the packaging substrate are bonded through an adhesive layer. And the bonding pad of the HEC sub-chip and the bonding pad of the HEC main control chip are subjected to lead bonding through a semiconductor bonding alloy wire to realize electrical connection. And the bonding pad of the packaging substrate and the bonding pad of the HEC main control chip are subjected to lead bonding through a semiconductor bonding alloy wire to realize electrical connection. And packaging the gap of the packaged chip by adopting packaging filler.

Description

High-performance elastic calculation packaging chip
Technical Field
the utility model relates to a package chip especially relates to a package chip that high performance elasticity calculated.
Background
In the field of high-performance flexible computing, the connection between the high-performance flexible computing main control chip and the high-performance flexible computing sub-chip is generally performed by respectively packaging the two chips and then performing connection at the Printed Circuit Board (PCB) level, but some problems still exist in this connection method. If the chip occupies too large PCB area, the system integration level is low, and the system cannot be made small; the main chip and the sub-chip are packaged respectively, so that the cost is high; and multiple chips are interconnected at the PCB level, so that the reliability is low.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a plurality of high performance elasticity that bond calculate sub-chip on high performance elasticity calculates the main control chip to and calculate main control chip lower surface bonding packaging substrate at high performance elasticity, and realize through semiconductor bonding gold wire that high performance elasticity calculates communication between main control chip, high performance elasticity calculation sub-chip and the packaging substrate. Therefore, the high-performance elastic computing main control chip and the high-performance elastic computing sub-chip are packaged together, the packaging cost is reduced, and the integration level and the reliability of the device are improved.
In order to achieve the above object, the utility model provides a high performance elasticity calculates's encapsulation chip, include: the high-performance elastic calculation main control chip, the n high-performance elastic calculation sub-chips, the packaging substrate, the adhesive layer, the semiconductor bonding alloy wire and the packaging filler. Wherein n is a positive integer. The high-performance elastic calculation main control chip is provided with n first interfaces, and each high-performance elastic calculation sub-chip is provided with a first interface; the first interface comprises m signal ends; wherein m is a positive integer. N superposed high-performance elastic calculation sub-chips are arranged on the upper surface of the high-performance elastic calculation main control chip; the upper surfaces and the lower surfaces of the two adjacent high-performance elastic calculating sub-chips are bonded through an adhesive layer, so that assembly and bonding are realized; the lower surface of the lowest high-performance elastic calculation sub-chip is bonded with the upper surface of the high-performance elastic calculation main control chip through an adhesive layer, and assembly and bonding are achieved. And a packaging substrate is arranged on the lower surface of the high-performance elastic calculation main control chip and is bonded with the upper surface of the packaging substrate through an adhesive layer, so that assembly and bonding are realized. The first interfaces of the n high-performance elastic calculation sub-chips and the n first interfaces of the high-performance elastic calculation main control chip are subjected to lead bonding through semiconductor bonding alloy wires, and electrical connection is achieved. The high-performance elastic calculation main control chip is provided with a second interface; and the interface of the packaging substrate and the second interface of the high-performance elastic calculation main control chip are subjected to lead bonding through a semiconductor bonding gold wire to realize electrical connection. And packaging the gaps of the packaged chips by adopting packaging filler.
Preferably, the m signal terminals are arranged in the order of signal 1, signal 2, … …, and signal m.
Preferably, the wire bonding of the first interfaces of the n high-performance elastic calculation sub-chips and the n first interfaces of the high-performance elastic calculation main control chip is performed through semiconductor bonding alloy wires, and the wire bonding includes: the first interface of the ith high-performance elastic calculation sub-chip and the i first interfaces of the high-performance elastic calculation main control chip are subjected to wire bonding through semiconductor bonding alloy wires; wherein i is a positive integer and i is not more than n.
Preferably, the wire bonding of the first interfaces of the n high-performance elastic calculation sub-chips and the n first interfaces of the high-performance elastic calculation main control chip is performed through semiconductor bonding alloy wires, and the wire bonding includes: a jth signal end of a first interface of the high-performance elastic calculation sub-chip and a jth signal end of a first interface of the high-performance elastic calculation main control chip are subjected to lead bonding through a semiconductor bonding alloy wire; wherein j is a positive integer and j is less than or equal to m.
Preferably, the adhesive layer is an adhesive Film; or the adhesive layer is formed by adopting special liquid Glue.
Preferably, the package Substrate adopts a ball grid array package Substrate BGA Substrate, a grid array package Substrate LGA Substrate, a quad flat no-lead package lead frame QFN lead frame or a quad flat package lead frame QFPLAdframe.
Preferably, the material of the encapsulating filler is resin.
Preferably, each high performance elasticity computation chiplet has a third interface; and wire bonding is carried out between the third interfaces of the n high-performance elastic calculation sub-chips through semiconductor bonding alloy wires.
Preferably, each high performance elasticity computation chiplet has a third interface; and wire bonding is carried out between the interface of the packaging substrate and the third interface of the high-performance elastic calculating sub-chip through a semiconductor bonding alloy wire.
Preferably, the material of the semiconductor bonding alloy wire is gold wire, copper wire, aluminum wire or alloy wire.
The utility model discloses an use specific PAD PAD to arrange, adopt the mode that the multicore piece piled up, calculate the high performance elasticity of main control chip and different quantity with a high performance elasticity and calculate sub-chip encapsulation and be in the same place, realized that the sub-chip quantity that high performance elasticity calculated carries out the elasticity as required and deploys, reduces the encapsulation cost, integrated level and reliability during having improved.
Drawings
Fig. 1 is a schematic cross-sectional structural diagram of a packaged chip for high performance elasticity calculation according to an embodiment of the present invention;
Fig. 2 is a schematic diagram of a planar structure of a high-performance elasticity-computing packaged chip according to an embodiment of the present invention;
Fig. 3 is a schematic cross-sectional structure diagram of a chip using a solder ball array package substrate according to an embodiment of the present invention;
Fig. 4 is a schematic diagram of a planar structure of a chip using a solder ball array package substrate according to an embodiment of the present invention;
Fig. 5 is a schematic cross-sectional structural view of a chip using a grid array package substrate according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of a planar structure of a chip using a grid array package substrate according to an embodiment of the present invention;
Fig. 7 is a schematic diagram of a cross-sectional structure of a chip using a square flat leadless package lead frame according to an embodiment of the present invention;
Fig. 8 is a schematic diagram of a planar structure of a chip using a square flat leadless package lead frame according to an embodiment of the present invention;
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
As shown in fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a packaged chip with high performance elasticity calculation according to an embodiment of the present invention. The packaged chip includes: the package structure comprises a high performance electronic computing (HEC) main control chip, n HEC sub-chips, a package substrate, an adhesive layer, a semiconductor bonding alloy wire and a package filling material. Wherein n is a positive integer.
and n superposed HEC sub-chips are arranged on the upper surface of the HEC main control chip. And the upper surfaces and the lower surfaces of the two adjacent HEC sub-chips are bonded through an adhesive layer, so that assembly and bonding are realized. And the lower surface of the lowermost HEC sub-chip is bonded with the upper surface of the HEC main control chip through an adhesive layer, so that assembly and bonding are realized. And a packaging substrate is arranged on the lower surface of the HEC main control chip and is bonded with the upper surface of the packaging substrate through an adhesive layer, so that assembly and bonding are realized. And packaging the gap of the packaged chip by adopting packaging filler.
In one embodiment, the adhesive layer is made of adhesive Film or the like; or the adhesive layer is formed by adopting special liquid Glue and other materials. It should be noted by those skilled in the art that the adhesive layer may be made of any adhesive material, and the invention is not limited thereto.
One or more bonding pads are arranged on the n HEC sub-chips, the HEC main control chip and the packaging substrate. And the n HEC sub-chips, the HEC main control chip and the pads on the packaging substrate are subjected to lead bonding through semiconductor bonding gold wires, so that the electrical connection is realized.
In one embodiment, the material of the encapsulating filler is resin.
In one embodiment, the semiconductor bonding wire is made of gold wire, copper wire, aluminum wire or alloy wire.
For better description of the packaged chip of the present invention, reference may be made to the plan view structure shown in fig. 2.
As shown in fig. 2, fig. 2 is a schematic diagram of a planar structure of a packaged chip for high performance elastic calculation according to an embodiment of the present invention.
The HEC main control chip is provided with n first interfaces, and each HEC sub-chip in the n HEC sub-chips is provided with the first interface. The first interface comprises m signal ends; wherein m is a positive integer.
and the first interface of each HEC sub-chip in the n HEC sub-chips and the n first interfaces of the HEC main control chip are subjected to lead bonding through semiconductor bonding alloy wires to realize electrical connection.
In one example, the wire bonding of the n first interfaces of the high performance elasticity calculation sub-chip and the n first interfaces of the high performance elasticity calculation main control chip is performed by a semiconductor bonding alloy wire, and the wire bonding method includes: the first interface of the ith high-performance elastic calculation sub-chip and the i first interfaces of the high-performance elastic calculation main control chip are subjected to wire bonding through semiconductor bonding alloy wires; wherein i is a positive integer and i is not more than n.
For example, the first interface of the HEC sub-chip 1 and the first interface 1 of the HEC main control chip are wire-bonded through a semiconductor bonding wire, and the first interface of the HEC sub-chip 2 and the first interface 2 of the HEC main control chip are wire-bonded through a semiconductor bonding wire. And repeating the steps until the first interface n of the HEC sub-chip n and the first interface n of the HEC main control chip are subjected to wire bonding through the semiconductor bonding alloy wire. And finally, the electrical connection between the n HEC sub-chips and the HEC main control chip is realized.
in one example, the wire bonding of the n first interfaces of the high performance elasticity calculation sub-chip and the n first interfaces of the high performance elasticity calculation main control chip is performed by a semiconductor bonding alloy wire, and the wire bonding method includes: a jth signal end of a first interface of the high-performance elastic calculation sub-chip and a jth signal end of a first interface of the high-performance elastic calculation main control chip are subjected to lead bonding through a semiconductor bonding alloy wire; wherein j is a positive integer and j is less than or equal to m.
For example, the m signal terminals of the first interface of the HEC sub-chip and the m signal terminals of the first port corresponding to the HEC main control chip are wire-bonded one to one by a semiconductor bonding alloy wire. For example, the signal 1 terminal of the first interface of the HEC sub-chip 1 and the signal 1 terminal of the first interface 1 of the HEC main control chip are wire-bonded by a semiconductor bonding alloy wire. The other signal terminals are all the same as the above connection mode, and are not described herein again for convenience of description. In one example, the control signals and/or data signals and the like can be transmitted between the HEC sub-chip and the HEC main control chip through the connection in the manner described above.
in one example, the m signal terminals are arranged in the order of signal 1, signal 2, … …, and signal m.
In one example, the HEC master chip has a second interface. And the interface of the packaging substrate and the second interface of the HEC main control chip are subjected to lead bonding through a semiconductor bonding gold wire to realize electrical connection. The second interface refers to other interfaces except the first interface in the HEC main control chip. In one example, the HEC main control chip and the package substrate can be connected in the above manner, so that control signals and/or data signals can be transmitted between the HEC main control chip and the package substrate.
In one example, each HEC chiplet has a third interface. And wire bonding is carried out between the third interfaces of the n HEC sub-chips through semiconductor bonding alloy wires. The third interface refers to other interfaces except the first interface in the HEC sub-control chip. As shown in the figure, the interface a of the HEC sub-chip 2 and the interface a' of the HEC sub-chip 1 may be electrically connected by wire bonding through a semiconductor bonding wire. In one example, the HEC sub-chip and the HEC sub-chip can be connected in the above manner to transmit control signals and/or data signals and the like to each other.
In one example, wire bonding may be performed by a semiconductor bonding wire between the interface of the package substrate and the third interface of the HEC sub-chip. For example, the third interface of the HEC sub-chip n and the interface of the package substrate in the figure are electrically connected by performing wire bonding through a semiconductor bonding gold wire. In one example, the HEC sub-chip and the package substrate can be connected in the above manner, so that control signals and/or data signals can be transmitted between the HEC sub-chip and the package substrate.
In one example, the package Substrate is a Ball Grid Array (BGA) Substrate, a Land Grid Array (LGA) Substrate, a quad flat non-leaded package (QFN) Leadframe, or a Quad Flat Package (QFP) Leadframe.
in one example, the first interface, the second interface, the third interface, and the interface on the packaged chip may be implemented by way of pads.
It should be noted by those skilled in the art that "first", "second", and "third" of the above "first interface", "second interface", and "third interface" are only for distinguishing different interfaces, and are not sequentially arranged.
In one example, the present invention relates to a packaged chip that can be soldered on a Printed Circuit Board (PCB) by solder paste.
The utility model discloses an use specific PAD PAD to arrange, adopt the mode that the multicore piece piled up, calculate the high performance elasticity of main control chip and different quantity with a high performance elasticity and calculate sub-chip encapsulation and be in the same place, realized that the sub-chip quantity that high performance elasticity calculated carries out the elasticity as required and deploys, reduces the encapsulation cost, integrated level and reliability during having improved.
as shown in fig. 3, fig. 3 is a schematic diagram of a cross-sectional structure of a chip using a solder ball array package substrate according to an embodiment of the present invention.
Fig. 3 shows an implementation of a package Substrate employing a ball grid array package Substrate BGA Substrate. It can be seen that the bottom surface of BGA Substrate has one or more solder balls. The packaged chip shown in fig. 3 may be soldered on the upper surface of the PCB by means of solder paste, so as to interconnect the BGA Substrate and the PCB.
The packaged chip shown in fig. 3 includes: HEC main control chip, n HEC sub-chips, LGA Substrate, adhesive layer, semiconductor bonding alloy wire and packaging filler.
And n superposed HEC sub-chips are arranged on the upper surface of the HEC main control chip. And the upper surfaces and the lower surfaces of the two adjacent HEC sub-chips are bonded through an adhesive layer, so that assembly and bonding are realized. And the lower surface of the lowermost HEC sub-chip is bonded with the upper surface of the HEC main control chip through an adhesive layer, so that assembly and bonding are realized. BGA Substrate is arranged on the lower surface of the HEC main control chip and is bonded with the upper surface of the BGASsubstrate through an adhesive layer, so that assembly and bonding are realized. And packaging the gap of the packaged chip by adopting packaging filler.
In one embodiment, the adhesive layer is made of adhesive Film or the like; or the adhesive layer is formed by adopting special liquid Glue and other materials. It should be noted by those skilled in the art that the adhesive layer may be made of any adhesive material, and the invention is not limited thereto.
One or more bonding pads are arranged on the n HEC sub-chips, the HEC main control chip and the packaging substrate. And the n HEC sub-chips, the HEC main control chip and the pads on the packaging substrate are subjected to lead bonding through semiconductor bonding gold wires, so that the electrical connection is realized.
As shown in fig. 4, fig. 4 is a schematic diagram of a planar structure of a chip using a solder ball array package substrate according to an embodiment of the present invention.
Fig. 4 shows a schematic plan view of the packaged chip of fig. 3. The HEC main control chip is provided with n first interfaces, and each HEC sub-chip in the n HEC sub-chips is provided with the first interface. The first interface comprises m signal ends; wherein m is a positive integer.
And the first interface of each HEC sub-chip in the n HEC sub-chips and the n first interfaces of the HEC main control chip are subjected to lead bonding through semiconductor bonding alloy wires to realize electrical connection. In one example, the first interface of the HEC sub-chip 1 and the first interface 1 of the HEC main control chip are wire-bonded through a semiconductor bonding alloy wire, and the first interface of the HEC sub-chip 2 and the first interface 2 of the HEC main control chip are wire-bonded through a semiconductor bonding alloy wire. And repeating the steps until the first interface n of the HEC sub-chip n and the first interface n of the HEC main control chip are subjected to wire bonding through the semiconductor bonding alloy wire. And finally, the electrical connection between the n HEC sub-chips and the HEC main control chip is realized. In another example, the m signal terminals of the first interface of the HEC sub-chip and the m signal terminals of the corresponding first port of the HEC main control chip are wire-bonded one-to-one by semiconductor bonding wires. For example, the signal 1 terminal of the first interface of the HEC sub-chip 1 and the signal 1 terminal of the first interface 1 of the HEC main control chip are wire-bonded by a semiconductor bonding alloy wire. The other signal terminals are all the same as the above connection mode, and are not described herein again for convenience of description.
In one example, the m signal terminals are arranged in the order of signal 1, signal 2, … …, and signal m.
In one example, the HEC master chip has a second interface. And the interface of the BGA Substrate and the second interface of the HEC main control chip are subjected to lead bonding through a semiconductor bonding gold wire, so that the electrical connection is realized. The second interface refers to other interfaces except the first interface in the HEC main control chip.
In one example, each HEC chiplet has a third interface. And wire bonding is carried out between the third interfaces of the n HEC sub-chips through semiconductor bonding alloy wires. The third interface refers to other interfaces except the first interface in the HEC sub-control chip. As shown in the figure, the interface a of the HEC sub-chip 2 and the interface a' of the HEC sub-chip 1 may be electrically connected by wire bonding through a semiconductor bonding wire.
In one example, the BGA Substrate interface and the third interface of the HEC sub-chip may be wire bonded via a semiconductor bond wire. For example, the third interface of the HEC sub-chip n in the figure and the interface of BGA Substrate are electrically connected by wire bonding through a semiconductor bonding gold wire.
In one example, the first interface, the second interface, the third interface, and the interface on the packaged chip may be implemented by way of pads.
It should be noted by those skilled in the art that "first", "second", and "third" of the above "first interface", "second interface", and "third interface" are only for distinguishing different interfaces, and are not sequentially arranged.
In one example, a PCB may also be disposed under the BGA Substrate as shown in fig. 4. Wherein, the lower surface of BGA Substrate can be soldered with the upper surface of PCB by solder paste.
The utility model discloses an use specific PAD PAD to arrange, adopt the mode that the multicore piece piled up, calculate the high performance elasticity of main control chip and different quantity with a high performance elasticity and calculate sub-chip encapsulation and be in the same place, realized that the sub-chip quantity that high performance elasticity calculated carries out the elasticity as required and deploys, reduces the encapsulation cost, integrated level and reliability during having improved.
as shown in fig. 5, fig. 5 is a schematic cross-sectional structure diagram of a chip using a grid array package substrate according to an embodiment of the present invention.
Figure 5 shows an implementation of a package Substrate using a land grid array package Substrate LGA Substrate. It can be seen that the lower surface of the LGA Substrate has one or more LGA pads. The packaged chip shown in fig. 5 may be soldered on the upper surface of the PCB by using solder paste to solder the lower surface of the LGA Substrate, so as to realize interconnection between the LGA Substrate and the PCB.
The structure of the packaged chip shown in fig. 5 is the same as the packaged chip shown in fig. 1, and for convenience of description, the structure is not described again.
the packaged chip shown in fig. 5 includes: HEC main control chip, n HEC sub-chips, LGA Substrate, adhesive layer, semiconductor bonding alloy wire and packaging filler.
and n superposed HEC sub-chips are arranged on the upper surface of the HEC main control chip. And the upper surfaces and the lower surfaces of the two adjacent HEC sub-chips are bonded through an adhesive layer, so that assembly and bonding are realized. And the lower surface of the lowermost HEC sub-chip is bonded with the upper surface of the HEC main control chip through an adhesive layer, so that assembly and bonding are realized. And the lower surface of the HEC main control chip is provided with the LGA Substrate, and the lower surface of the HEC main control chip is bonded with the upper surface of the LGA Substrate through an adhesive layer, so that assembly and bonding are realized. And packaging the gap of the packaged chip by adopting packaging filler.
In one embodiment, the adhesive layer is made of adhesive film Fi lm and the like; or the adhesive layer is formed by adopting special liquid Glue and other materials. It should be noted by those skilled in the art that the adhesive layer may be made of any adhesive material, and the invention is not limited thereto.
One or more bonding pads are arranged on the n HEC sub-chips, the HEC main control chip and the packaging substrate. And the n HEC sub-chips, the HEC main control chip and the pads on the packaging substrate are subjected to lead bonding through semiconductor bonding gold wires, so that the electrical connection is realized.
As shown in fig. 6, fig. 6 is a schematic diagram of a planar structure of a chip using a grid array package substrate according to an embodiment of the present invention.
Fig. 6 shows a schematic plan view of the packaged chip of fig. 5. The HEC main control chip is provided with n first interfaces, and each HEC sub-chip in the n HEC sub-chips is provided with the first interface. The first interface comprises m signal ends; wherein m is a positive integer.
And the first interface of each HEC sub-chip in the n HEC sub-chips and the n first interfaces of the HEC main control chip are subjected to lead bonding through semiconductor bonding alloy wires to realize electrical connection. In one example, the first interface of the HEC sub-chip 1 and the first interface 1 of the HEC main control chip are wire-bonded through a semiconductor bonding alloy wire, and the first interface of the HEC sub-chip 2 and the first interface 2 of the HEC main control chip are wire-bonded through a semiconductor bonding alloy wire. And repeating the steps until the first interface n of the HEC sub-chip n and the first interface n of the HEC main control chip are subjected to wire bonding through the semiconductor bonding alloy wire. And finally, the electrical connection between the n HEC sub-chips and the HEC main control chip is realized. In another example, the m signal terminals of the first interface of the HEC sub-chip and the m signal terminals of the corresponding first port of the HEC main control chip are wire-bonded one-to-one by semiconductor bonding wires. For example, the signal 1 terminal of the first interface of the HEC sub-chip 1 and the signal 1 terminal of the first interface 1 of the HEC main control chip are wire-bonded by a semiconductor bonding alloy wire. The other signal terminals are all the same as the above connection mode, and are not described herein again for convenience of description.
In one example, the m signal terminals are arranged in the order of signal 1, signal 2, … …, and signal m.
In one example, the HEC master chip has a second interface. And the interface of the LGA Substrate and the second interface of the HEC main control chip are subjected to lead bonding through a semiconductor bonding gold wire to realize electrical connection. The second interface refers to other interfaces except the first interface in the HEC main control chip.
In one example, each HEC chiplet has a third interface. And wire bonding is carried out between the third interfaces of the n HEC sub-chips through semiconductor bonding alloy wires. The third interface refers to other interfaces except the first interface in the HEC sub-control chip. As shown in the figure, the interface a of the HEC sub-chip 2 and the interface a' of the HEC sub-chip 1 may be electrically connected by wire bonding through a semiconductor bonding wire.
in one example, wire bonding may be performed via a semiconductor bond wire between the interface of LGA Substrate and the third interface of the HEC sub-chip. For example, the third interface of the HEC sub-chip n in the figure and the interface of LGA Substrate are electrically connected by wire bonding through a semiconductor bonding gold wire.
In one example, the first interface, the second interface, the third interface, and the interface on the packaged chip may be implemented by way of pads.
It should be noted by those skilled in the art that "first", "second", and "third" of the above "first interface", "second interface", and "third interface" are only for distinguishing different interfaces, and are not sequentially arranged.
In one example, a PCB may also be disposed under the LGA Substrate as shown in FIG. 6. The lower surface of the LGA Substrate may be soldered to the upper surface of the PCB by solder paste.
The utility model discloses an use specific PAD PAD to arrange, adopt the mode that the multicore piece piled up, calculate the high performance elasticity of main control chip and different quantity with a high performance elasticity and calculate sub-chip encapsulation and be in the same place, realized that the sub-chip quantity that high performance elasticity calculated carries out the elasticity as required and deploys, reduces the encapsulation cost, integrated level and reliability during having improved.
As shown in fig. 7, fig. 7 is a schematic diagram of a cross-sectional structure of a chip using a quad flat non-leaded package lead frame according to an embodiment of the present invention.
Fig. 7 shows an implementation of a package substrate using a quad flat no-lead package lead frame QFNLeadframe. It can be seen that the lower surface of the QFN Leadframe has one or more QFN pads. The packaged chip shown in fig. 7 can be formed by soldering the lower surface of the QFN lead frame to the upper surface of the PCB by means of solder paste soldering, so as to implement interconnection between the QFN lead frame and the PCB.
The packaged chip shown in fig. 7 includes: the chip comprises an HEC main control chip, n HEC sub-chips, a QFN lead frame, an adhesive layer, a semiconductor bonding alloy wire and a packaging filler.
and n superposed HEC sub-chips are arranged on the upper surface of the HEC main control chip. And the upper surfaces and the lower surfaces of the two adjacent HEC sub-chips are bonded through an adhesive layer, so that assembly and bonding are realized. And the lower surface of the lowermost HEC sub-chip is bonded with the upper surface of the HEC main control chip through an adhesive layer, so that assembly and bonding are realized. And the lower surface of the HEC main control chip is provided with a QFN leader frame, and the QFNLoadframe is bonded with the upper surface of the QFNLoadframe through an adhesive layer, so that assembly and bonding are realized. And packaging the gap of the packaged chip by adopting packaging filler.
In one embodiment, the adhesive layer is made of adhesive Film or the like; or the adhesive layer is formed by adopting special liquid Glue and other materials. It should be noted by those skilled in the art that the adhesive layer may be made of any adhesive material, and the invention is not limited thereto.
One or more bonding pads are arranged on the n HEC sub-chips, the HEC main control chip and the packaging substrate. And the n HEC sub-chips, the HEC main control chip and the pads on the packaging substrate are subjected to lead bonding through semiconductor bonding gold wires, so that the electrical connection is realized.
As shown in fig. 8, fig. 8 is a schematic diagram of a planar structure of a chip adopting a quad flat non-leaded package lead frame according to an embodiment of the present invention.
fig. 8 shows a schematic plan view of the packaged chip of fig. 7. The HEC main control chip is provided with n first interfaces, and each HEC sub-chip in the n HEC sub-chips is provided with the first interface. The first interface comprises m signal ends; wherein m is a positive integer.
And the first interface of each HEC sub-chip in the n HEC sub-chips and the n first interfaces of the HEC main control chip are subjected to lead bonding through semiconductor bonding alloy wires to realize electrical connection. In one example, the first interface of the HEC sub-chip 1 and the first interface 1 of the HEC main control chip are wire-bonded through a semiconductor bonding alloy wire, and the first interface of the HEC sub-chip 2 and the first interface 2 of the HEC main control chip are wire-bonded through a semiconductor bonding alloy wire. And repeating the steps until the first interface n of the HEC sub-chip n and the first interface n of the HEC main control chip are subjected to wire bonding through the semiconductor bonding alloy wire. And finally, the electrical connection between the n HEC sub-chips and the HEC main control chip is realized. In another example, the m signal terminals of the first interface of the HEC sub-chip and the m signal terminals of the corresponding first port of the HEC main control chip are wire-bonded one-to-one by semiconductor bonding wires. For example, the signal 1 terminal of the first interface of the HEC sub-chip 1 and the signal 1 terminal of the first interface 1 of the HEC main control chip are wire-bonded by a semiconductor bonding alloy wire. The other signal terminals are all the same as the above connection mode, and are not described herein again for convenience of description.
in one example, the m signal terminals are arranged in the order of signal 1, signal 2, … …, and signal m.
In one example, the HEC master chip has a second interface. And the interface of the QFN leader frame and the second interface of the HEC main control chip are subjected to lead bonding through a semiconductor bonding gold wire to realize electrical connection. The second interface refers to other interfaces except the first interface in the HEC main control chip.
In one example, each HEC chiplet has a third interface. And wire bonding is carried out between the third interfaces of the n HEC sub-chips through semiconductor bonding alloy wires. The third interface refers to other interfaces except the first interface in the HEC sub-control chip. As shown in the figure, the interface a of the HEC sub-chip 2 and the interface a' of the HEC sub-chip 1 may be electrically connected by wire bonding through a semiconductor bonding wire.
In one example, wire bonding may be performed through a semiconductor bonding alloy wire between the interface of the QFN header frame and the third interface of the HEC sub-chip. For example, the third interface of the HEC sub-chip n and the interface of the QFN header frame in the figure are electrically connected by performing wire bonding through a semiconductor bonding gold wire.
In one example, the first interface, the second interface, the third interface, and the interface on the packaged chip may be implemented by way of pads.
It should be noted by those skilled in the art that "first", "second", and "third" of the above "first interface", "second interface", and "third interface" are only for distinguishing different interfaces, and are not sequentially arranged.
In one example, a PCB may also be disposed below the QFN Leadframe as shown in fig. 8. The lower surface of the QFN lead frame can be welded with the upper surface of the PCB through solder paste.
The utility model discloses an use specific PAD PAD to arrange, adopt the mode that the multicore piece piled up, calculate the high performance elasticity of main control chip and different quantity with a high performance elasticity and calculate sub-chip encapsulation and be in the same place, realized that the sub-chip quantity that high performance elasticity calculated carries out the elasticity as required and deploys, reduces the encapsulation cost, integrated level and reliability during having improved.
In the present invention, the terms "connected", connecting ", and" connecting "mean electrically connected, and if there is no specific description, they mean directly or indirectly electrically connected. The term "row" or "column" in the present invention is used in a broad sense, and can refer to either a horizontal row or a vertical row in the array.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. A packaged chip for high performance elastic computing, comprising: the high-performance elastic calculation main control chip, the n high-performance elastic calculation sub-chips, the packaging substrate, the adhesive layer, the semiconductor bonding alloy wire and the packaging filler; wherein n is a positive integer;
The high-performance flexible computing main control chip is provided with n first interfaces, and each high-performance flexible computing sub-chip is provided with a first interface; the first interface comprises m signal ends; wherein m is a positive integer;
N superposed high-performance elastic calculation sub-chips are arranged on the upper surface of the high-performance elastic calculation main control chip; the upper surfaces and the lower surfaces of the two adjacent high-performance elastic calculating sub-chips are bonded through the adhesive layers, so that assembly and bonding are realized; the lower surface of the lowermost high-performance elastic calculation sub-chip is bonded with the upper surface of the high-performance elastic calculation main control chip through the adhesive layer, so that assembly and bonding are realized;
The lower surface of the high-performance elastic calculation main control chip is provided with the packaging substrate, and the packaging substrate is bonded with the upper surface of the packaging substrate through the adhesive layer, so that assembly and bonding are realized;
The first interfaces of the n high-performance elastic calculation sub-chips and the n first interfaces of the high-performance elastic calculation main control chip are subjected to wire bonding through the semiconductor bonding alloy wires to realize electrical connection;
The high-performance elastic computing main control chip is provided with a second interface; the interface of the packaging substrate and the second interface of the high-performance elastic calculation main control chip are subjected to lead bonding through the semiconductor bonding alloy wire to realize electrical connection;
And packaging the gap of the packaged chip by adopting packaging filler.
2. The packaged chip of claim 1, wherein the m signal terminals are arranged in the order signal 1, signal 2, … …, and signal m.
3. The packaged chip of claim 1, wherein the n first interfaces of the high-performance flexible computing sub-chips and the n first interfaces of the high-performance flexible computing main chip are wire-bonded by the semiconductor bonding wires, and the wire-bonding comprises:
The first interface of the ith high-performance elastic calculation sub-chip and the i first interfaces of the high-performance elastic calculation main control chip are subjected to wire bonding through the semiconductor bonding alloy wires; wherein i is a positive integer and i is not more than n.
4. The packaged chip of claim 1, wherein the n first interfaces of the high-performance flexible computing sub-chips and the n first interfaces of the high-performance flexible computing main chip are wire-bonded by the semiconductor bonding wires, and the wire-bonding comprises:
A jth signal end of a first interface of the high-performance elastic calculation sub-chip and a jth signal end of a first interface of the high-performance elastic calculation main control chip are subjected to lead bonding through the semiconductor bonding alloy wire; wherein j is a positive integer and j is less than or equal to m.
5. The packaged chip of claim 1, wherein the package Substrate is a Ball Grid Array (BGA) Substrate, a Land Grid Array (LGA) Substrate, a quad flat no lead package (QFNEAdframe) or a Quad Flat Package (QFP) Leadframe.
6. The packaged chip of claim 1, wherein each of the high performance resilient compute chiplets has a third interface; and wire bonding is carried out between the third interfaces of the n high-performance elastic calculating sub-chips through the semiconductor bonding alloy wires.
7. The packaged chip of claim 1, wherein each of the high performance resilient compute chiplets has a third interface; and wire bonding is carried out between the interface of the packaging substrate and the third interface of the high-performance elastic calculating sub-chip through the semiconductor bonding alloy wire.
CN201920776708.4U 2019-05-27 2019-05-27 High-performance elastic calculation packaging chip Expired - Fee Related CN209766418U (en)

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