CN209199908U - A kind of flip chip packaging structure - Google Patents
A kind of flip chip packaging structure Download PDFInfo
- Publication number
- CN209199908U CN209199908U CN201821685317.3U CN201821685317U CN209199908U CN 209199908 U CN209199908 U CN 209199908U CN 201821685317 U CN201821685317 U CN 201821685317U CN 209199908 U CN209199908 U CN 209199908U
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- wiring board
- packaging structure
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
The utility model discloses a kind of flip chip packaging structure, the flip chip packaging structure includes first chip, at least one second chip, wiring board, first chip has upper and lower two surfaces, the upper surface of first chip is provided with pad, metal coupling is provided on second chip, second chip makes metal coupling connect progress signal interconnection with the pad of the first chip upper surface by inverted structure, the lower surface of first chip is provided at least one layer of wiring board, it is realized by bonding material between first chip and every layer of wiring board affixed, signal connection is carried out by metal wire between first chip and every layer of wiring board, first chip, it is wrapped up by plastic-sealed body between the surrounding of second chip and every layer of wiring board.The technical program solves the problems such as current IC design area is big or thickness is high, provides the multi-chip superposition flip-chip resin circuit board encapsulating structure that a kind of area is smaller, thinner.
Description
Technical field
The utility model relates to a kind of flip chip packaging structures, can be used for technical field of semiconductor encapsulation.
Background technique
Traditional multi-chip package form mainly uses chip tiling or longitudinal stack structure, both conventional packages
Not foot point be: 1, chip tiling encapsulating structure occupy resin circuit board area it is big.2, Chip Vertical superposition encapsulating structure is wanted
Plastic packaging body thickness is asked to increase.It is connected between former chip superposed (chip I with chip II) using non-conductive adhesive, chip I and core
II surface metal wire of piece and resin circuit board circuit connection, this integrated design circuit plastic packaging body thickness are high.
Utility model content
The purpose of this utility model is exactly to propose a kind of flip-chip to solve the above-mentioned problems in the prior art
Encapsulating structure.
The purpose of this utility model will be realized through the following technical scheme: a kind of flip chip packaging structure, including
One the first chip, at least one second chip, wiring board, first chip have upper and lower two surfaces, the first chip
Upper surface is provided with pad, and metal coupling is provided on the second chip, and the second chip makes metal coupling and by inverted structure
The pad connection of one chip upper surface carries out signal interconnection, and the lower surface of first chip is provided at least one layer of wiring board,
Realized by bonding material between first chip and every layer of wiring board it is affixed, the first chip and every layer of wiring board it
Between by metal wire carry out signal connection, by plastic packaging between the first chip, the surrounding of the second chip and every layer of wiring board
Body package.
The size for being preferably located at second chip on upper layer is less than the size for being located at the first chip of lower layer.
Preferably, second chip with a thickness of 50~200 μm.
Preferably, the wiring board is single-layer or multi-layer resin circuit board.
Preferably, the metal coupling is column structure.
Preferably, the metal coupling is tin projection or copper bump or golden convex block.
Preferably, the bonding material is conductive or nonconducting bonding material.
The advantages of technical solutions of the utility model is mainly reflected in: the technical program solves current IC dust circuit design
The problems such as area is big or thickness is high provides the multi-chip superposition flip-chip resin route that a kind of area is smaller, thinner
Plate encapsulating structure, chip superposed are used flip-chip packaged structure, are connected with metal coupling with lower layer chip, and upper layer chip superposed is reduced
Metal space of lines can be effectively reduced over all Integration circuit plastic packaging body thickness or area, improve integrated.
The structure, which can be applied, becomes small-sized thin colloid integrated circuit in general packaging body and packaging technology, such as
BGA can become ST-BGA, and LGA can become ST-LGA, and FPS can become ST-FPS ..., reduce integrated circuit in terminal
Volume occupied by plated circuit.
Detailed description of the invention
Fig. 1 is a kind of schematic diagram of flip chip packaging structure of the utility model.
Fig. 2 is the top view of Fig. 1.
Appended drawing reference in figure: the first chip of 1---, the second chip of 2---, 3--- wiring board, 4--- bonding material, 6--- modeling
Feng Ti, 7--- metal wire, 8--- metal coupling.
Specific embodiment
The purpose of this utility model, advantage and feature will carry out figure by the non-limitative illustration of preferred embodiment below
Show and explains.These embodiments are only the prominent examples using technical solutions of the utility model, all to take equivalent replacement or wait
Effect transformation and formed technical solution, all fall within the requires of the utility model protection within the scope of.
The utility model discloses a kind of flip chip packaging structure, as depicted in figs. 1 and 2, the Flip-Chip Using knot
Structure includes first chip 1, at least one second chip 2, wiring board 3, and first chip 1 has upper and lower two surfaces,
The upper surface of first chip is provided with pad, and metal coupling 8 is provided on the second chip 2, and the second chip 2 is made by inverted structure
Metal coupling is connect with the pad of the first chip upper surface carries out signal interconnection.Second chip 2 is convex with metal by flip-chip fashion
Block and the first chip signal interconnect, which greatly reduces plastic-sealed body integral thickness or area.The metal coupling 8
For column structure, the metal coupling 8 is tin projection or copper bump or golden convex block.The metal coupling can adapt to high density envelope
Dress, and there are preferable stress characteristics, it can be improved the electrical stability and mechanical stability of flip-chip packaged.
The lower surface of first chip is provided at least one layer of wiring board 3, and the wiring board is single-layer or multi-layer resin
Wiring board in the technical program, does not do the material of the wiring board specifically defined.First chip and every layer of wiring board
Between realized by bonding material 4 affixed, the bonding material is conductive or nonconducting bonding material, which can
It is bonded in the fixation of the first chip on single-layer or multi-layer resin circuit board, enhances the fastness of the first chip.First chip and every
Signal connection, the first chip, the surrounding of the second chip and every layer of route are carried out by metal wire 7 between the layer wiring board
It is wrapped up by plastic-sealed body 6 between plate.
The length of first chip, width are greater than the length of the second chip, width, second chip with a thickness of 50~
200μm。
The technical program provides the multi-chip superposition flip-chip resin circuit board envelope that a kind of area is smaller, thinner
Assembling structure.Second chip uses flip-chip packaged structure, is connected with metal coupling with the first chip, the first chip again with metal wire and
Resin circuit board circuit connection can effectively reduce over all Integration circuit plastic packaging body thickness, reduce production cost.
Still there are many embodiment, all technologies formed using equivalents or equivalent transformation for the utility model
Scheme is all fallen within the protection scope of the utility model.
Claims (7)
1. a kind of flip chip packaging structure, it is characterised in that: including first chip, at least one second chip, route
Plate, first chip have upper and lower two surfaces, and the upper surface of the first chip is provided with pad, is provided with gold on the second chip
Belonging to convex block, the second chip makes metal coupling connect progress signal interconnection with the pad of the first chip upper surface by inverted structure,
The lower surface of first chip is provided at least one layer of wiring board, by viscous between the first chip and every layer of wiring board
It ties substance and realizes affixed, pass through metal wire progress signal connection, the first chip, the between the first chip and every layer of wiring board
It is wrapped up by plastic-sealed body between the surrounding of two chips and every layer of wiring board.
2. a kind of flip chip packaging structure according to claim 1, it is characterised in that: second core positioned at upper layer
The size of piece is less than the size positioned at the first chip of lower layer.
3. a kind of flip chip packaging structure according to claim 1, it is characterised in that: second chip with a thickness of
50~200 μm.
4. a kind of flip chip packaging structure according to claim 1, it is characterised in that: the wiring board is single layer or more
Layer resin circuit board.
5. a kind of flip chip packaging structure according to claim 1, it is characterised in that: the metal coupling be column or
Chondritic.
6. a kind of flip chip packaging structure according to claim 1, it is characterised in that: the metal coupling is tin projection
Or copper bump or golden convex block.
7. a kind of flip chip packaging structure according to claim 1, it is characterised in that: the bonding material be it is conductive or
Nonconducting bonding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821685317.3U CN209199908U (en) | 2018-10-17 | 2018-10-17 | A kind of flip chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821685317.3U CN209199908U (en) | 2018-10-17 | 2018-10-17 | A kind of flip chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209199908U true CN209199908U (en) | 2019-08-02 |
Family
ID=67408263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821685317.3U Active CN209199908U (en) | 2018-10-17 | 2018-10-17 | A kind of flip chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209199908U (en) |
-
2018
- 2018-10-17 CN CN201821685317.3U patent/CN209199908U/en active Active
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