KR20110012675A - Semiconductor package and stack package using the same - Google Patents

Semiconductor package and stack package using the same Download PDF

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KR20110012675A
KR20110012675A KR1020090070492A KR20090070492A KR20110012675A KR 20110012675 A KR20110012675 A KR 20110012675A KR 1020090070492 A KR1020090070492 A KR 1020090070492A KR 20090070492 A KR20090070492 A KR 20090070492A KR 20110012675 A KR20110012675 A KR 20110012675A
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South Korea
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semiconductor chip
substrate
semiconductor
package
attached
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KR1020090070492A
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Korean (ko)
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나다운
정정태
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주식회사 하이닉스반도체
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Publication of KR20110012675A publication Critical patent/KR20110012675A/en

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

PURPOSE: A semiconductor package and a stack package using the same are provided to manufacture a high intensity and thin semiconductor package by flip-chip bonding semiconductor chips with a connection pin. CONSTITUTION: A substrate(100) comprises a mounting groove exposing a core to a first side(101) and a second side(102) opposite to the first side. The substrate comprises a bond finger(122) outside of the mounting groove. A semiconductor chip module(195) comprise a first semiconductor chip(150a), a connection member(160), and a second semiconductor chip(150b). A second semiconductor chips are respectively attached to opposite to the first semiconductor chips through a face-down type. A sealing member(190) seals the first and second sides of the substrate and the semiconductor chip module.

Description

반도체 패키지 및 이를 이용한 스택 패키지{Semiconductor Package and Stack Package using the same}Semiconductor Package and Stack Package using the same

본 발명은 반도체 패키지에 관한 것으로, 보다 구체적으로는 듀얼 스택 방식으로 제작된 고밀도 및 박형의 반도체 패키지 및 이를 이용한 스택 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a high density and thin semiconductor package manufactured in a dual stack method and a stack package using the same.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전 되고 있다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장 작업의 효율성 및 실장 후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다.In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

반도체 산업에서 말하는 "스택"이란 적어도 2개 이상의 반도체 칩 또는 패키지를 수직으로 쌓아 올리는 기술로서, 메모리 소자의 경우 반도체 집적 공정에서 구현 가능한 메모리 용량보다 큰 메모리 용량을 갖는 제품을 구현할 수 있고, 실장 면적 사용의 효율성을 높일 수 있다. In the semiconductor industry, a "stack" refers to a technology in which at least two semiconductor chips or packages are stacked vertically. In the case of a memory device, a product having a memory capacity larger than the memory capacity that can be realized in a semiconductor integration process may be implemented. It can increase the efficiency of use.

스택형의 반도체 패키지는 제조 기술에 따라 개별 반도체 칩을 스택한 후, 한번에 스택된 반도체 칩들을 패키징하는 방법과, 패키징된 개별 반도체 칩들을 스택하여 형성하는 방법으로 구분되며, 상기 스택형의 반도체 패키지는 금속 와이어 또는 관통 실리콘 비아 등을 통하여 전기적으로 연결된다.Stacked semiconductor packages are classified into a method of stacking individual semiconductor chips according to a manufacturing technology, packaging the stacked semiconductor chips at once, and stacking and forming packaged individual semiconductor chips. Is electrically connected through metal wires or through silicon vias or the like.

이하, 첨부한 도면을 참조하여 금속 와이어를 이용한 스택형의 반도체 패키지에 대해 설명하도록 한다.Hereinafter, a stack type semiconductor package using metal wires will be described with reference to the accompanying drawings.

도 1은 종래에 따른 금속 와이어를 이용한 스택형의 반도체 패키지를 나타낸 단면도이다.1 is a cross-sectional view showing a stack-type semiconductor package using a metal wire according to the prior art.

도시한 바와 같이, 금속 와이어를 이용한 반도체 패키지(5)는 적어도 2개 이상의 반도체 칩(50)들이 기판(1) 상에 접착제(14)를 매개로 스택된다. 각 반도체 칩(50)과 기판(1)은 금속 와이어(16)를 통하여 전기적으로 연결된다.As shown, at least two or more semiconductor chips 50 are stacked on the substrate 1 via the adhesive 14 in the semiconductor package 5 using the metal wire. Each semiconductor chip 50 and the substrate 1 are electrically connected through the metal wire 16.

도 1에서, 미설명된 도면부호 12는 본딩패드, 22는 본드핑거, 24는 볼랜드, 70은 솔더볼, 그리고 90은 봉지제를 각각 나타낸다.In FIG. 1, reference numeral 12 denotes a bonding pad, 22 bond finger, 24 borland, 70 solder ball, and 90 encapsulant.

현재는 주로 반도체 패키지(5)의 높은 실장 밀도를 요구하는 동시에 그 두께가 얇은 박형의 반도체 패키지(5)를 제작하는 데 연구 개발의 초점이 맞추어져 있다.Currently, the research and development focus is mainly on manufacturing the thin semiconductor package 5 which requires the high mounting density of the semiconductor package 5 and is thin.

그러나, 전술한 구성과 같이 상면으로만 반도체 칩(50)을 스택하다 보면, 박형의 반도체 패키지(5)의 연구 개발과 역행하는 결과를 초래하는바, 이에 대한 해결책에 대한 방안을 강구하는 것이 시급한 상황이다.However, when stacking the semiconductor chip 50 only on the upper surface as described above, it results in the reverse of the research and development of the thin semiconductor package 5, it is urgent to find a solution for this solution Situation.

본 발명은 듀얼 스택 방식의 적용으로 고밀도 및 박형의 반도체 패키지 및 이를 이용한 스택 패키지를 제공한다.The present invention provides a high density and thin semiconductor package and a stack package using the dual stack method.

본 발명의 실시예에 따른 반도체 패키지는 제1면 및 상기 제1면에 대향하는 제2면 각각에 코어를 노출시키는 실장홈이 구비되고, 상기 실장홈 외측에 본드핑거를 구비한 기판; 상기 기판의 실장홈 내에 페이스 업 타입으로 각각 부착된 제1 반도체 칩, 상기 제1 반도체 칩 상에 각각 부착된 연결부재, 상기 연결부재 상에 상기 제1 반도체 칩과 마주보는 페이스 다운 타입으로 각각 부착된 제2 반도체 칩을 포함한 반도체 칩 모듈; 및 상기 기판의 제1, 제2면과 상기 반도체 칩 모듈을 밀봉하는 봉지제를 포함하는 것을 특징으로 한다.According to an embodiment of the present invention, a semiconductor package may include: a substrate having a mounting groove exposing a core on each of a first surface and a second surface opposite to the first surface, and having a bond finger outside the mounting groove; A first semiconductor chip attached to each of the mounting grooves of the substrate as a face up type, a connecting member attached to the first semiconductor chip, and a face down type facing the first semiconductor chip to the connecting member, respectively. A semiconductor chip module including the second semiconductor chip; And an encapsulant sealing the first and second surfaces of the substrate and the semiconductor chip module.

상기 연결부재는 전도성 핀, 리드 프레임 및 플렉서블 기판 중 어느 하나인 것을 특징으로 한다.The connection member may be any one of a conductive pin, a lead frame, and a flexible substrate.

상기 제2 반도체 칩 상에 페이스 업 타입으로 각각 부착된 적어도 하나 이상의 제3 반도체 칩을 더 포함하는 것을 특징으로 한다.And at least one third semiconductor chip attached to the second semiconductor chip in a face-up type, respectively.

상기 제3 반도체 칩과 상기 연결부재를 전기적으로 각각 연결하는 금속 와이어를 더 포함하는 것을 특징으로 한다.And a metal wire electrically connecting the third semiconductor chip and the connection member, respectively.

상기 기판의 제1면 또는 제2면에 구비된 상기 연결부재에 부착된 외부접속단자를 더 포함하는 것을 특징으로 한다.And an external connection terminal attached to the connection member provided on the first or second surface of the substrate.

본 발명의 다른 실시예에 따른 반도체 패키지는 제1면 및 상기 제1면에 대향하는 제2면 각각에 코어를 노출시키는 실장홈이 구비되고, 상기 실장홈 외측에 본드핑거를 구비한 기판; 상기 기판의 실장홈 내에 페이스 업 타입으로 각각 부착된 제1 반도체 칩, 상기 제1 반도체 칩 상에 각각 부착된 연결부재, 상기 연결부재 상에 페이스 업 타입으로 각각 부착된 제2 반도체 칩을 포함한 반도체 칩 모듈; 및 상기 기판의 제1, 제2면과 상기 반도체 칩 모듈을 밀봉하는 봉지제를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a semiconductor package including: a mounting groove exposing a core on each of a first surface and a second surface facing the first surface, the substrate having a bond finger outside the mounting groove; A semiconductor including a first semiconductor chip attached to a face up type in a mounting groove of the substrate, a connecting member attached to the first semiconductor chip, and a second semiconductor chip attached to a face up type on the connecting member, respectively; Chip module; And an encapsulant sealing the first and second surfaces of the substrate and the semiconductor chip module.

상기 제2 반도체 칩과 상기 연결부재를 전기적으로 연결하는 금속 와이어를 더 포함하는 것을 특징으로 한다.And a metal wire electrically connecting the second semiconductor chip and the connection member.

본 발명의 실시예에 따른 스택 패키지는 수직적으로 스택된 적어도 하나 이상의 패키지 유닛을 포함하며,The stack package according to the embodiment of the present invention includes at least one package unit stacked vertically,

상기 패키지 유닛은, 제1면 및 상기 제1면에 대향하는 제2면 각각에 코어를 노출시키는 실장홈이 구비되고, 상기 실장홈 외측에 본드핑거를 구비한 기판; 상기 기판의 실장홈 내에 페이스 업 타입으로 각각 부착된 제1 반도체 칩, 상기 제1 반도체 칩 상에 각각 부착된 연결부재, 상기 연결부재 상에 상기 제1 반도체 칩과 마주보는 페이스 다운 타입으로 각각 부착된 제2 반도체 칩을 포함한 반도체 칩 모듈; 상기 기판의 제1, 제2면과 상기 반도체 칩 모듈을 밀봉하는 봉지제; 및 상기 기판의 제2면에 구비된 상기 연결부재에 부착된 솔더볼을 포함하는 것을 특징으로 한다.The package unit may include: a substrate having a mounting groove exposing a core on each of a first surface and a second surface opposite to the first surface, and having a bond finger outside the mounting groove; A first semiconductor chip attached to each of the mounting grooves of the substrate as a face up type, a connecting member attached to the first semiconductor chip, and a face down type facing the first semiconductor chip to the connecting member, respectively. A semiconductor chip module including the second semiconductor chip; An encapsulant sealing the first and second surfaces of the substrate and the semiconductor chip module; And a solder ball attached to the connection member provided on the second surface of the substrate.

상기 연결부재는 전도성 핀, 리드 프레임 및 플렉서블 기판 중 어느 하나인 것을 특징으로 한다.The connection member may be any one of a conductive pin, a lead frame, and a flexible substrate.

상기 솔더볼은 상기 스택된 패키지 유닛의 상기 기판의 제1면에 각각 구비된 상기 연결부재들과 맞닿도록 부착된 것을 특징으로 한다.The solder ball may be attached to abut on the connection members respectively provided on the first surface of the substrate of the stacked package unit.

본 발명은 코어를 노출하는 실장홈이 구비된 기판의 상면과 하면에 반도체 칩들을 부착하고, 반도체 칩들 간을 연결핀으로 플립 칩 본딩하는 것을 통해 고밀도 및 박형의 반도체 패키지 및 이를 이용한 스택 패키지를 제공하는 효과가 있다.The present invention provides a high-density and thin semiconductor package and a stack package using the same by attaching semiconductor chips to the upper and lower surfaces of a substrate having a mounting groove exposing the core and flip-chip bonding the semiconductor chips with connection pins. It is effective.

(제1 실시예)(First embodiment)

이하, 첨부한 도면을 참조하여 본 발명의 제1 실시예에 따른 반도체 패키지에 대해 설명하도록 한다.Hereinafter, a semiconductor package according to a first embodiment of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명의 제1 실시예에 따른 반도체 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention.

도시한 바와 같이, 본 발명의 제1 실시예에 따른 반도체 패키지(105)는 제1면(101) 및 상기 제1면(101)에 대향하는 제2면(102) 각각에 코어를 노출시키는 실장홈(도시안함)이 구비되고, 상기 실장홈 외측에 본드핑거(122)를 구비한 기판(100)과, 상기 기판(100)의 실장홈 내에 삽입된 반도체 칩 모듈(195)을 포함한다.As shown, the semiconductor package 105 according to the first embodiment of the present invention is mounted to expose the core on each of the first surface 101 and the second surface 102 opposite to the first surface 101. A groove (not shown) is provided, and includes a substrate 100 having a bond finger 122 outside the mounting groove and a semiconductor chip module 195 inserted into the mounting groove of the substrate 100.

상기 실장홈은 기판(100)의 제1면(101) 및 제2면(102)의 중앙에 위치하는 보호층(165)과 코어의 일부 두께를 제거하는 것을 통해 형성될 수 있다.The mounting groove may be formed by removing a portion of the protective layer 165 and the core positioned at the center of the first surface 101 and the second surface 102 of the substrate 100.

상기 반도체 칩 모듈(195)은 각각의 일면에 본딩패드(112)들이 구비되고, 기 판(100)의 실장홈 내에 페이스 업 타입(Face-Up Type)으로 각각 부착된 제1 반도체 칩(150a)과, 상기 제1 반도체 칩(150a) 상에 각각 부착된 연결부재(160)와, 상기 연결부재(160) 상에 일면에 본딩패드(112)들이 구비되고, 상기 제1 반도체 칩(150a)과 마주보는 페이스 다운 타입(Face-Down Type)으로 각각 부착된 제2 반도체 칩(150b)을 포함한다.The semiconductor chip module 195 includes bonding pads 112 formed on one surface of each of the semiconductor chip modules 195, and each of the first semiconductor chips 150a attached to the mounting groove of the substrate 100 in a face-up type. And a connection member 160 attached to each of the first semiconductor chip 150a, bonding pads 112 formed on one surface of the connection member 160, and the first semiconductor chip 150a. The second semiconductor chip 150b may be attached to face the face-down type.

상기 연결부재(160)는 전도성 핀, 리드 프레임 및 플렉서블 기판 중 어느 하나가 이용될 수 있다. 이때, 상기 제1면(101)과 제2면(102)에 위치하는 본드핑거(122)들은 기판(100)을 관통하는 비아전극(150)들을 통해 전기적으로 연결될 수 있다.The connection member 160 may use any one of a conductive pin, a lead frame, and a flexible substrate. In this case, the bond fingers 122 positioned on the first surface 101 and the second surface 102 may be electrically connected to each other through the via electrodes 150 passing through the substrate 100.

상기 제1 반도체 칩(150a)들과 제2 반도체 칩(150b)들의 본딩패드(112)들은 연결부재(160)를 사이에 두고 각각 마주보도록 배치될 수 있다.The bonding pads 112 of the first and second semiconductor chips 150a and 150b may be disposed to face each other with the connection member 160 therebetween.

이때, 상기 제1 반도체 칩(150a)들의 본딩패드(112)들은 연결부재(160)를 매개로 기판(100)의 제1면(101)의 양측 가장자리에 위치하는 본드핑거(122)들과 전기적으로 각각 연결되고, 상기 제2 반도체 칩(150b)들의 본딩패드(112)들은 연결부재(160)를 매개로 기판(100)의 제2면(102)의 양측 가장자리에 위치하는 본드핑거(122)들과 전기적으로 각각 연결된다.In this case, the bonding pads 112 of the first semiconductor chips 150a may be electrically connected to the bond fingers 122 positioned at both edges of the first surface 101 of the substrate 100 through the connection member 160. The bonding pads 112 of the second semiconductor chips 150b may be bonded to the edges of the second surface 102 of the second surface 102 of the substrate 100 via the connection member 160. Are electrically connected to each other.

또한, 상기 기판(100)의 제2면(102)에 위치하는 연결부재(160)의 하면에 외부접속단자(170)로서 솔더볼들을 더 부착할 수 있다. 도면으로 제시하지는 않았지만, 본 발명의 반도체 패키지(105)는 기판(100)의 제1면(101)과 제2면(102)에 부착된 제1 반도체 칩(150a)들과 제2반도체 칩(150b)들이 상호 대칭을 이루는 구조이므 로, 상기 기판(100)의 제1면(101)에 위치하는 연결부재(160)의 상면에 대해서만 외부접속단자(170)를 부착할 수도 있다.In addition, solder balls may be further attached to the lower surface of the connection member 160 positioned on the second surface 102 of the substrate 100 as an external connection terminal 170. Although not shown in the drawings, the semiconductor package 105 of the present invention includes the first semiconductor chip 150a and the second semiconductor chip attached to the first surface 101 and the second surface 102 of the substrate 100. Since the 150b) are symmetrical to each other, the external connection terminal 170 may be attached only to the upper surface of the connection member 160 positioned on the first surface 101 of the substrate 100.

상기 기판(100)의 제1면(101) 및 제2면(102)과 반도체 칩 모듈(195)을 밀봉하는 봉지제(190)를 더 형성할 수 있다.An encapsulant 190 may be further formed to seal the first surface 101 and the second surface 102 of the substrate 100 and the semiconductor chip module 195.

전술한 구성은 코어를 노출하는 실장홈을 구비한 기판의 상기 실장홈 내에 반도체 칩 모듈을 삽입함에 있어서, 제1 반도체 칩들과 제2 반도체 칩들을 서로 마주보도록 배치하고 연결부재를 이용하여 플립 칩 본딩하는 것을 통해 고밀도 및 박형의 반도체 패키지를 제작할 수 있다.In the above-described configuration, in inserting the semiconductor chip module into the mounting groove of the substrate having the mounting groove exposing the core, the first semiconductor chips and the second semiconductor chips are disposed to face each other and flip chip bonding using a connection member. Through this, high density and thin semiconductor packages can be manufactured.

특히, 상기 반도체 칩들 간의 전기적 연결이 연결부재에 플립 칩 본딩되므로, 전기적 신호의 경로가 짧아져 반도체 패키지의 동작 속도를 향상시킬 수 있다.In particular, since the electrical connection between the semiconductor chips is flip chip bonded to the connection member, the path of the electrical signal may be shortened to improve the operating speed of the semiconductor package.

이하, 첨부한 도면을 참조하여 본 발명의 제1 실시예에 따른 반도체 패키지의 제조방법에 대해 설명하도록 한다.Hereinafter, a method of manufacturing a semiconductor package according to a first embodiment of the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3e는 본 발명의 제1 실시예에 따른 반도체 패키지의 제조방법을 공정 순서에 따라 순차적으로 나타낸 공정 단면도이다.3A to 3E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to a first embodiment of the present invention, in the order of a process.

도 3a에 도시한 바와 같이, 제1면(101) 및 상기 제1면(101)에 대향하는 제2면(102) 각각에 코어를 노출시키는 실장홈(C)이 구비되고, 제1면(101) 및 제2면(102)의 외곽으로 본드핑거(122)들이 구비된 기판(100)을 준비한다. 상기 실장홈(C)은 기판(100)의 중앙에 위치하는 보호층(165)과 코어의 일부 두께를 제거하는 것에 의해 형성될 수 있다.As shown in FIG. 3A, a mounting groove C exposing a core is provided on each of the first surface 101 and the second surface 102 opposite to the first surface 101, and the first surface ( The substrate 100 having the bond fingers 122 is prepared outside the 101 and the second surface 102. The mounting groove C may be formed by removing the protective layer 165 positioned at the center of the substrate 100 and some thicknesses of the core.

이때, 상기 제1면(101)과 제2면(102)에 위치하는 본드핑거(122)들은 기 판(100)의 내부를 관통하는 비아전극(150)들을 통해 전기적으로 연결될 수 있다.In this case, the bond fingers 122 positioned on the first surface 101 and the second surface 102 may be electrically connected to each other through the via electrodes 150 passing through the substrate 100.

도 3b에 도시한 바와 같이, 상기 기판(100)의 제1면(101)과 제2면(102)에 각각 구비된 실장홈(C) 내에 접착제(도시안함)를 매개로 상면에 본딩패드(112)들이 구비된 제1 반도체 칩(150a)들을 부착한다. 이때, 제1 반도체 칩(150a)들은 페이스 업 타입으로 부착하는 것이 바람직하다.As illustrated in FIG. 3B, a bonding pad (or a bonding pad) may be formed on the upper surface of the substrate 100 by using an adhesive (not shown) in the mounting grooves C provided on the first and second surfaces 101 and 102, respectively. 112 are attached to the first semiconductor chip 150a. In this case, the first semiconductor chips 150a may be attached in a face up type.

다음으로, 도 3c에 도시한 바와 같이, 상기 제1 반도체 칩(150a)들 상에 연결부재(160)를 각각 배치한다. 상기 연결부재(160)는 전도성 핀, 리드 프레임 및 플렉시블 기판 중 어느 하나가 이용될 수 있다.Next, as shown in FIG. 3C, the connection members 160 are disposed on the first semiconductor chips 150a, respectively. The connection member 160 may use any one of a conductive pin, a lead frame, and a flexible substrate.

도 3d에 도시한 바와 같이, 본딩패드(112)를 구비한 제1 반도체 칩(150a)들의 일면 상에 위치하는 연결부재(160) 상에 일면에 구비한 본딩패드(112)가 상기 제1 반도체 칩(150a)들의 본딩패드(112)와 상호 대향하도록 접착제(도시안함)를 매개로 제2 반도체 칩(150b)들을 부착한다.As shown in FIG. 3D, the bonding pad 112 provided on one surface of the connection member 160 positioned on one surface of the first semiconductor chips 150a including the bonding pad 112 is formed on the first semiconductor. The second semiconductor chips 150b are attached to each other so as to face the bonding pads 112 of the chips 150a through an adhesive (not shown).

이때, 제2 반도체 칩(150b)은 페이스 다운 타입으로 부착하는 것이 바람직하다. 따라서, 제1 반도체 칩(150a)의 본딩패드(112)와 제2 반도체 칩(150b)의 본딩패드(112)는 연결부재(160)를 사이에 두고 배치될 수 있다.At this time, it is preferable to attach the second semiconductor chip 150b in a face-down type. Accordingly, the bonding pad 112 of the first semiconductor chip 150a and the bonding pad 112 of the second semiconductor chip 150b may be disposed with the connection member 160 interposed therebetween.

제1 및 제2 반도체 칩(150a, 150b)들과 연결부재(160)의 맞닿는 각각의 사이 공간과, 기판(100)에 구비된 본드핑거(122)와 연결부재(160) 간의 맞닿는 사이 공간에 솔더 페이스트(140)를 개재하고 열 및 압력을 가하여 기판(100)과 제1 및 제2 반도체 칩(150a, 150b) 간을 전기적으로 각각 연결한다.In the space between each of the first and second semiconductor chips 150a and 150b and the connection member 160 abut, and the space between the bond finger 122 and the connection member 160 provided in the substrate 100. The substrate 100 and the first and second semiconductor chips 150a and 150b are electrically connected to each other by applying heat and pressure through the solder paste 140.

이때, 상기 기판(100)의 제1면(101)과 제2면(102)에 각각 부착된 제1 및 제2 반도체 칩(150a, 150b)들과 연결부재(160)를 포함하여 반도체 칩 모듈(195)을 이룬다.In this case, the semiconductor chip module including the first and second semiconductor chips 150a and 150b and the connection member 160 attached to the first surface 101 and the second surface 102 of the substrate 100, respectively. (195).

다음으로, 도 3e에 도시한 바와 같이, 반도체 칩 모듈(195)을 포함하는 기판(100)의 하면에 외부로의 신호를 입출력하는 외부접속단자(170)를 부착한다. 특히, 상기 외부접속단자(170)는 기판(100)의 제1면(101) 또는 제2면(102)에 구비된 연결부재(160)와 접하는 상면 또는 하면에 부착하는 것이 바람직하다. 외부접속단자(170)는 일 예로 솔더볼을 포함할 수 있다.Next, as shown in FIG. 3E, an external connection terminal 170 for inputting and outputting signals to the outside is attached to the bottom surface of the substrate 100 including the semiconductor chip module 195. In particular, the external connection terminal 170 is preferably attached to the upper or lower surface in contact with the connection member 160 provided on the first surface 101 or the second surface 102 of the substrate 100. The external connection terminal 170 may include solder balls as an example.

또한, 상기 기판(100)의 제1면(101) 및 제2면(102)과 반도체 칩 모듈(195)을 밀봉하는 봉지제(190)를 더 형성할 수 있다.In addition, an encapsulant 190 may be further formed to seal the first surface 101 and the second surface 102 of the substrate 100 and the semiconductor chip module 195.

이상으로, 본 발명의 제1 실시예에 따른 반도체 패키지를 제작할 수 있다.As described above, the semiconductor package according to the first embodiment of the present invention can be manufactured.

도 4는 본 발명의 제1 실시예에 따른 반도체 패키지를 이용한 스택 패키지를 나타낸 단면도이다.4 is a cross-sectional view illustrating a stack package using a semiconductor package according to a first embodiment of the present invention.

도시한 바와 같이, 본 발명에 따른 스택 패키지(205)는 수직적으로 스택된 적어도 하나 이상의 패키지 유닛(210)을 포함한다. 각 패키지 유닛(210)은, 도 2의 반도체 패키지와 실질적으로 동일한 구성을 가질 수 있다.As shown, the stack package 205 according to the present invention includes at least one package unit 210 stacked vertically. Each package unit 210 may have a configuration substantially the same as that of the semiconductor package of FIG. 2.

이때, 상기 각 패키지 유닛(210)은, 기판(200)의 제2면에 구비된 상기 연결부재(260)에 각각 부착된 외부접속단자(270)들을 더 포함한다. 외부접속단자(270)는 일 예로 솔더볼을 포함할 수 있다.In this case, each package unit 210 further includes external connection terminals 270 attached to the connection members 260 provided on the second surface of the substrate 200. The external connection terminal 270 may include solder balls as an example.

상기 외부접속단자(270)는, 상기 스택된 상하 패키지 유닛(210) 간의 맞닿는 사이에 개재된다. 즉, 외부접속단자(270)는 스택된 패키지 유닛(210)의 상기 기 판(200)의 제1면에 각각 구비된 연결부재(260)들과 맞닿도록 부착되어 상하 패키지 유닛(210) 간의 전기적으로 연결시킨다.The external connection terminal 270 is interposed between the abutment between the stacked vertical package units 210. That is, the external connection terminal 270 is attached to abut the connecting members 260 provided on the first surface of the substrate 200 of the stacked package unit 210 to electrically connect between the upper and lower package units 210. Connect it.

또한, 스택된 패키지 유닛(210) 간의 맞닿는 사이에 상하 패키지 유닛(210) 간을 물리적으로 부착하는 접착제(도시안함)가 더 개재될 수 있다. 그 밖의 구성은 전술한 제1 실시예에 따른 반도체 패키지와 동일한바, 중복된 설명은 생략하도록 한다.In addition, an adhesive (not shown) for physically attaching the upper and lower package units 210 may be interposed between the abutments between the stacked package units 210. Other configurations are the same as the semiconductor package according to the first embodiment described above, and thus redundant descriptions thereof will be omitted.

(제2 실시예)(2nd Example)

도 5는 본 발명의 제2 실시예에 따른 반도체 패키지를 나타낸 단면도이다.5 is a cross-sectional view illustrating a semiconductor package according to a second exemplary embodiment of the present invention.

도시한 바와 같이, 본 발명의 제2 실시예에 따른 반도체 패키지(205)는 기판(200), 상기 기판(200) 상에 실장된 적어도 하나 이상의 반도체 칩 모듈(295) 및 제3 반도체 칩(250c)들을 포함한다.As illustrated, the semiconductor package 205 according to the second embodiment of the present invention may include a substrate 200, at least one semiconductor chip module 295 and a third semiconductor chip 250c mounted on the substrate 200. )

이때, 상기 제3 반도체 칩(250c)들은 최하부 반도체 칩 모듈(295)과 최상부 반도체 칩 모듈(295)의 제1 및 제2 반도체 칩(250a, 250b) 각각의 상면에 부착하는 것이 바람직하다. 특히, 상기 제3 반도체 칩(250c)들은 본딩패드(212)들이 상면을 향하는 페이스 업 타입으로 부착하는 것이 바람직하다.In this case, the third semiconductor chips 250c may be attached to upper surfaces of the first and second semiconductor chips 250a and 250b of the lowermost semiconductor chip module 295 and the uppermost semiconductor chip module 295. In particular, the third semiconductor chips 250c may be attached in a face-up type with bonding pads 212 facing upward.

이때, 상기 제1 및 제2 반도체 칩(250a, 250b)들은 제1 연결부재(260a), 제3 반도체 칩(250c)들은 제2 연결부재(260b)를 매개로 각각 본딩될 수 있다. 상기 제1 연결부재(260a)는 전도성 핀, 리드 프레임 및 플렉시블 기판 중 어느 하나가 이용될 수 있고, 제2 연결부재(260b)는 금속 와이어가 이용될 수 있다.In this case, the first and second semiconductor chips 250a and 250b may be bonded to each other through the first connection member 260a and the third semiconductor chip 250c through the second connection member 260b. The first connection member 260a may use any one of a conductive pin, a lead frame, and a flexible substrate, and the metal wire may be used as the second connection member 260b.

(제3 실시예)(Third Embodiment)

본 발명의 제3 실시예는 제1 실시예의 변형예로 그 구성에 대해 간략히 설명하도록 한다.The third embodiment of the present invention is a modification of the first embodiment to briefly describe the configuration.

도 6은 본 발명의 제3 실시예에 따른 반도체 패키지를 나타낸 단면도이다.6 is a cross-sectional view illustrating a semiconductor package according to a third exemplary embodiment of the present invention.

도시한 바와 같이, 본 발명의 제3 실시예에 따른 반도체 패키지(305)는 기판(300), 상기 기판(300) 상에 실장된 적어도 하나 이상의 반도체 칩 모듈(395)을 포함한다.As illustrated, the semiconductor package 305 according to the third embodiment of the present invention includes a substrate 300 and at least one semiconductor chip module 395 mounted on the substrate 300.

특히, 제3 실시예에서는 도 2에서 설명한 반도체 칩 모듈의 실장 방식을 일부 변경한 것을 특징으로 한다. 즉, 제1 및 제2 반도체 칩(350a, 350b)들의 부착시, 제1 반도체 칩(350a)들과 제2 반도체 칩(350b)들의 본딩패드(312)들이 서로 동일한 방향을 향하는 페이스 업 타입으로 각각 부착한 후, 제1 반도체 칩(350a)들은 제1 연결부재(360a), 제2 반도체 칩(350b)들은 제2 연결부재(360b)를 매개로 기판(300)에 각각 본딩한 것을 특징으로 한다.In particular, the third embodiment is characterized in that a part of the mounting method of the semiconductor chip module described in FIG. That is, when the first and second semiconductor chips 350a and 350b are attached, the bonding pads 312 of the first and second semiconductor chips 350a and 350b face each other in the same direction. After attaching to each other, the first semiconductor chips 350a are bonded to the substrate 300 through the first connection member 360a and the second semiconductor chip 350b through the second connection member 360b. do.

이때, 상기 제1 연결부재(360a)는 전도성 핀, 리드 프레임 및 플렉시블 기판 중 어느 하나가 이용될 수 있고, 제2 연결부재(360b)는 금속 와이어가 이용될 수 있다. 그 밖의 구성 요소는 전술한 제1 실시예와 동일한바, 중복 설명은 생략하도록 한다.In this case, any one of the conductive pin, the lead frame, and the flexible substrate may be used as the first connection member 360a, and the metal wire may be used as the second connection member 360b. The other components are the same as in the above-described first embodiment, and redundant description thereof will be omitted.

이상, 여기에서는 본 발명을 특정 실시예들에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

도 1은 종래에 따른 금속 와이어를 이용한 스택형의 반도체 패키지를 나타낸 단면도.1 is a cross-sectional view showing a stack-type semiconductor package using a metal wire according to the prior art.

도 2는 본 발명의 제1 실시예에 따른 반도체 패키지를 나타낸 단면도.2 is a cross-sectional view showing a semiconductor package according to a first embodiment of the present invention.

도 3a 내지 도 3e는 본 발명의 제1 실시예에 따른 반도체 패키지의 제조방법을 공정 순서에 따라 순차적으로 나타낸 공정 단면도.3A to 3E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to a first embodiment of the present invention in the order of processes.

도 4는 본 발명의 제1 실시예에 따른 반도체 패키지를 이용한 스택 패키지를 나타낸 단면도.4 is a cross-sectional view illustrating a stack package using a semiconductor package according to a first embodiment of the present invention.

도 5는 본 발명의 제2 실시예에 따른 반도체 패키지를 나타낸 단면도.5 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention.

도 6은 본 발명의 제3 실시예에 따른 반도체 패키지를 나타낸 단면도.6 is a cross-sectional view illustrating a semiconductor package according to a third embodiment of the present invention.

Claims (10)

제1면 및 상기 제1면에 대향하는 제2면 각각에 코어를 노출시키는 실장홈이 구비되고, 상기 실장홈 외측에 본드핑거를 구비한 기판;A substrate having a mounting groove exposing a core on each of a first surface and a second surface opposite to the first surface, the substrate having a bond finger outside the mounting groove; 상기 기판의 실장홈 내에 페이스 업 타입으로 각각 부착된 제1 반도체 칩, 상기 제1 반도체 칩 상에 각각 부착된 연결부재, 상기 연결부재 상에 상기 제1 반도체 칩과 마주보는 페이스 다운 타입으로 각각 부착된 제2 반도체 칩을 포함한 반도체 칩 모듈; 및A first semiconductor chip attached to each of the mounting grooves of the substrate as a face up type, a connecting member attached to the first semiconductor chip, and a face down type facing the first semiconductor chip to the connecting member, respectively. A semiconductor chip module including the second semiconductor chip; And 상기 기판의 제1, 제2면과 상기 반도체 칩 모듈을 밀봉하는 봉지제;An encapsulant sealing the first and second surfaces of the substrate and the semiconductor chip module; 를 포함하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서, 상기 연결부재는 전도성 핀, 리드 프레임 및 플렉서블 기판 중 어느 하나인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the connection member is any one of a conductive pin, a lead frame, and a flexible substrate. 제 1 항에 있어서, 상기 제2 반도체 칩 상에 페이스 업 타입으로 각각 부착된 적어도 하나 이상의 제3 반도체 칩을 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, further comprising at least one third semiconductor chip each attached to the second semiconductor chip in a face-up type. 제 1 항에 있어서, 상기 제3 반도체 칩과 상기 연결부재를 전기적으로 각각 연결하는 금속 와이어를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, further comprising metal wires electrically connecting the third semiconductor chip and the connection member, respectively. 제 1 항에 있어서, 상기 기판의 제1면 또는 제2면에 구비된 상기 연결부재에 부착된 외부접속단자를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, further comprising an external connection terminal attached to the connection member provided on the first or second surface of the substrate. 제1면 및 상기 제1면에 대향하는 제2면 각각에 코어를 노출시키는 실장홈이 구비되고, 상기 실장홈 외측에 본드핑거를 구비한 기판;A substrate having a mounting groove exposing a core on each of a first surface and a second surface opposite to the first surface, the substrate having a bond finger outside the mounting groove; 상기 기판의 실장홈 내에 페이스 업 타입으로 각각 부착된 제1 반도체 칩, 상기 제1 반도체 칩 상에 각각 부착된 연결부재, 상기 연결부재 상에 페이스 업 타입으로 각각 부착된 제2 반도체 칩을 포함한 반도체 칩 모듈; 및A semiconductor including a first semiconductor chip attached to a face up type in a mounting groove of the substrate, a connecting member attached to the first semiconductor chip, and a second semiconductor chip attached to a face up type on the connecting member, respectively; Chip module; And 상기 기판의 제1, 제2면과 상기 반도체 칩 모듈을 밀봉하는 봉지제;An encapsulant sealing the first and second surfaces of the substrate and the semiconductor chip module; 를 포함하는 반도체 패키지.Semiconductor package comprising a. 제 6 항에 있어서, 상기 제2 반도체 칩과 상기 연결부재를 전기적으로 연결하는 금속 와이어를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 6, further comprising a metal wire electrically connecting the second semiconductor chip and the connection member. 수직적으로 스택된 적어도 하나 이상의 패키지 유닛을 포함하며,At least one package unit stacked vertically; 상기 패키지 유닛은,The package unit, 제1면 및 상기 제1면에 대향하는 제2면 각각에 코어를 노출시키는 실장홈이 구비되고, 상기 실장홈 외측에 본드핑거를 구비한 기판;A substrate having a mounting groove exposing a core on each of a first surface and a second surface opposite to the first surface, the substrate having a bond finger outside the mounting groove; 상기 기판의 실장홈 내에 페이스 업 타입으로 각각 부착된 제1 반도체 칩, 상기 제1 반도체 칩 상에 각각 부착된 연결부재, 상기 연결부재 상에 상기 제1 반도체 칩과 마주보는 페이스 다운 타입으로 각각 부착된 제2 반도체 칩을 포함한 반도체 칩 모듈;A first semiconductor chip attached to each of the mounting grooves of the substrate as a face up type, a connecting member attached to the first semiconductor chip, and a face down type facing the first semiconductor chip to the connecting member, respectively. A semiconductor chip module including the second semiconductor chip; 상기 기판의 제1, 제2면과 상기 반도체 칩 모듈을 밀봉하는 봉지제; 및An encapsulant sealing the first and second surfaces of the substrate and the semiconductor chip module; And 상기 기판의 제2면에 구비된 상기 연결부재에 부착된 솔더볼을 포함하는 것을 특징으로 하는 스택 패키지.And a solder ball attached to the connection member provided on the second surface of the substrate. 제 8 항에 있어서, 상기 연결부재는 전도성 핀, 리드 프레임 및 플렉서블 기판 중 어느 하나인 것을 특징으로 하는 스택 패키지.The stack package of claim 8, wherein the connection member is any one of a conductive pin, a lead frame, and a flexible substrate. 제 8 항에 있어서, 상기 솔더볼은 상기 스택된 패키지 유닛의 상기 기판의 제1면에 각각 구비된 상기 연결부재들과 맞닿도록 부착된 것을 특징으로 하는 스택 패키지.The stack package of claim 8, wherein the solder balls are attached to abut the connection members respectively provided on the first surface of the substrate of the stacked package unit.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019156732A1 (en) * 2018-02-07 2019-08-15 Micron Technology, Inc. Semiconductor assemblies using edge stacking and method of manufacturing the same
CN110663111A (en) * 2017-06-13 2020-01-07 美光科技公司 Semiconductor device assembly having a lid containing circuit elements
US11715725B2 (en) 2017-02-24 2023-08-01 Micron Technology, Inc. Semiconductor device assemblies with electrically functional heat transfer structures

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11715725B2 (en) 2017-02-24 2023-08-01 Micron Technology, Inc. Semiconductor device assemblies with electrically functional heat transfer structures
CN110663111A (en) * 2017-06-13 2020-01-07 美光科技公司 Semiconductor device assembly having a lid containing circuit elements
CN110663111B (en) * 2017-06-13 2023-05-12 美光科技公司 Semiconductor device assembly having cover including circuit element
WO2019156732A1 (en) * 2018-02-07 2019-08-15 Micron Technology, Inc. Semiconductor assemblies using edge stacking and method of manufacturing the same
US10453820B2 (en) 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US10867964B2 (en) 2018-02-07 2020-12-15 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US11955457B2 (en) 2018-02-07 2024-04-09 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same

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