KR20110004120A - Semiconductor package and method for fabricating thereof - Google Patents

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to fundamentally prevent the generation of voids due to the insertion of a semiconductor chip by surrounding the semiconductor chip using sealant. CONSTITUTION: A semiconductor chip(150a) and a second semiconductor(150b) are prepared. A first dielectric layer(102) and a second dielectric layer(104) surround each semiconductor chip and in contact with each other. A first circuit wiring(122) and a second circuit wiring(124) are formed on the upper side of the dielectric layers. The circuit wirings are in connection with via-electrodes passing through the dielectric layers. A first insulating layer(152) and a second insulating layer(154) cover the upper side of the circuit wirings.

Description

Semiconductor package and method for fabrication

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to an embedded semiconductor package in which a semiconductor chip is inserted and a method of manufacturing the same.

In the semiconductor industry, packaging technology for integrated circuits has continually evolved to meet the demand for miniaturization and mounting reliability.

For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

Currently, computers, laptops and mobile phones have increased chip capacities such as large RAMs and flash memories as the memory capacity increases, but packages tend to be smaller. Situation.

Therefore, the size of a package used as a core component is being researched and developed in a tendency to be miniaturized, and various techniques for mounting a larger number of packages on a limited size substrate have been proposed and studied.

Hereinafter, a stack type semiconductor package using metal wires will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing a stack-type semiconductor package using a metal wire according to the prior art.

As shown, at least two or more semiconductor chips 50 are stacked on the substrate 1 via the adhesive 14 in the semiconductor package 5 using the metal wire. Each semiconductor chip 50 and the substrate 1 are electrically connected through the metal wire 16.

In FIG. 1, reference numeral 12 denotes a bonding pad, 22 bond finger, 24 borland, 70 solder ball, and 90 encapsulant.

Currently, the research and development focus is mainly on manufacturing the thin semiconductor package 5 which requires the high mounting density of the semiconductor package 5 and is thin.

In order to overcome this disadvantage, efforts have been actively made to manufacture an embedded type semiconductor package in which a semiconductor chip is inserted into a substrate.

However, such an embedded type semiconductor package can be electrically connected by inserting a semiconductor chip into the inside of the substrate, sealing it in a first lamination process, and then forming and plating a via hole.

At this time, in the prior art, since the semiconductor chip is inserted into the substrate, the thickness of the semiconductor chip should be less than or equal to a predetermined thickness since a sealing agent having a predetermined height or more relative to the thickness of the semiconductor chip should be used so that defects such as voids do not occur. There is a limit to the reduction.

As a result, when stacking two or more semiconductor chips, the thickness increases more than necessary, which makes it difficult to manufacture a thin stack package.

The present invention provides a thin semiconductor package in which a plurality of semiconductor chips are inserted into a semiconductor package while minimizing the thickness of the semiconductor chip and a method of manufacturing the same.

A semiconductor package according to an embodiment of the present invention includes a first semiconductor chip and a second semiconductor chip each having one surface on which a bonding pad is disposed and the other surface opposite thereto, and the other surfaces contacted with each other; A first dielectric layer and a second dielectric layer formed to surround each other and surround the first semiconductor chip and the second semiconductor chip; First and second circuit wiring lines formed on the exposed surfaces of the first and second dielectric layers, respectively, and connected to the bonding pads of the first semiconductor chip and the bonding pads of the second semiconductor chip; And an insulating layer formed to expose portions of the first circuit wiring and the second circuit wiring on exposed surfaces of the first dielectric layer and the second dielectric layer including the first circuit wiring and the second circuit wiring, respectively. It is characterized by.

A first via electrode connected to the bonding pads of the first and second semiconductor chips, and a second via electrode penetrating the first and second dielectric layers and electrically connecting the first and second circuit wirings. It characterized in that it further comprises.

At least one third semiconductor chip stacked in a face-up type on the insulating layer on the first dielectric layer or the second dielectric layer; A connection member electrically connecting the third semiconductor chip and the first circuit wiring or the second circuit wiring corresponding thereto; An encapsulation member sealing an exposed surface of the first dielectric layer or the second dielectric layer including the at least one third semiconductor chip and the connection member; And an external connection terminal attached to the first circuit wiring or the second circuit wiring exposed by the insulating layer.

The connecting member is characterized in that it comprises a metal wire.

A third semiconductor chip flip-chip bonded onto the insulating layer on the first dielectric layer or the second dielectric layer; At least one fourth semiconductor chip stacked in a face-up type on the third semiconductor chip; A connection member electrically connecting the fourth semiconductor chip and the first circuit wiring or the second circuit wiring corresponding thereto; An encapsulation member sealing an exposed surface of the first dielectric layer or the second dielectric layer including the third semiconductor chip, at least one of the fourth semiconductor chips, and the connection member; And an external connection terminal attached to the first circuit wiring or the second circuit wiring exposed by the insulating layer.

A semiconductor package according to another embodiment of the present invention is a semiconductor package in which at least two or more package units are stacked via a connection member,

The package unit may include: a first semiconductor chip and a second semiconductor chip each having one surface on which a bonding pad is disposed and the other surface opposite thereto, and the other surfaces contacted with each other; A first dielectric layer and a second dielectric layer formed to surround each other and surround the first semiconductor chip and the second semiconductor chip; First and second circuit wiring lines formed on the exposed surfaces of the first and second dielectric layers, respectively, and connected to the corresponding bonding pads of the first semiconductor chip and the bonding pads of the second semiconductor chip; And an insulating layer formed to expose portions of the first circuit wiring and the second circuit wiring on exposed surfaces of the first dielectric layer and the second dielectric layer including the first circuit wiring and the second circuit wiring, respectively. It is characterized by.

The connection member is characterized in that the solder ball or bump.

It characterized in that it further comprises an adhesive member interposed between the abutment of each package unit.

A method of manufacturing a semiconductor package according to an embodiment of the present invention includes attaching an upper surface of a first semiconductor chip to an upper surface of a substrate; Forming a lower surface of the first dielectric layer on an upper surface of the substrate including the first semiconductor chip; Forming a first circuit wiring on an upper surface of the first dielectric layer; Removing the substrate; Attaching a lower surface of the second semiconductor chip to the lower surface of the first semiconductor chip; Forming an upper surface of the second dielectric layer on a lower surface of the first dielectric layer including the second semiconductor chip; And forming a second circuit wiring on a lower surface of the second dielectric layer.

The first and second dielectric layers may be formed of any one selected from the group of insulating materials including polyimide, benzocyclobutene, and epoxy resin.

After the forming of the second circuit wiring, a first via electrode connected to the bonding pads of the first and second semiconductor chips and the first and second dielectric layers penetrate the first and second circuits, respectively. And forming a second via electrode electrically connecting the wirings.

After the forming of the first and second via electrodes, the method may further include forming first and second insulating layers covering the first and second circuit wirings, respectively.

The first and second insulating layers are formed of a solder resist.

The present invention has an advantage of preventing the generation of voids due to the insertion of the semiconductor chip by wrapping the semiconductor chip with a sealing agent in a state in which the semiconductor chips are attached to contact with the rear surface of each other.

In addition, a thin semiconductor package can be manufactured by inserting a semiconductor chip into the sealing agent.

(Example)

Hereinafter, a semiconductor package according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2A is a cross-sectional view illustrating a semiconductor package according to the present invention.

As shown, the semiconductor package 105 according to the present invention includes the first and second dielectric layers 102 and 104 and the first and second semiconductor chips 150a and 150b.

The first and second dielectric layers 102 and 104 may use any one selected from an insulating material group including polyimide, benzocyclobutene, and epoxy resin. In this case, the first and second dielectric layers 102 and 104 may include, for example, a film form.

The first and second dielectric layers 102 and 104 surround the first and second semiconductor chips 150a and 150b, respectively, and are bonded to each other so that the rear surfaces thereof come into contact with each other. Therefore, bonding pads 112 are provided on respective top surfaces of the first and second semiconductor chips 150a and 150b, respectively.

In addition, first and second circuit wirings 122 and 124 are formed on upper surfaces of each of the first and second dielectric layers 102 and 104. The first and second circuit wirings 122 and 124 are connected to the first via electrode 132 and the second via electrode 134 formed inside the first and second dielectric layers 102 and 104, respectively.

Therefore, the first and second semiconductor chips 150a and 150b may be electrically connected to each other through the first and second circuit wirings 122 and 124 and the first and second via electrodes 132 and 134.

The first via electrode 132 is connected to the bonding pads 112 of the first and second semiconductor chips 150a and 150b, respectively. In addition, the second via electrode 134 penetrates the first and second dielectric layers 102 and 104 and electrically connects the first and second circuit wirings 122 and 124.

In addition, first and second insulating layers 152 and 154 may be further formed to cover top surfaces of the first and second circuit wirings 122 and 124, respectively.

The above-described configuration wraps the first and second semiconductor chips with the first and second dielectric layers, which are sealing agents, and is bonded so that the rear surfaces of the first and second semiconductor chips come into contact with each other, so that there is no fear of voids. As a result, it is possible to actively cope with the manufacture of a thin semiconductor package with the effect of minimizing the thickness of the semiconductor chip.

2B is a cross-sectional view illustrating a stack-type semiconductor package according to the present invention, which will be described in more detail with reference to this.

As shown, the stack-type semiconductor package 101 according to the present invention, the package unit 105 stacked via the connection member 130 and the adhesive member 114 interposed between at least two or more contact with each other. )

Each package unit 105 may have the same configuration as the semiconductor package shown in FIG. 2A. That is, each of the package units 105 may include first and second dielectric layers 102 and 104, and first and second semiconductor chips 150a, which are inserted into the first and second dielectric layers 102 and 104, respectively. 150b).

In addition, first and second circuit wirings 122 and 124 having first and second ball lands 123 and 125 are formed on upper surfaces of the first and second dielectric layers 102 and 104, respectively. In addition, first and second insulating layers 152 and 154 may be further formed to cover top surfaces of the first and second circuit wirings 122 and 124, respectively.

In this case, the stack-type semiconductor package 101 may be electrically and physically connected between the package units 105 through the connection member 130 and the adhesive member 114. The connection member 130 may be a solder ball or a bump.

The stacked semiconductor package 101 may further include an external connection terminal 170 attached to one surface of the lowermost package unit 105 or the uppermost package unit 105. The external connection terminal 170 may be any one of the first and second circuit wirings 122 and 124 having the first and second borlands 123 and 125 disposed in the lowermost and uppermost package units 105, respectively. It is preferable to attach to one surface which is in contact with the circuit wiring.

In addition, a sealing member (not shown) covering one surface of the uppermost or lowermost package unit 105 may be further included.

(Application example)

3A to 3D are cross-sectional views illustrating semiconductor packages according to an application example of the present invention, and the same reference numerals are used for the same names as those of FIG. 2A.

First, as shown in FIG. 3A, the semiconductor package 105 according to an application example of the present invention is face-up on the semiconductor package 105 and the semiconductor package 105 shown in FIG. 1. up) a third semiconductor chip 150c attached in a type. In addition, the semiconductor package 105 according to an application of the present invention further includes a fourth semiconductor chip 150d attached as a face-up type on the third semiconductor chip 150c as shown in FIG. 3B. can do.

The bonding pads 112 of the third semiconductor chip 150c and the fourth semiconductor chip 150d may include first and second borlands provided on exposed surfaces of portions of the first or second insulating layers 152 and 154. The first or second circuit wirings 122 and 124 having the 123 and 125 are electrically connected to each other through the connecting member 116. For example, a metal wire may be used as the connection member 116.

In addition, the third and fourth semiconductor chips 150a and 150b attached to the first and second insulating layers 152 and 154 may be physically attached to each other through the adhesive 114 interposed between the first and second insulating layers 152 and 154. have.

In this case, an encapsulation member 190 for sealing the exposed surface of the first dielectric layer 102 or the second dielectric layer 104 including at least one semiconductor chip 150a, 150b and the connection member 116 is further included. Can be formed. The external connection terminal 170 may be further attached to the first or second ball lands 123 and 125 provided in the first dielectric layer 102 or the second dielectric layer 104.

3C and 3D, the semiconductor package 105 according to another application example of the present invention includes the semiconductor package 105 shown in FIG. 1 and a flip chip on the semiconductor package 105. It may include a bonded third semiconductor chip 150c. In addition, at least one of the fourth semiconductor chips 150d attached to the upper surface of the third semiconductor chip 150c may be further included as a face-up type.

Between the bonding pad 112 of the third semiconductor chip 150c and the first circuit wiring 122 or the second circuit wiring 124 having the first and second borland 123 and 125 corresponding thereto, respectively, As a connecting member 116 to be connected to the metal wire, it is characterized in that the use of bumps.

In this case, the third semiconductor chip 150c may be attached to the bonding pad 112 provided therein in a face-down type facing the first or second dielectric layers 102 and 104.

Although not shown in detail in the drawing, when the third semiconductor chip 150c is attached, the first or second circuit wiring 122 positioned on the top surface of the first or second dielectric layers 102 and 104 may be rearranged. It is desirable to change the arrangement.

In this case, the at least one fourth semiconductor chip 150d attached to the third semiconductor chip 150c in the form of a face-up type may include the bonding pads 112 provided in the first or second dielectric layers 102 and 104. The first or second borland 122 and the at least one or more connecting members 116 positioned on the upper surface thereof are electrically connected to each other. For example, a metal wire may be used as the connection member 116.

Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described with reference to the accompanying drawings.

4A through 4E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention, according to a process sequence.

As shown in FIG. 4A, an upper surface of the first semiconductor chip 150a is attached to the upper surface of the substrate 100. In this case, the bonding pads 112 included in the first semiconductor chip 150a may be attached in a face-up type disposed on an upper surface thereof.

Next, a bottom surface of the first dielectric layer 102 is formed on the top surface of the substrate 100 including the first semiconductor chip 150a. The first dielectric layer 102 may be any one selected from the group of insulating materials including polyimide, benzocyclobutene, and epoxy resin. For example, the first dielectric layer 102 may be manufactured in a film form and attached to the first semiconductor chip 150a by thermocompression bonding.

As shown in FIG. 4B, the first circuit wiring 122 is formed on the upper surface of the first dielectric layer 102. Next, the substrate (100 in FIG. 4A) disposed on the bottom surface of the first dielectric layer 102 is removed.

The substrate may be removed by performing any one or more than one of a backgrinding process and an etching process. In the above-described process, the first semiconductor chip 150a may be disposed in the first dielectric layer 102.

Next, the lower surface of the second semiconductor chip 150b is attached to the lower surface of the first semiconductor chip 150a. Although not shown in the drawings, the first semiconductor chip 150a and the second semiconductor chip 150b may be attached to each other through an adhesive (not shown) interposed therebetween.

As shown in FIG. 4C, the upper surface of the second dielectric layer 104 is attached to the lower surface of the first dielectric layer 102 including the second semiconductor chip 150b so as to face the lower surface of the second dielectric layer 104. The second circuit wiring 124 is formed on the substrate. In this case, the same material as the first dielectric layer 102 may be used for the second dielectric layer 104.

As shown in FIG. 4D, the first and second dielectric layers 102 and 104 are patterned by any one of laser drilling or dry etching to form the via holes 160, and a metal material is formed in the via holes 160. The buried first via electrode 132 and the second via electrode 134 are formed.

The metal material may be any one of copper (Cu), tin (Sn), aluminum (Al), gold (Au), nickel (Ni), and platinum (Pt).

In this case, the first via electrode 132 is connected to the bonding pads 112 of the first and second semiconductor chips 150a and 150b, respectively, and the second via electrode 134 is connected to the first and second circuit wirings ( 122 and 124 are electrically connected respectively.

As shown in FIG. 4E, the first insulating layer 152 and the second insulating layer 154 covering the first circuit wiring 122 and the second circuit wiring 124 are formed. Solder resists may be used for the first and second insulating layers 152 and 154.

In the above-described manufacturing method, although shown and described as attaching the individual semiconductor chip on the substrate, the process of attaching the semiconductor chip on the substrate is preferably carried out at the wafer level, it is separated to the chip level through the sawing process It is preferable to attach to the substrate or the first and second dielectric layers after the process.

As described above, the semiconductor package according to the embodiment of the present invention can be manufactured.

Therefore, the present invention has the advantage of preventing the generation of voids due to the insertion of the semiconductor chip by wrapping the semiconductor chip with a sealing agent in a state in which the semiconductor chips are attached to contact with each other.

As a result, it is possible to actively cope with the manufacture of a thin semiconductor package with the effect of minimizing the thickness of the semiconductor chip.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

1 is a cross-sectional view showing a stack-type semiconductor package using a metal wire according to the prior art.

Figure 2a is a cross-sectional view showing a semiconductor package according to the present invention.

Figure 2b is a cross-sectional view showing a stacked semiconductor package according to the present invention.

3A through 3D are cross-sectional views of respective semiconductor packages according to an application of the present invention.

4A through 4E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention, in a process order.

Claims (13)

A first semiconductor chip and a second semiconductor chip each having one surface on which a bonding pad is disposed and the other surface opposite thereto, and the other surfaces being in contact with each other; A first dielectric layer and a second dielectric layer formed to surround each other and surround the first semiconductor chip and the second semiconductor chip; First and second circuit wiring lines formed on the exposed surfaces of the first and second dielectric layers, respectively, and connected to the bonding pads of the first semiconductor chip and the bonding pads of the second semiconductor chip; And An insulating layer formed to expose portions of the first circuit wiring and the second circuit wiring, respectively, on exposed surfaces of the first dielectric layer and the second dielectric layer including the first circuit wiring and the second circuit wiring; A semiconductor package comprising a. The semiconductor device of claim 1, further comprising: a first via electrode connected to the bonding pads of the first and second semiconductor chips, and the first and second dielectric layers, respectively, to electrically connect the first and second circuit wires. And a second via electrode for connecting. The semiconductor device of claim 1, further comprising: at least one third semiconductor chip stacked in a face-up type on the insulation layer on the first dielectric layer or the second dielectric layer; A connection member electrically connecting the third semiconductor chip and the first circuit wiring or the second circuit wiring corresponding thereto; An encapsulation member sealing an exposed surface of the first dielectric layer or the second dielectric layer including the at least one third semiconductor chip and the connection member; And An external connection terminal attached to the first circuit wiring or the second circuit wiring exposed by the insulating layer; The semiconductor package further comprises. The semiconductor package of claim 3, wherein the connection member comprises a metal wire. The semiconductor device of claim 1, further comprising: a third semiconductor chip flip-bonded on the insulating layer on the first dielectric layer or the second dielectric layer; At least one fourth semiconductor chip stacked in a face-up type on the third semiconductor chip; A connection member electrically connecting the fourth semiconductor chip and the first circuit wiring or the second circuit wiring corresponding thereto; An encapsulation member sealing an exposed surface of the first dielectric layer or the second dielectric layer including the third semiconductor chip, at least one of the fourth semiconductor chips, and the connection member; And An external connection terminal attached to the first circuit wiring or the second circuit wiring exposed by the insulating layer; The semiconductor package further comprises. In a semiconductor package in which at least two package units are stacked via a connection member, The package unit, A first semiconductor chip and a second semiconductor chip each having one surface on which a bonding pad is disposed and the other surface opposite thereto, and the other surfaces being in contact with each other; A first dielectric layer and a second dielectric layer formed to surround each other and surround the first semiconductor chip and the second semiconductor chip; First and second circuit wiring lines formed on the exposed surfaces of the first and second dielectric layers, respectively, and connected to the corresponding bonding pads of the first semiconductor chip and the bonding pads of the second semiconductor chip; And An insulating layer formed to expose portions of the first circuit wiring and the second circuit wiring, respectively, on exposed surfaces of the first dielectric layer and the second dielectric layer including the first circuit wiring and the second circuit wiring; A semiconductor package comprising a. The semiconductor package of claim 6, wherein the connection member is a solder ball or a bump. 7. The semiconductor package according to claim 6, further comprising an adhesive member interposed between the abutting portions of the package units. Attaching an upper surface of the first semiconductor chip to an upper surface of the substrate; Forming a lower surface of the first dielectric layer on an upper surface of the substrate including the first semiconductor chip; Forming a first circuit wiring on an upper surface of the first dielectric layer; Removing the substrate; Attaching a lower surface of the second semiconductor chip to the lower surface of the first semiconductor chip; Forming an upper surface of the second dielectric layer on a lower surface of the first dielectric layer including the second semiconductor chip; And Forming a second circuit wiring on a lower surface of the second dielectric layer; Method of manufacturing a semiconductor package comprising a. The method of claim 9, wherein the first and second dielectric layers are formed of any one selected from a group of insulating materials including polyimide, benzocyclobutene, and epoxy resin. The method of claim 9, after the forming of the second circuit wiring, passes through the first via electrode connected to the bonding pads of the first and second semiconductor chips and the first and second dielectric layers, respectively. And forming a second via electrode electrically connecting the first and second circuit wirings. 12. The method of claim 11, further comprising, after forming the first and second via electrodes, forming first and second insulating layers covering the first and second circuit wirings, respectively. Method of manufacturing a semiconductor package. The method of claim 12, wherein the first and second insulating layers are formed of a solder resist.

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