CN212750883U - Lead bonding and flip-chip bonding hybrid integrated structure - Google Patents

Lead bonding and flip-chip bonding hybrid integrated structure Download PDF

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Publication number
CN212750883U
CN212750883U CN202022098382.XU CN202022098382U CN212750883U CN 212750883 U CN212750883 U CN 212750883U CN 202022098382 U CN202022098382 U CN 202022098382U CN 212750883 U CN212750883 U CN 212750883U
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chip
flip
bonding
wire
bonded
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CN202022098382.XU
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朱召贤
徐衡
朱家昌
张爱兵
明雪飞
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The utility model discloses a lead bonding and flip-chip bonding hybrid integrated structure, which belongs to the field of integrated circuit packaging and comprises an organic substrate, a flip-chip bonding chip and a lead bonding chip; the flip chip is flip-chip bonded on the organic substrate through the metal bumps. A wire-bond chip is placed on top of the flip-chip and is interconnected with the organic substrate by gold wires. The utility model discloses not only can provide the effective protection to integrated circuit chip, through the advantage of integrating two kinds of integrated configuration of lead bonding and flip-chip bonding, realize that the solid of multicore piece piles up simultaneously, reach the purpose that the subassembly is miniaturized, multi-functional and high reliability.

Description

Lead bonding and flip-chip bonding hybrid integrated structure
Technical Field
The utility model relates to an integrated circuit packaging technology field, in particular to lead bonding and flip-chip bonding mix integrated configuration.
Background
With the development of ultra-light weight, miniaturization and multi-functionalization of electronic equipment, the work of ensuring high reliability of integrated circuit chips becomes the key point of research. At present, a common packaging form in the integrated circuit packaging technology is to use a wire bonding technology to interconnect a chip and a substrate on an organic substrate.
The wire bonding technology is relatively mature, and the adaptability of a new device is high, but the I/O number of a chip adopting a wire bonding packaging form is usually 50-540, so that the packaging of a high-density functional chip is difficult to meet; in addition, because the areas of the bonding pads on the chip and the substrate are small, the chopper used in the precise distance welding is a bottle neck type chopper, the diameter of the head is small, and the small-diameter head of the chopper and the narrow pin lead cause the cross-sectional area of the welding point on the substrate to be small, so that the bonding strength is influenced.
In recent years, research and development of solder bump type flip chips are rapidly increased, the flip chip technology can overcome the problem of the center distance limit of a wire bonding pad, the I/O number of the flip chip is usually more than 540, and the size of a package body is small, so that the flip chip technology can play an irreplaceable role in the packaging of high-frequency and high-power devices. However, the flip chip bumps are made in a previous process and are therefore costly. In summary, both package structures have their own advantages and limitations, and the choice of which interconnection method is chosen depends on the physical properties of the package substrate material used and the application conditions of the device.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a lead bonding and flip-chip bonding mix integrated configuration to overcome the problem that exists in current lead bonding and the flip-chip bonding interconnection form.
In order to solve the technical problem, the utility model provides a lead bonding and flip-chip bonding mix integrated configuration, include:
an organic substrate;
the flip chip is flip-chip welded on the organic substrate through the metal bumps;
a wire-bonded chip disposed on top of the flip chip, and the wire-bonded chip is interconnected with the organic substrate by gold wires.
Optionally, the organic substrate includes bonding fingers, and the bonding fingers are bonded and interconnected with the wire bonding chip through the gold wires.
Optionally, the bonding connection mode of the wire bonding chip and the bonding fingers includes two types, namely thermal compression bonding and ultrasonic bonding.
Optionally, the wire-bond chip is bonded to the flip chip through a die attach film on a back surface of the wire-bond chip.
Optionally, the flip chip and the hole of the organic substrate are filled with filling glue.
Optionally, a plurality of solder balls are soldered to the bottom of the organic substrate to achieve interconnection between board levels.
Optionally, the solder ball has a composition of Sn63Pb37 or Sn90Pb 10.
Optionally, the diameter of the solder ball is 0.25 mm.
Optionally, the metal bump is made of one of Cu, Ni, or SnAg.
Optionally, the gold wire is made of gold wire, copper wire or aluminum wire.
Optionally, the diameter of the gold wire is 0.8 mils.
The utility model provides a lead bonding and flip-chip bonding hybrid integrated structure, which comprises an organic substrate, a flip-chip bonding chip and a lead bonding chip; the flip chip is flip-chip bonded on the organic substrate through the metal bumps. A wire-bond chip is placed on top of the flip-chip and is interconnected with the organic substrate by gold wires.
The utility model discloses following beneficial effect has:
(1) compared with the traditional single interconnection packaging structure, the utility model integrates two interconnection forms of lead bonding and flip-chip bonding, and can specifically select the corresponding interconnection form by combining the I/O number of the packaged chip, thereby realizing the optimal combination of multi-chip interconnection;
(2) bonding wires used by the hybrid integrated structure can be gold wires, copper wires and aluminum wires, and the bonding modes include a hot-press bonding mode and an ultrasonic bonding mode; the process has good matching performance and is suitable for packaging various devices and products.
Drawings
Fig. 1 is a schematic structural view of a hybrid integrated structure of wire bonding and flip chip bonding provided by the present invention;
fig. 2 is a plan view of an organic substrate.
Detailed Description
The present invention provides a hybrid integrated structure of wire bonding and flip chip bonding, which is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
The utility model provides a lead bonding and flip-chip bonding hybrid integrated structure, the structure of which is shown in figure 1 and comprises an organic substrate 2, a flip-chip bonding chip 7 and a lead bonding chip 9; the flip chip 7 is flip-chip bonded on the organic substrate 2 through the metal bumps 5; the metal bump 5 is made of one of Cu, Ni and SnAg. The wire-bond chip 9 is placed on top of the flip-chip 7 and the wire-bond chip 9 is interconnected with the organic substrate 2 by gold wires 4.
As shown in fig. 2, the organic substrate 2 includes bonding fingers 3, and the metal bumps 5 are also located on the organic substrate 2. The bonding fingers 3 are bonded and interconnected with the wire bonding chip 9 through the gold wires 4; the bonding connection mode of the lead bonding chip 9 and the bonding fingers 3 is hot-press bonding or ultrasonic bonding. The gold thread 4 is made of gold thread, copper wire or aluminum wire.
With continued reference to fig. 1, the wire bond chip 9 is bonded to the flip chip 7 through the die attach film 8 on the back side thereof. The flip chip 7 and the pores of the organic substrate 2 are filled with filling glue 6. The bottom of the organic substrate 2 is welded with a plurality of solder balls 1 for realizing interconnection between board levels; wherein the solder ball 1 has a composition of Sn63Pb37 or Sn90Pb 10.
The utility model discloses well organic substrate 2's size has decided whole mixed integrated packaging structure's size of a dimension, and in this embodiment, whole packaging structure's size is 12 x 12mm, and thickness is 255 mu m. The diameter of the solder ball 1 soldered under the organic substrate 2 was 0.25 mm. Wherein the flip chip 7 is mounted on the organic substrate 2 by flip chip bonding, the size of the flip chip 7 can be 6 × 6 × 0.15mm, and the diameter of the metal bump 5 under the flip chip 7 is 30 μm. The gap between the flip chip 7 and the organic substrate 2 is filled with a filling adhesive 6. A wire-bonded chip 9 having dimensions of 5 × 5 × 0.1mm is then bonded to the flip chip 7 through the die attach film 8 on the back side. The diameter of the gold wire 4 used for connecting the wire bonding chip 9 and the organic substrate 2 is 0.8 mils.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims (11)

1. A hybrid wire-bond and flip-chip integrated structure comprising:
an organic substrate (2);
the flip chip (7) is flip-chip welded on the organic substrate (2) through metal bumps (5);
a wire-bond chip (9) placed on top of the flip-chip (7), and the wire-bond chip (9) is interconnected with the organic substrate (2) by gold wires (4).
2. The hybrid wire-bonded and flip-chip bonded integrated structure of claim 1, wherein the organic substrate (2) comprises bonding fingers (3), the bonding fingers (3) being bonded and interconnected with the wire-bonded chip (9) by the gold wires (4).
3. The hybrid wire-bonded and flip-chip bonded integrated structure of claim 2, wherein the bonding connection of the wire-bonded chip (9) and the bonding fingers (3) comprises both thermocompression bonding and ultrasonic bonding.
4. The hybrid wire-bond and flip-chip bonding integrated structure according to claim 1, wherein the wire-bond chip (9) is bonded to the flip-chip bonding chip (7) through a die attach film (8) on a back surface thereof.
5. The hybrid wire-bond and flip-chip integrated structure according to claim 1, wherein the voids of the flip-chip (7) and the organic substrate (2) are filled with an underfill (6).
6. The hybrid wire-bonded and flip-chip bonded integrated structure of claim 1, wherein a plurality of solder balls (1) are bonded to the bottom of the organic substrate (2) for realizing interconnection between board levels.
7. The hybrid wire-bonded and flip-chip bonded integrated structure of claim 6, wherein the composition of the solder ball (1) is Sn63Pb37 or Sn90Pb 10.
8. Hybrid wire-bond and flip-chip integrated structure according to claim 6, characterized in that the solder ball (1) has a diameter of 0.25 mm.
9. The hybrid wire-bond and flip-chip bonding integrated structure according to claim 1, wherein the composition of the metal bump (5) is one of Cu, Ni or SnAg.
10. The hybrid wirebond and flip-chip bonding integrated structure according to claim 1, wherein the gold wires (4) are gold wires, copper wires, or aluminum wires.
11. The hybrid wire-bond and flip-chip integrated structure of claim 1, wherein the gold wire (4) has a diameter of 0.8 mils.
CN202022098382.XU 2020-09-23 2020-09-23 Lead bonding and flip-chip bonding hybrid integrated structure Active CN212750883U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192936A (en) * 2021-04-23 2021-07-30 泓林微电子（昆山）有限公司 Double-sided chip packaging structure
CN113589449A (en) * 2021-06-21 2021-11-02 北京协同创新研究院 Hybrid integrated system applied to photoelectric interconnection
CN115881559A (en) * 2023-01-18 2023-03-31 中科亿海微电子科技（苏州）有限公司 FPGA chip, packaging method thereof and substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192936A (en) * 2021-04-23 2021-07-30 泓林微电子（昆山）有限公司 Double-sided chip packaging structure
CN113589449A (en) * 2021-06-21 2021-11-02 北京协同创新研究院 Hybrid integrated system applied to photoelectric interconnection
CN115881559A (en) * 2023-01-18 2023-03-31 中科亿海微电子科技（苏州）有限公司 FPGA chip, packaging method thereof and substrate
CN115881559B (en) * 2023-01-18 2023-09-15 中科亿海微电子科技（苏州）有限公司 FPGA chip, packaging method thereof and substrate

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