CN218333753U

CN218333753U - Chip fan-out type low-thickness packaging structure

Info

Publication number: CN218333753U
Application number: CN202221676914.6U
Authority: CN
Inventors: 李太龙; 邵滋人; 付永朝
Original assignee: Unimos Microelectronics(shanghai) Ltd
Current assignee: Unimos Microelectronics(shanghai) Ltd
Priority date: 2022-07-01
Filing date: 2022-07-01
Publication date: 2023-01-17
Anticipated expiration: 2032-07-01

Abstract

The utility model belongs to the technical field of the semiconductor packaging technique and specifically relates to a chip fan-out type low thickness packaging structure. The utility model provides a chip fan-out type low thickness packaging structure, packaging structure includes first rewiring layer, function chip lamination, first encapsulated layer, the top of first rewiring layer is equipped with function chip lamination, and the first encapsulated layer of outside parcel of function chip lamination, function chip lamination comprises a plurality of function chips, a plurality of function chips are echelonment dislocation distribution, lower extreme one side of function chip is equipped with the pad, the pad of function chip passes through conductive structure and is connected with first rewiring layer electricity. Compared with the prior art, the utility model discloses the thickness of attenuate packaging body adopts deep hole conducting structure or metal connecting post to make function chip and external implementation electricity be connected, has improved the functioning speed of product greatly, and reinforcing data processing ability adopts fan-out type encapsulation, has reduced the area of packaging body.

Description

Chip fan-out type low thickness packaging structure

Technical Field

The utility model belongs to the technical field of the semiconductor packaging technique and specifically relates to a chip fan-out type low thickness packaging structure.

Background

In the conventional chip packaging, a chip is directly attached to the surface of a substrate, and then a metal wire bonding process is adopted to realize electrical connection between a chip bonding pad and the substrate. The substrate is used as one of core materials of the chip package, and the cost of the substrate accounts for 30% -50% of the cost of the whole packaging material. In order to cope with the development of electronic devices towards diversification, miniaturization and functionalization, the design in the substrate is more and more complicated, and the number of layers is increased, which not only increases the thickness of the substrate, affects the overall package thickness, but also leads to further increase of the price of the substrate. In addition, the conventional bonding process of metal wires also causes time delay of the product, resulting in inefficiency.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model discloses a chip fan-out type low thickness packaging structure adopts deep hole conducting structure or metal connecting post to make function chip and external implementation electricity be connected, has improved the functioning speed of product greatly, reinforcing data processing ability.

The utility model provides a chip fan-out type low thickness packaging structure, packaging structure includes first rewiring layer, function chip lamination, first encapsulated layer, the top of first rewiring layer is equipped with function chip lamination, the first encapsulated layer of function chip lamination's outside parcel, function chip lamination comprises a plurality of function chips, a plurality of function chips are echelonment dislocation distribution, lower extreme one side of function chip is equipped with the pad, the pad of function chip passes through conducting structure and is connected with first rewiring layer electricity, the lower extreme of first rewiring layer is equipped with metal convex block.

Furthermore, a control chip is arranged between the first rewiring layer and the functional chip laminated structure, the upper end of the control chip is bonded with the functional chip laminated structure, and the lower end of the control chip is electrically connected with the first rewiring layer.

Furthermore, a second rewiring layer is arranged at the upper end of the first packaging layer, a control chip is arranged above the second rewiring layer, the second packaging layer is wrapped outside the control chip, and the first rewiring layer is connected with the second rewiring layer through a second conductive structure.

Further, the control chip is electrically connected with the second rewiring layer.

Compared with the prior art, the utility model discloses a there is following beneficial effect:

1) The first rewiring layer is used for replacing a substrate structure, so that the packaging cost is reduced, and the thickness of the packaging body is reduced;

2) The functional chip is electrically connected with the outside by adopting a deep hole conductive structure or a metal connecting column, so that the running speed of the product is greatly improved, and the data processing capacity is enhanced;

3) And the fan-out type packaging is adopted, so that the area of a packaging body is effectively reduced.

Drawings

Fig. 1 is a schematic structural diagram of the chip fan-out type low-thickness package structure of the present invention.

Fig. 2 is a schematic structural diagram of the chip fan-out type low-thickness package structure of the present invention.

Fig. 3 is a third schematic structural view of the chip fan-out type low-thickness package structure of the present invention.

Fig. 4 is the functional chip lamination structure diagram of the chip fan-out type low thickness package structure of the present invention.

Detailed Description

The present invention will now be further described with reference to the accompanying drawings.

Referring to fig. 1, the utility model relates to a chip fan-out type low thickness packaging structure, packaging structure includes first rewiring layer 1, function chip lamination 2, first encapsulated layer 3, the top of first rewiring layer 1 is equipped with function chip lamination 2, the first encapsulated layer 3 of outside parcel of function chip lamination 2, function chip lamination 2 comprises a plurality of function chips 4, a plurality of function chips 4 are echelonment dislocation distribution, lower extreme one side of function chip 4 is equipped with pad 5, pad 5 of function chip 4 is connected with first rewiring layer 1 electricity through conducting structure 6, the lower extreme of first rewiring layer 1 is equipped with metal convex block 7. As shown in figure 1.

Be equipped with control chip 8 between first rewiring layer 1 and the function chip lamination 2, control chip 8's upper end and function chip lamination 2 splice, control chip 8's lower extreme is connected with first rewiring layer 1 electricity. As shown in fig. 2.

The upper end of the first packaging layer 3 is provided with a second rewiring layer 9, a control chip 8 is arranged above the second rewiring layer 9, the second packaging layer 10 is wrapped outside the control chip 8, and the first rewiring layer 1 is connected with the second rewiring layer 9 through a second conducting structure 11. As shown in fig. 3.

The control chip 8 is electrically connected to the second rewiring layer 9.

The first rewiring layer 1 comprises a dielectric layer and a metal wiring layer, the dielectric layer is made of one or a combination of more than one of polyimide, epoxy resin, silicon oxide and silica gel, and the metal wiring layer comprises one or a combination of more than one of copper, nickel, gold, silver and titanium.

The first rewiring layer 1 is electrically connected with the functional chip 4 through the conductive structure 6 relative to the second surface, and then is connected with the outside through the metal bump 7 on the first surface.

The conductive structure 6 is formed in the deep hole by drilling a hole on the first packaging layer 3 by using laser and then adopting the processes of sputtering, electroplating or chemical plating and the like;

the conductive structure 6 may also be a metal pillar, and before packaging, the metal pillar may be formed on the surface of the chip by using a sputtering process or an electroplating process;

the material of the conductive structure 6 can be one or more of copper, nickel, gold, silver and titanium;

the functional chip 4 may be a memory chip, and the pads 5 on the first surface of the functional chip 4 are all electrically connected to the second surface of the first redistribution layer 1 through the conductive structures 6.

The material of the first packaging layer 3 is resin, and the metal bump 7 is a solder ball.

Claims

1. A chip fan-out type low thickness packaging structure which characterized in that: packaging structure includes first rewiring layer (1), function chip lamination (2), first encapsulation layer (3), the top of first rewiring layer (1) is equipped with function chip lamination (2), the first encapsulation layer (3) of outside parcel of function chip lamination (2), function chip lamination (2) comprise a plurality of function chips (4), a plurality of function chips (4) are echelonment dislocation distribution, lower extreme one side of function chip (4) is equipped with pad (5), pad (5) of function chip (4) are connected with first rewiring layer (1) electricity through conducting structure (6), the lower extreme of first rewiring layer (1) is equipped with metal convex block (7).

2. The chip fan-out low thickness package structure of claim 1, wherein: be equipped with control chip (8) between first rewiring layer (1) and function chip lamination (2), the upper end and the function chip lamination (2) of control chip (8) splice, the lower extreme and the first rewiring layer (1) electricity of control chip (8) are connected.

3. The chip fan-out low thickness package structure of claim 1, wherein: the upper end of the first packaging layer (3) is provided with a second rewiring layer (9), a control chip (8) is arranged above the second rewiring layer (9), the second packaging layer (10) is wrapped outside the control chip (8), and the first rewiring layer (1) is connected with the second rewiring layer (9) through a second conductive structure (11).

4. The chip fan-out low thickness package structure of claim 3, wherein: the control chip (8) is electrically connected with the second rewiring layer (9).