CN216871944U

CN216871944U - Chip packaging device for chip processing

Info

Publication number: CN216871944U
Application number: CN202123374742.5U
Authority: CN
Inventors: 陈力颖
Original assignee: Tianjin Lixin Weiye Technology Co ltd
Current assignee: Tianjin Lixin Weiye Technology Co ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-07-01
Anticipated expiration: 2031-12-30

Abstract

The utility model relates to the technical field of chip packaging, in particular to a chip packaging device for chip processing, which comprises a chip, wherein a wiring layer is arranged at the lower part of the chip, a first packaging layer is wrapped at the edge of the chip and covers the wiring layer downwards at the same time, a second packaging layer is wrapped at the upper part of the chip and is provided with a hole, a conductive post is arranged in the hole, a lead is connected to the upper surface of the chip and is connected to the upper end of the conductive post, the wiring layer is coupled with the lower surface of the chip and the lower end of the conductive post, and the first packaging layer, the lead and the conductive post are covered downwards at the same time by the second packaging layer. According to the utility model, substrate switching is omitted, so that the chip packaging is lighter and smaller, and the adaptation requirement of small electronic products is met.

Description

Chip packaging device for chip processing

Technical Field

The utility model relates to the technical field of chip packaging, in particular to a chip packaging device for chip processing.

Background

Semiconductors are widely used in various intelligent electronic products, and the integration of intelligent systems has continuously increased requirements on the functional density and performance of electronic component products in unit area, which puts higher requirements on the chip packaging and manufacturing process with continuously reduced component size. The conventional chip package is mounted by using a substrate, so that the height of a packaging layer is increased, the size of the packaging layer is increased, and the adaptation requirement of a small electronic product is difficult to meet.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to a chip packaging apparatus for chip processing, so as to solve the problems in the background art.

In order to achieve the purpose, the utility model provides the following technical scheme: the utility model provides a chip packaging hardware for chip processing, includes the chip, the lower part of chip is provided with the wiring layer, the edge cladding of chip has first encapsulated layer, first encapsulated layer covers downwards simultaneously the wiring layer, the upper portion cladding of chip has the second encapsulated layer, set up the hole in the first encapsulated layer, be provided with in the hole and lead electrical pillar, the higher authority of chip is connected with the wire, the wire is connected to lead the upper end of electrical pillar, the wiring layer with the lower face of chip, the lower extreme coupling of electrical pillar, the second encapsulated layer covers downwards simultaneously first encapsulated layer the wire with lead electrical pillar.

Optionally, the upper portion of the second encapsulation layer is coated with a protection layer, and the protection layer, the second encapsulation layer and the first encapsulation layer are made of resin.

Optionally, a nano-silica layer is disposed in the protective layer.

Optionally, the second encapsulation layer and the protective layer are thick in the middle and thin on two sides.

Optionally, a solder ball is disposed at a lower portion of the wiring layer, and the solder ball is coupled to the lower surface of the chip and the lower end of the conductive pillar through the wiring layer.

Compared with the prior art, the utility model has the following beneficial effects:

1. according to the utility model, substrate switching is omitted, so that the chip packaging is lighter and smaller, and the adaptation requirement of small electronic products is met.

2. According to the utility model, the wiring layer is arranged below the chip, so that the input/output ports of the chip can be rearranged, and the input/output ports of the chip can be arranged in a region with loose pitch station positions, and the layout flexibility of the packaging structure is improved.

3. According to the utility model, the chip can be covered by two layers of packaging, the protective layer is arranged outside the uppermost packaging layer, and the nano silicon dioxide particles are mixed in the protective layer, so that the dispersibility is better, and the rigidity, the heat resistance, the impact strength, the tensile strength and the like of the protective layer can be improved.

Drawings

FIG. 1 is a cross-sectional structural view of a first package layer and a second package layer according to the present invention;

fig. 2 is a schematic cross-sectional structural view of a protection layer covering an upper portion of a second encapsulation layer according to the present invention.

In the figure: 1. a chip; 2. a wiring layer; 3. a first encapsulation layer; 4. a second encapsulation layer; 5. an aperture; 6. a conductive post; 7. a wire; 8. a protective layer; 9. a nano-silica layer; 10. and (7) solder balls.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example (b): referring to fig. 1 to 2, the present invention provides a chip packaging apparatus for chip processing, including a chip 1, a wiring layer 2 is disposed at a lower portion of the chip 1, in an embodiment, the wiring layer 2 may be one or more layers, and a redistribution of input/output ports of the chip 1 may be implemented so as to be arranged in a region with loose pitch station, thereby improving layout flexibility of the packaging structure, in an embodiment, the material of the wiring layer 2 may be one of aluminum, gold, chromium, or tungsten, or an alloy of the foregoing metals.

The edge of the chip 1 is coated with a first encapsulation layer 3, the first encapsulation layer 3 simultaneously covers the wiring layer 2 downward, and the first encapsulation layer 3 is made of resin, and in a specific embodiment, the first encapsulation layer 3 can be formed by injecting resin into the edge of the chip 1 and curing the resin; the height of the first encapsulation layer 3 may be slightly lower than the upper face of the chip 1 or flush with the upper face of the chip 1 so as to expose the pads of the chip 1 upward.

Forming a hole 5 in the first encapsulation layer 3, and providing a conductive pillar 6 in the hole 5, in a specific embodiment, the hole 5 may be formed by laser drilling, and then inserting the formed conductive pillar 6 into the hole 5 or filling the conductive pillar 6 into the hole 5 for curing; for example, the conductive post 6 may be formed by pouring conductive paste into the hole 5 and curing; the upper surface of the chip 1 is connected with a conducting wire 7, the conducting wire 7 is connected to the upper end of the conductive column 6, the wiring layer 2 is coupled with the lower surface of the chip 1 and the lower end of the conductive column 6, and in a specific embodiment, the conducting wire 7 can be a gold wire or an aluminum wire; the lower part of the wiring layer 2 is provided with a solder ball 10, the solder ball 10 is coupled with the lower surface of the chip 1 and the lower end of the conductive column 6 through the wiring layer 2, and the bonding pad of the chip 1 can be led out through the lead 7, the conductive column 6 and the solder ball 10, so that the fan-out of the chip pin is realized.

The upper part of the chip 1 is coated with a second packaging layer 4, and the second packaging layer 4 simultaneously covers the first packaging layer 3, the conducting wires 7 and the conducting posts 6 downwards; the material of the second encapsulation layer 4 is resin, and in a specific embodiment, the second encapsulation layer may be formed by injecting resin into the upper portion of the chip 1 and then curing the resin.

The upper portion of the second encapsulation layer 4 is coated with a protection layer 8, the protection layer 8 is made of resin and plays a role in protecting the encapsulation layer, and in a specific embodiment, the protection layer can be formed by pouring resin onto the second encapsulation layer 4 and curing the resin, or formed in a corresponding mold and then covered; the middle of the second packaging layer 4 and the protective layer 8 is thick, and the two sides are thin and are crescent, the middle is thick, so that the protective performance can be improved, and the two sides are thin, so that the heat conduction speed can be improved, and the heat dissipation can be enhanced; the nano silicon dioxide layer 9 is arranged in the protective layer 8, and the nano silicon dioxide layer 9 is nano silicon dioxide particles, so that the dispersibility is better, the rigidity of the protective layer 8 can be improved, the impact energy can be absorbed, and the heat resistance, the impact strength, the tensile strength and the like can be improved.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A chip packaging arrangement for chip processing, comprising a chip (1), characterized in that: the chip packaging structure is characterized in that a wiring layer (2) is arranged on the lower portion of the chip (1), a first packaging layer (3) wraps the edge of the chip (1), the first packaging layer (3) simultaneously covers the wiring layer (2) downwards, a second packaging layer (4) wraps the upper portion of the chip (1), a hole (5) is formed in the first packaging layer (3), a conductive post (6) is arranged in the hole (5), a lead (7) is connected to the upper surface of the chip (1), the lead (7) is connected to the upper end of the conductive post (6), the wiring layer (2) is coupled with the lower surface of the chip (1) and the lower end of the conductive post (6), and the second packaging layer (4) simultaneously covers the first packaging layer (3), the lead (7) and the conductive post (6) downwards.

2. The chip packaging apparatus for chip processing according to claim 1, wherein: the upper portion of second encapsulating layer (4) cladding has protective layer (8), second encapsulating layer (4) and first encapsulating layer (3)'s material is resin.

3. The chip packaging apparatus for chip processing according to claim 2, wherein: and a nano silicon dioxide layer (9) is arranged in the protective layer (8).

4. The chip packaging apparatus for chip processing according to claim 2, wherein: the second packaging layer (4) and the protective layer (8) are thick in the middle and thin on two sides.

5. The chip packaging apparatus for chip processing according to claim 1, wherein: the lower part of the wiring layer (2) is provided with a solder ball (10), and the solder ball (10) is coupled with the lower surface of the chip (1) and the lower end of the conductive column (6) through the wiring layer (2).