CN218333754U - Chip fan-out type low-thickness packaging structure with bidirectional laminated sheets - Google Patents
Chip fan-out type low-thickness packaging structure with bidirectional laminated sheets Download PDFInfo
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- CN218333754U CN218333754U CN202221678401.9U CN202221678401U CN218333754U CN 218333754 U CN218333754 U CN 218333754U CN 202221678401 U CN202221678401 U CN 202221678401U CN 218333754 U CN218333754 U CN 218333754U
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Abstract
The utility model belongs to the technical field of the semiconductor packaging technique and specifically relates to a chip fan-out type low thickness packaging structure of two-way lamination. The utility model provides a chip fan-out type low thickness packaging structure of two-way lamination, includes first rewiring layer, second rewiring layer, control chip, function chip laminated structure, first packaging layer, second packaging layer, the top of first rewiring layer is equipped with function chip laminated structure, and the first packaging layer of outside parcel of function chip laminated structure, the upper end of first packaging layer is equipped with second rewiring layer, and the top of second rewiring layer is equipped with control chip, function chip laminated structure is piled up by a plurality of positive and negative function chip groups and is constituteed. Compared with the prior art, the utility model discloses packaging structure adopts second rewiring layer and conductive structure to realize inside interconnection, adopts first rewiring layer to replace the base plate to realize external connection, adopts three-dimensional packaging structure that piles up, reduces the volume of encapsulation.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor packaging technique and specifically relates to a chip fan-out type low thickness packaging structure of two-way lamination.
Background
In the conventional chip package, a chip is directly attached to the surface of a substrate, and then the electrical connection between a chip pad and the substrate is realized by adopting a metal wire bonding process. The substrate is used as one of core materials of the chip package, and the cost of the substrate accounts for 30% -50% of the cost of the whole packaging material. In order to deal with the development of diversification, miniaturization and functionalization of electronic devices, the design of the substrate is more and more complicated, and the number of layers is increased, which not only increases the thickness of the substrate, affects the overall package thickness, but also further increases the price of the substrate. In addition, the conventional bonding process of metal wires also causes time delay of the product, resulting in inefficiency.
Disclosure of Invention
In order to solve the technical problem, the utility model discloses a chip fan-out type low thickness packaging structure of two-way lamination adopts second rewiring layer and conductive structure to realize inside interconnection, adopts first rewiring layer to replace the base plate to realize external connection, reduces the cost of encapsulation.
The utility model provides a chip fan-out type low thickness packaging structure of two-way lamination, including first rewiring layer, second rewiring layer, control chip, function chip laminated structure, first encapsulated layer, second encapsulated layer, the top of first rewiring layer is equipped with function chip laminated structure, the first encapsulated layer of outside parcel of function chip laminated structure, and the upper end of first encapsulated layer is equipped with second rewiring layer, and the top of second rewiring layer is equipped with control chip, control chip's outside parcel second encapsulated layer, be connected through conductive structure one electricity between first rewiring layer and the function chip laminated structure, be connected through conductive structure two electricity between second rewiring layer and the function chip laminated structure, be connected through conductive structure three electricity between first rewiring layer and the second rewiring layer, function chip laminated structure piles up by a plurality of positive and negative functions and constitutes.
Furthermore, the positive and negative functional chip groups are distributed in a stepped staggered manner and comprise positive chips and negative chips, the first rewiring layer is electrically connected with the positive chips through the first conductive structures, the negative chips are arranged on one sides of the positive chips, and the negative chips are electrically connected with the second rewiring layer through the second conductive structures.
Further, a metal bump is arranged at the lower end of the first rewiring layer.
Further, the control chip is electrically connected with the second rewiring layer.
Compared with the prior art, the utility model discloses a there is following beneficial effect:
1) The utility model discloses packaging structure adopts second rewiring layer and conductive structure to realize internal interconnection, adopts first rewiring layer to replace the base plate and realizes external connection, reduces the cost of encapsulation;
2) The chip is electrically connected with the outside by adopting a deep hole conductive structure or a metal connecting column, so that the running speed of the product is greatly improved, and the data processing capacity is enhanced;
3) The utility model discloses a three-dimensional packaging structure that piles up integrates the chip of different functions together, has not only improved the integrated level of encapsulation, still reduces the volume of encapsulation. Through transversely arranging the lamination with functional chip, the further effectual thickness that thins the packaging body.
Drawings
Fig. 1 is the structure schematic diagram of the chip fan-out type low thickness packaging structure of the bidirectional lamination of the present invention.
Fig. 2 is the functional chip lamination structure diagram of the chip fan-out type low thickness package structure of the bidirectional lamination of the present invention.
Detailed Description
The present invention will now be further described with reference to the accompanying drawings.
Referring to fig. 1, the utility model relates to a chip fan-out type low thickness packaging structure of two-way lamination, including first rewiring layer 1, second rewiring layer 2, control chip 3, function chip laminated structure 4, first encapsulated layer 5, second encapsulated layer 6, first rewiring layer 1's top is equipped with function chip laminated structure 4, and function chip laminated structure 4's outside parcel first encapsulated layer 5, first encapsulated layer 5's upper end is equipped with second rewiring layer 2, and second rewiring layer 2's top is equipped with control chip 3, and control chip 3's outside parcel second encapsulated layer 6, be connected through conductive structure one 7 electricity between first rewiring layer 1 and the function chip laminated structure 4, be connected through conductive structure two 8 electricity between second rewiring layer 2 and the function chip laminated structure 4, be connected through conductive structure three 9 electricity between first rewiring layer 1 and the second rewiring layer 2, function chip laminated structure 4 piles up by a plurality of positive and negative functions 10 and constitutes.
The positive and negative functional chip groups 10 are distributed in a stepped staggered manner, each positive and negative functional chip group 10 comprises a positive chip 11 and a negative chip 12, the first rewiring layer 1 is electrically connected with the positive chip 11 through a first conductive structure 7, the negative chip 12 is arranged on one side of the positive chip 11, and the negative chip 12 is electrically connected with the second rewiring layer 2 through a second conductive structure 8. The lower end of the first rewiring layer 1 is provided with a metal bump 13. The control chip 3 is electrically connected to the second rewiring layer 2.
The positive and negative functional chip sets 10 are connected through a die attached film DAF, and the thickness of the die attached film DAF is 10 micrometers.
The utility model discloses a three-dimensional packaging structure that piles up, the chip integration with different functions is in the same place, has improved the integrated level of encapsulation, secondly connects through conductive structure, can improve the storage speed of chip greatly, reinforcing data processing ability.
The first rewiring layer 1 and the second rewiring layer 2 comprise dielectric layers and metal wiring layers, the dielectric layers are made of one or a combination of more than one of polyimide, epoxy resin, silicon oxide and silica gel, and the metal wiring layers comprise one or a combination of more than one of copper, nickel, gold, silver and titanium.
The first rewiring layer 1 is electrically connected with the forward chip 11 and the second rewiring layer 2 through the first conductive structure 7 and the third conductive structure 9, the reverse chip 12 is electrically connected with the second rewiring layer 2 through the second conductive structure 8, and connection with the outside is achieved through the metal bump 13 on the surface of the first rewiring layer 1.
The second rewiring layer 2 comprises a first surface and a second surface which are opposite, the control chip 3 is bonded on the first surface, and the second surface is electrically connected with the reverse chip 12 and the second surface, opposite to the first rewiring layer 1, of the first rewiring layer 1 through the second conductive structure 8 and the third conductive structure 9.
The conductive structure is formed by drilling a hole on the plastic packaging layer by using laser, and then forming a first conductive structure 7, a second conductive structure 8 and a third conductive structure 9 in the deep hole by using a sputtering process, an electroplating process or a chemical plating process and the like. The materials of the first conductive structure 7, the second conductive structure 8 and the third conductive structure 9 are one or more of copper, nickel, gold, silver and titanium.
The conductive structure may also be a metal pillar, and before packaging, the metal pillar may be formed on the surface of the chip by using a sputtering process or an electroplating process.
The forward chip 11 and the reverse chip 12 may be memory chips. The material of the first and second sealing layers 5 and 6 is resin. The metal bump is a solder ball.
Claims (4)
1. The utility model provides a chip fan-out type low thickness packaging structure of two-way lamination which characterized in that: the packaging structure comprises a first rewiring layer (1), a second rewiring layer (2), a control chip (3), a functional chip lamination structure (4), a first packaging layer (5) and a second packaging layer (6), wherein the functional chip lamination structure (4) is arranged above the first rewiring layer (1), the first packaging layer (5) is wrapped outside the functional chip lamination structure (4), the second rewiring layer (2) is arranged at the upper end of the first packaging layer (5), the control chip (3) is arranged above the second rewiring layer (2), the second packaging layer (6) is wrapped outside the control chip (3), the first rewiring layer (1) is electrically connected with the functional chip lamination structure (4) through a first conductive structure (7), the second rewiring layer (2) is electrically connected with the functional chip lamination structure (4) through a second conductive structure (8), the first rewiring layer (1) is electrically connected with the second rewiring layer (2) through a third conductive structure (9), and the functional chip lamination structure (4) is formed by stacking a plurality of positive and negative functional chip laminations (10).
2. The chip fan-out type low thickness package structure of a bidirectional lamination as claimed in claim 1, wherein: a plurality of positive and negative functional chipset (10) are echelonment dislocation distribution, positive and negative functional chipset (10) are including forward chip (11), reverse chip (12), first rewiring layer (1) is connected with forward chip (11) electricity through conducting structure (7), and one side of forward chip (11) is equipped with reverse chip (12), and reverse chip (12) are connected with second rewiring layer (2) electricity through conducting structure two (8).
3. The chip fan-out low thickness package structure of bi-directional laminate of claim 1, wherein: the lower end of the first rewiring layer (1) is provided with a metal bump (13).
4. The chip fan-out type low thickness package structure of a bidirectional lamination as claimed in claim 1, wherein: the control chip (3) is electrically connected with the second rewiring layer (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221678401.9U CN218333754U (en) | 2022-07-01 | 2022-07-01 | Chip fan-out type low-thickness packaging structure with bidirectional laminated sheets |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221678401.9U CN218333754U (en) | 2022-07-01 | 2022-07-01 | Chip fan-out type low-thickness packaging structure with bidirectional laminated sheets |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218333754U true CN218333754U (en) | 2023-01-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221678401.9U Active CN218333754U (en) | 2022-07-01 | 2022-07-01 | Chip fan-out type low-thickness packaging structure with bidirectional laminated sheets |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218333754U (en) |
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2022
- 2022-07-01 CN CN202221678401.9U patent/CN218333754U/en active Active
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