CN218069843U

CN218069843U - Three-dimensional integrated fan-out type packaging structure

Info

Publication number: CN218069843U
Application number: CN202222309780.0U
Authority: CN
Inventors: 马书英; 王姣; 常笑男; 赵艳娇
Original assignee: Huatian Technology Kunshan Electronics Co Ltd
Current assignee: Huatian Technology Kunshan Electronics Co Ltd
Priority date: 2022-08-31
Filing date: 2022-08-31
Publication date: 2022-12-16
Anticipated expiration: 2032-08-31

Abstract

The utility model discloses a three-dimensional integrated fan-out type packaging structure, which comprises a first chip, a second chip, a conductive column, a first conductive structure and a second conductive structure, wherein the first chip is positioned below the second chip; the first chip is encapsulated with a first plastic encapsulation layer, and the second chip is encapsulated with a second plastic encapsulation layer; the chip PAD of the first chip and the chip PAD of the second chip face outwards; the conductive column penetrates through the second plastic packaging layer and the first plastic packaging layer from top to bottom; the first conductive structure is positioned below the first chip, and the second conductive structure is positioned above the second chip; the first conductive structure is electrically connected with the lower end of the conductive column and the first chip; the second conductive structure is electrically connected with the upper end of the conductive column and the second chip. The packaging structure can further reduce the packaging volume of the chip while meeting the performance of the chip, realize the interconnection in the Z direction, reduce the signal loss, improve the packaging efficiency and reduce the packaging cost.

Description

Three-dimensional integrated fan-out type packaging structure

Technical Field

The utility model relates to a semiconductor chip encapsulates technical field, in particular to three-dimensional integrated fan-out type packaging structure.

Background

With the increasingly high requirements for small size, high performance, high reliability and ultra-low power consumption of electronic products such as mobile phones and computers, the advanced packaging technology breaks through and develops continuously, and meanwhile, under the assistance of emerging industries such as artificial intelligence, automatic driving, 5G networks, internet of things and the like, the requirement for three-dimensional integrated advanced packaging is increasingly strong.

Advanced packaging is currently moving towards system integration, high speed, high frequency, and three dimensional. The high-density TSV technology and the Fan-Out technology are core technologies of the current advanced packaging due to the advantages of flexibility, high density and suitability for system integration; however, for high density integrated package, the TSV technology generally used in the industry is costly and causes a certain degree of signal loss due to high density integration. Therefore, how to integrate and package a plurality of different high-density chips together to form a system or subsystem with powerful functions and small volume power consumption becomes a great challenge in the advanced packaging field of semiconductor chips.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, an object of the present invention is to provide a three-dimensional integrated fan-out type package structure. The packaging structure can further reduce the packaging volume of the chip while meeting the performance of the chip, realize the interconnection in the Z direction, reduce the signal loss, improve the packaging efficiency and reduce the packaging cost.

For realizing above-mentioned technical purpose, reach above-mentioned technological effect, the utility model discloses a following technical scheme realizes:

a three-dimensional integrated fan-out type packaging structure comprises a first chip, a second chip, a conductive column, a first conductive structure and a second conductive structure, wherein the first chip is positioned below the second chip; the first chip is encapsulated with a first plastic encapsulation layer, and the second chip is encapsulated with a second plastic encapsulation layer; the chip PAD of the first chip and the chip PAD of the second chip face outwards; the conductive column penetrates through the second plastic packaging layer and the first plastic packaging layer from top to bottom; the first conductive structure is positioned below the first chip, and the second conductive structure is positioned above the second chip; the first conductive structure is electrically connected with the lower end of the conductive column and a chip PAD of the first chip; the second conductive structure is electrically connected with the upper end of the conductive column and a chip PAD of the second chip.

Furthermore, the first conductive structure includes at least one first metal redistribution layer electrically connected to the lower end of the conductive pillar and the first chip, and each first metal redistribution layer is covered with a first insulating layer.

Furthermore, the second conductive structure includes at least one second metal redistribution layer electrically connected to the upper end of the conductive pillar and the second chip, and each second metal redistribution layer is covered with a second insulating layer.

Furthermore, the first conductive structure is further connected with an electrical lead-out structure, and the second conductive structure is further connected with an under bump metal layer.

Furthermore, the electrical conduction structure is a solder ball, a metal bump or a conductive adhesive structure.

The manufacturing method of the three-dimensional integrated fan-out packaging structure comprises the following steps:

s1, providing a bearing sheet, and connecting a first chip on the bearing sheet through a bonding layer; and the chip PAD of the first chip is downward;

s2, forming a first plastic packaging layer for packaging the first chip on the bearing sheet;

s3, mounting a second chip on the first plastic packaging layer, wherein a chip PAD of the second chip faces upwards;

s4, forming a second plastic packaging layer for packaging the second chip on the first plastic packaging layer, and thinning the second plastic packaging layer;

s5, removing the bearing sheet and the bonding layer;

s6, forming through holes penetrating through the two plastic packaging layers on the first plastic packaging layer and the second plastic packaging layer, and manufacturing conductive columns in the through holes;

s7, forming a first conductive structure electrically connected with the lower end of the conductive column and a chip PAD of the first chip on the lower surface of the first plastic packaging layer; and forming a second conductive structure electrically connected with the upper end of the conductive column and the chip PAD of the second chip on the second plastic packaging layer.

Further, before the second chip is mounted, a conductive bump is formed on a chip PAD of the second chip in advance; and after the second plastic packaging layer is thinned, the conductive salient points on the chip PAD of the second chip are exposed.

Further, in step S7, the forming process of the first conductive structure is: forming at least one first metal redistribution layer electrically connected with the lower end of the conductive column and the first chip on the lower surface of the first plastic package layer, and covering a first insulating layer on each first metal redistribution layer; and forming at least one second metal redistribution layer electrically connected with the upper end of the conductive post and the second chip on the second plastic packaging layer, and covering a second insulating layer on each second metal redistribution layer.

Further, step S8 is included to respectively open openings at a position on the outer layer first insulating layer corresponding to the first metal redistribution layer and a position on the outer layer second insulating layer corresponding to the second metal redistribution layer, form an electrical lead-out structure electrically connected to the first metal redistribution layer on the opening of the first insulating layer, and form an under bump metal layer electrically connected to the second metal redistribution layer on the opening of the second insulating layer.

Furthermore, the electrical lead-out structure in the method is one of a solder ball, a metal bump and a conductive adhesive structure.

The utility model has the advantages that:

the packaging structure of the utility model can realize the Z-direction interconnection of a plurality of chips, and realize the purposes of small packaging volume and multi-chip integration; the conductive structure in the packaging structure is matched with the conductive column, so that the chip PAD can directly lead out signals when the chip is interconnected, the impedance can be reduced, the signal loss is reduced, the wiring distance is shortened, the packaging cost is reduced, and high-density integration is realized.

The utility model discloses an encapsulation structure is through boring the through-hole on two upper and lower plastic-sealed layers when the preparation, sets up again and leads electrical pillar, can realize two-sided simultaneous processing conductive structure, reduces the encapsulated time, greatly improves encapsulation efficiency, reduces the encapsulation cost.

Drawings

Fig. 1 is a schematic structural diagram of a three-dimensional integrated fan-out package structure according to an embodiment of the present invention.

Fig. 2 to 9 are schematic diagrams illustrating a manufacturing process of a three-dimensional integrated fan-out package structure according to an embodiment of the present invention.

Detailed Description

The following detailed description of the preferred embodiments of the present invention will be provided in conjunction with the accompanying drawings, so as to enable those skilled in the art to more easily understand the advantages and features of the present invention, and thereby define the scope of the invention more clearly and clearly.

As shown in fig. 1, a preferred embodiment of a three-dimensional integrated fan-out package structure includes a first chip 10, a second chip 11, a conductive pillar 12, a first conductive structure and a second conductive structure, wherein the first chip 10 is located below the second chip 11; a first plastic package layer 13 is encapsulated on the first chip 10, and a second plastic package layer 14 is encapsulated on the second chip 11; the chip PAD of the first chip 10 and the chip PAD of the second chip 11 face outward; the conductive posts 12 penetrate through the second plastic package layer 14 and the first plastic package layer 13 from top to bottom; the first conductive structure is located below the first chip 10, and the second conductive structure is located above the second chip 11; the first conductive structure is electrically connected to the lower end of the conductive pillar 12 and the chip PAD of the first chip 10; the second conductive structure is electrically connected to the upper end of the conductive pillar 12 and the chip PAD of the second chip 11.

In this embodiment, the first conductive structure includes two first metal redistribution layers 15 electrically connected to the lower ends of the conductive pillars 12 and the first chip 10, and each first metal redistribution layer 15 is covered with a first insulating layer 16.

The second conductive structure includes two second metal redistribution layers 17 electrically connected to the upper ends of the conductive pillars 12 and the second chip 11, and each second metal redistribution layer 17 is covered with a second insulating layer 18.

Openings are respectively formed in the position, corresponding to the first metal rewiring layer 15, of the first insulating layer 16 on the outermost layer and the position, corresponding to the second metal rewiring layer 17, of the second insulating layer 18 on the outermost layer; an electrical lead-out structure 19 electrically connected to the first metal redistribution layer 15 is formed on the opening of the first insulating layer 16, and an under bump metallization layer 20 electrically connected to the second metal redistribution layer 17 is formed on the opening of the second insulating layer 18. The electrical lead-out structure 19 may be a solder ball, a metal bump or a conductive adhesive structure; in the present embodiment, the electrical lead-out structure 19 is a solder ball.

The manufacturing method of the three-dimensional integrated fan-out type packaging structure comprises the following steps:

s1, providing a carrier sheet 21, and connecting a first chip 10 on the carrier sheet 21 through a bonding layer 22 to obtain a structure shown in FIG. 2; the PAD of the first chip 10 is down; the material of the carrier sheet 21 may be one of silicon, glass, metal or organic material; in this embodiment, the material of the carrier sheet 21 is metal.

And S2, forming a first plastic package layer 13 for encapsulating the first chip 10 on the carrier sheet 21 by adopting a plastic package process to obtain the structure shown in FIG. 3.

S3, manufacturing a conductive bump 111 on a chip PAD of the second chip 11, and then attaching the second chip 11 to the first plastic package layer 13 through an adhesive, wherein the chip PAD of the second chip 11 faces upwards, so as to obtain the structure shown in FIG. 4; the second chip 11 and the first chip 10 may be the same chip or different chips.

And S4, forming a second plastic packaging layer 14 for packaging the second chip 11 on the first plastic packaging layer 13 by adopting a plastic packaging process, thinning the second plastic packaging layer 14, and exposing the conductive bumps on the second chip 11 to obtain the structure shown in FIG. 5.

And S5, removing the carrier sheet 21 and the bonding layer 22 through a bonding removal process to obtain the structure shown in FIG. 6.

S6, forming through holes penetrating through the two plastic packaging layers on the first plastic packaging layer 13 and the second plastic packaging layer 14, and manufacturing conductive columns 12 in the through holes to obtain the structure shown in FIG. 7; the conductive post 12 may be made of one or a combination of two or more of copper, copper alloy, titanium and titanium alloy, or may be made of other suitable conductive materials such as conductive adhesive; in this embodiment, the material of the conductive post is copper.

S7, forming two first metal redistribution layers 15 electrically connected with the lower ends of the conductive columns 12 and the first chip 10 on the first plastic package layer 13, and covering a first insulating layer 16 on each first metal redistribution layer 15; forming two second metal redistribution layers 17 electrically connected to the upper ends of the conductive pillars 12 and the second chip 11 (conductive bumps on the second chip) on the second plastic package layer 14, and covering a second insulating layer 18 on each second metal redistribution layer 17, respectively, to obtain the structure shown in fig. 8;

the material of the first metal redistribution layer 15 and the second metal redistribution layer 17 may be one or a combination of two or more of metal materials such as aluminum, copper, nickel, gold, and the like; the materials of the first insulating layer 16 and the second insulating layer 18 are inorganic or organic materials; in the present embodiment, the material of the first metal redistribution layer 15 and the second metal redistribution layer 17 is copper; the material of the first insulating layer 16 and the second insulating layer 18 is epoxy resin.

S8, respectively forming openings at a position corresponding to the first metal redistribution layer 15 on the outermost first insulating layer 16 and a position corresponding to the second metal redistribution layer 17 on the outermost second insulating layer 18, forming an electrical lead-out structure 19 electrically connected to the first metal redistribution layer 15 on the opening of the first insulating layer 16, forming an under bump metallization layer 20 electrically connected to the second metal redistribution layer 17 on the opening of the second insulating layer 18, obtaining a structure shown in fig. 9, and finally cutting the structure to obtain a package structure shown in fig. 1;

the electrical property leading-out structure can be one of a solder ball, a metal salient point and a conductive adhesive structure; in the present embodiment, the electrically conducting structure is a solder ball; the solder ball is electrically connected to the first metal wiring layer through the pad.

The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all the equivalent structures or equivalent processes that are used in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A three-dimensional integrated fan-out type packaging structure is characterized by comprising a first chip, a second chip, a conductive column, a first conductive structure and a second conductive structure, wherein the first chip is positioned below the second chip; the first chip is encapsulated with a first plastic encapsulation layer, and the second chip is encapsulated with a second plastic encapsulation layer; the chip PAD of the first chip and the chip PAD of the second chip face outwards; the conductive column penetrates through the second plastic packaging layer and the first plastic packaging layer from top to bottom; the first conductive structure is positioned below the first chip, and the second conductive structure is positioned above the second chip; the first conductive structure is electrically connected with the lower end of the conductive column and a chip PAD of the first chip; the second conductive structure is electrically connected with the upper end of the conductive column and a chip PAD of the second chip.

2. The package structure of claim 1, wherein the first conductive structure comprises at least one first redistribution layer electrically connected to the lower end of the conductive pillar and the first chip, and each first redistribution layer is covered with a first insulating layer.

3. The package structure of claim 2, wherein the second conductive structure comprises at least one second redistribution layer electrically connected to the upper ends of the conductive pillars and the second chip, and each second redistribution layer is covered with a second insulating layer.

4. The package structure of claim 1, wherein the first conductive structure is further connected to an electrical lead-out structure, and the second conductive structure is further connected to an Under Bump Metallurgy (UBM).

5. The package structure of claim 4, wherein the electrically conductive structure is a solder ball, a metal bump or a conductive paste.