CN115295529A - Three-dimensional integrated fan-out type packaging structure and manufacturing method thereof - Google Patents

Three-dimensional integrated fan-out type packaging structure and manufacturing method thereof Download PDF

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Publication number
CN115295529A
CN115295529A CN202211054666.6A CN202211054666A CN115295529A CN 115295529 A CN115295529 A CN 115295529A CN 202211054666 A CN202211054666 A CN 202211054666A CN 115295529 A CN115295529 A CN 115295529A
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China
Prior art keywords
chip
layer
conductive
electrically connected
plastic packaging
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Pending
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CN202211054666.6A
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Chinese (zh)
Inventor
马书英
王姣
常笑男
赵艳娇
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Huatian Technology Kunshan Electronics Co Ltd
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Huatian Technology Kunshan Electronics Co Ltd
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Priority to CN202211054666.6A priority Critical patent/CN115295529A/en
Publication of CN115295529A publication Critical patent/CN115295529A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses a three-dimensional integrated fan-out type packaging structure and a manufacturing method thereof, wherein the packaging structure comprises a first chip, a second chip, a conductive post, a first conductive structure and a second conductive structure, wherein the first chip is positioned below the second chip; the first chip is encapsulated with a first plastic encapsulation layer, and the second chip is encapsulated with a second plastic encapsulation layer; the chip PAD of the first chip and the chip PAD of the second chip face outwards; the conductive column penetrates through the second plastic packaging layer and the first plastic packaging layer from top to bottom; the first conductive structure is positioned below the first chip, and the second conductive structure is positioned above the second chip; the first conductive structure is electrically connected with the lower end of the conductive column and the first chip; the second conductive structure is electrically connected with the upper end of the conductive column and the second chip. The packaging structure and the manufacturing method can further reduce the packaging volume of the chip while meeting the performance of the chip, realize the interconnection in the Z direction, reduce the signal loss, improve the packaging efficiency and reduce the packaging cost.

Description

Three-dimensional integrated fan-out type packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor chip packaging, in particular to a three-dimensional integrated fan-out type packaging structure and a manufacturing method thereof.
Background
With the increasingly high requirements for small size, high performance, high reliability and ultra-low power consumption of electronic products such as mobile phones and computers, the advanced packaging technology is continuously breaking through and developing, and meanwhile, the requirement for three-dimensional integrated advanced packaging is increasingly strong under the support of new industries such as artificial intelligence, automatic driving, 5G networks, internet of things and the like.
Currently, advanced packaging is moving towards system integration, high speed, high frequency, three dimensional. The high-density TSV technology and the Fan-Out technology become core technologies of the current advanced packaging due to the advantages of flexibility, high density and suitability for system integration; however, for high-density integrated package, the TSV technology generally used in the industry is costly and causes a certain signal loss due to high-density integration. Therefore, how to integrate and package a plurality of different kinds of high-density chips together to form a system or subsystem with powerful functions and small volume power consumption becomes a great challenge in the field of advanced packaging of semiconductor chips.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a three-dimensional integrated fan-out package structure and a method for manufacturing the same. The packaging structure and the manufacturing method can further reduce the packaging volume of the chip while meeting the performance of the chip, realize the interconnection in the Z direction, reduce the signal loss, improve the packaging efficiency and reduce the packaging cost.
In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:
a three-dimensional integrated fan-out type packaging structure comprises a first chip, a second chip, a conductive column, a first conductive structure and a second conductive structure, wherein the first chip is positioned below the second chip; the first chip is encapsulated with a first plastic encapsulation layer, and the second chip is encapsulated with a second plastic encapsulation layer; the chip PAD of the first chip and the chip PAD of the second chip face outwards; the conductive column penetrates through the second plastic packaging layer and the first plastic packaging layer from top to bottom; the first conductive structure is positioned below the first chip, and the second conductive structure is positioned above the second chip; the first conductive structure is electrically connected with the lower end of the conductive column and a chip PAD of the first chip; the second conductive structure is electrically connected with the upper end of the conductive column and a chip PAD of the second chip.
Furthermore, the first conductive structure includes at least one first metal redistribution layer electrically connected to the lower end of the conductive pillar and the first chip, and each first metal redistribution layer is covered with a first insulating layer.
Furthermore, the second conductive structure includes at least one second metal redistribution layer electrically connected to the upper end of the conductive pillar and the second chip, and each second metal redistribution layer is covered with a second insulating layer.
Furthermore, the first conductive structure is further connected with an electrical conduction structure, and the second conductive structure is further connected with an under bump metal layer.
Further, the electrical conduction structure is a solder ball, a metal bump or a conductive adhesive structure.
The invention further provides a manufacturing method of the three-dimensional integrated fan-out type packaging structure, which comprises the following steps:
s1, providing a bearing sheet, and connecting a first chip on the bearing sheet through a bonding layer; and the chip PAD of the first chip is downward;
s2, forming a first plastic packaging layer for packaging the first chip on the bearing sheet;
s3, mounting a second chip on the first plastic packaging layer, wherein a chip PAD of the second chip faces upwards;
s4, forming a second plastic packaging layer for packaging the second chip on the first plastic packaging layer, and thinning the second plastic packaging layer;
s5, removing the bearing sheet and the bonding layer;
s6, forming through holes penetrating through the two plastic packaging layers on the first plastic packaging layer and the second plastic packaging layer, and manufacturing conductive columns in the through holes;
s7, forming a first conductive structure electrically connected with the lower end of the conductive column and a chip PAD of the first chip on the lower surface of the first plastic packaging layer; and forming a second conductive structure electrically connected with the upper end of the conductive column and the chip PAD of the second chip on the second plastic packaging layer.
Further, before the second chip is mounted, a conductive bump is formed on a chip PAD of the second chip in advance; and after the second plastic packaging layer is thinned, the conductive salient points on the chip PAD of the second chip are exposed.
Further, in step S7, the forming process of the first conductive structure is as follows: forming at least one first metal redistribution layer electrically connected with the lower end of the conductive column and the first chip on the lower surface of the first plastic package layer, and covering a first insulating layer on each first metal redistribution layer; and forming at least one second metal redistribution layer electrically connected with the upper end of the conductive post and the second chip on the second plastic packaging layer, and covering a second insulating layer on each second metal redistribution layer.
Further, step S8 is included to respectively open openings at a position on the outer layer first insulating layer corresponding to the first metal redistribution layer and a position on the outer layer second insulating layer corresponding to the second metal redistribution layer, form an electrical lead-out structure electrically connected to the first metal redistribution layer on the opening of the first insulating layer, and form an under bump metal layer electrically connected to the second metal redistribution layer on the opening of the second insulating layer.
Furthermore, the electrical conduction structure in the method is one of a solder ball, a metal bump and a conductive adhesive structure.
The invention has the beneficial effects that:
the packaging structure can realize the Z-direction interconnection of a plurality of chips, and realizes the purposes of small packaging volume and multi-chip integration; the conductive structure in the packaging structure is matched with the conductive column, so that the chip PAD can directly lead out signals when the chip is interconnected, the impedance can be reduced, the signal loss is reduced, the wiring distance is shortened, the packaging cost is reduced, and high-density integration is realized.
According to the method, through holes are drilled in the upper plastic packaging layer and the lower plastic packaging layer, and then the conductive columns are arranged, so that the conductive structures can be processed on two sides simultaneously, the packaging time is shortened, the packaging efficiency is greatly improved, and the packaging cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a three-dimensional integrated fan-out package structure according to an embodiment of the present invention.
Fig. 2 to 9 are schematic diagrams illustrating a manufacturing process of a three-dimensional integrated fan-out package structure according to an embodiment of the invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
As shown in fig. 1, a preferred embodiment of a three-dimensional integrated fan-out package structure includes a first chip 10, a second chip 11, a conductive pillar 12, a first conductive structure and a second conductive structure, wherein the first chip 10 is located below the second chip 11; a first plastic package layer 13 is encapsulated on the first chip 10, and a second plastic package layer 14 is encapsulated on the second chip 11; the chip PAD of the first chip 10 and the chip PAD of the second chip 11 are both facing outwards; the conductive posts 12 penetrate through the second plastic package layer 14 and the first plastic package layer 13 from top to bottom; the first conductive structure is located below the first chip 10, and the second conductive structure is located above the second chip 11; the first conductive structure is electrically connected with the lower end of the conductive column 12 and the chip PAD of the first chip 10; the second conductive structure is electrically connected to the upper end of the conductive pillar 12 and the chip PAD of the second chip 11.
In this embodiment, the first conductive structure includes two first metal redistribution layers 15 electrically connected to the lower ends of the conductive pillars 12 and the first chip 10, and each first metal redistribution layer 15 is covered with a first insulating layer 16.
The second conductive structure includes two second metal redistribution layers 17 electrically connected to the upper ends of the conductive pillars 12 and the second chip 11, and each second metal redistribution layer 17 is covered with a second insulating layer 18.
Openings are respectively formed in the position, corresponding to the first metal rewiring layer 15, of the first insulating layer 16 on the outermost layer and the position, corresponding to the second metal rewiring layer 17, of the second insulating layer 18 on the outermost layer; an electrical lead-out structure 19 electrically connected to the first metal redistribution layer 15 is formed on the opening of the first insulating layer 16, and an under bump metal layer 20 electrically connected to the second metal redistribution layer 17 is formed on the opening of the second insulating layer 18. The electrical lead-out structure 19 may be a solder ball, a metal bump or a conductive adhesive structure; in the present embodiment, the electrically leading-out structure 19 is a solder ball.
The manufacturing method of the three-dimensional integrated fan-out type packaging structure comprises the following steps:
s1, providing a carrier sheet 21, and connecting a first chip 10 on the carrier sheet 21 through a bonding layer 22 to obtain a structure shown in FIG. 2; the PAD of the first chip 10 is down; the material of the carrier sheet 21 may be one of silicon, glass, metal or organic material; in this embodiment, the material of the carrier sheet 21 is metal.
And S2, forming a first plastic package layer 13 for encapsulating the first chip 10 on the carrier sheet 21 by adopting a plastic package process to obtain the structure shown in FIG. 3.
S3, manufacturing a conductive bump 111 on a chip PAD of the second chip 11, and then attaching the second chip 11 to the first plastic package layer 13 through an adhesive, wherein the chip PAD of the second chip 11 faces upwards, so as to obtain the structure shown in FIG. 4; the second chip 11 and the first chip 10 may be the same chip or different chips.
And S4, forming a second plastic package layer 14 for encapsulating the second chip 11 on the first plastic package layer 13 by adopting a plastic package process, and thinning the second plastic package layer 14 to expose the conductive bumps on the second chip 11, so as to obtain the structure shown in FIG. 5.
And S5, removing the bearing sheet 21 and the bonding layer 22 through a bonding-releasing process to obtain the structure shown in FIG. 6.
S6, forming through holes penetrating through the two plastic packaging layers on the first plastic packaging layer 13 and the second plastic packaging layer 14, and manufacturing conductive columns 12 in the through holes to obtain the structure shown in FIG. 7; the conductive post 12 may be made of one or a combination of two or more of copper, copper alloy, titanium and titanium alloy, or may be made of other suitable conductive materials such as conductive adhesive; in this embodiment, the material of the conductive post is copper.
S7, forming two first metal redistribution layers 15 electrically connected to the lower ends of the conductive pillars 12 and the first chip 10 on the first plastic package layer 13, and covering a first insulating layer 16 on each first metal redistribution layer 15; forming two second metal redistribution layers 17 electrically connected to the upper ends of the conductive pillars 12 and the second chip 11 (conductive bumps on the second chip) on the second plastic package layer 14, and covering a second insulating layer 18 on each second metal redistribution layer 17, respectively, to obtain the structure shown in fig. 8;
the material of the first metal redistribution layer 15 and the second metal redistribution layer 17 may be one or a combination of two or more of metal materials such as aluminum, copper, nickel, gold, and the like; the materials of the first insulating layer 16 and the second insulating layer 18 are inorganic or organic materials; in the present embodiment, the material of the first metal redistribution layer 15 and the second metal redistribution layer 17 is copper; the material of the first insulating layer 16 and the second insulating layer 18 is epoxy resin.
S8, respectively forming openings at a position corresponding to the first metal redistribution layer 15 on the outermost first insulating layer 16 and a position corresponding to the second metal redistribution layer 17 on the outermost second insulating layer 18, forming an electrical lead-out structure 19 electrically connected to the first metal redistribution layer 15 on the opening of the first insulating layer 16, forming an under bump metallization layer 20 electrically connected to the second metal redistribution layer 17 on the opening of the second insulating layer 18, obtaining a structure shown in fig. 9, and finally cutting the structure to obtain a package structure shown in fig. 1;
the electrical conduction structure can be one of a solder ball, a metal bump and a conductive adhesive structure; in the present embodiment, the electrical lead-out structure is a solder ball; the solder ball is electrically connected to the first metal wiring layer through the pad.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A three-dimensional integrated fan-out type packaging structure is characterized by comprising a first chip, a second chip, a conductive column, a first conductive structure and a second conductive structure, wherein the first chip is positioned below the second chip; the first chip is encapsulated with a first plastic encapsulation layer, and the second chip is encapsulated with a second plastic encapsulation layer; the chip PAD of the first chip and the chip PAD of the second chip face outwards; the conductive column penetrates through the second plastic packaging layer and the first plastic packaging layer from top to bottom; the first conductive structure is positioned below the first chip, and the second conductive structure is positioned above the second chip; the first conductive structure is electrically connected with the lower end of the conductive column and a chip PAD of the first chip; the second conductive structure is electrically connected with the upper end of the conductive column and a chip PAD of the second chip.
2. The package structure of claim 1, wherein the first conductive structure comprises at least one first redistribution layer electrically connected to the lower end of the conductive pillar and the first chip, and each first redistribution layer is covered with a first insulating layer.
3. The package structure of claim 2, wherein the second conductive structure comprises at least one second redistribution layer electrically connected to the upper end of the conductive pillar and the second chip, and each second redistribution layer is covered with a second insulating layer.
4. The package structure of claim 1, wherein the first conductive structure is further connected to an electrical lead-out structure, and the second conductive structure is further connected to an Under Bump Metallurgy (UBM).
5. The package structure of claim 4, wherein the electrically conductive structure is a solder ball, a metal bump or a conductive paste.
6. A manufacturing method of a three-dimensional integrated fan-out packaging structure is characterized by comprising the following steps:
s1, providing a bearing sheet, and connecting a first chip on the bearing sheet through a bonding layer; and the chip PAD of the first chip is downward;
s2, forming a first plastic packaging layer for packaging the first chip on the bearing sheet;
s3, mounting a second chip on the first plastic packaging layer, wherein a chip PAD of the second chip faces upwards;
s4, forming a second plastic packaging layer for packaging the second chip on the first plastic packaging layer, and thinning the second plastic packaging layer;
s5, removing the bearing sheet and the bonding layer;
s6, forming through holes penetrating through the two plastic packaging layers on the first plastic packaging layer and the second plastic packaging layer, and manufacturing conductive columns in the through holes;
s7, forming a first conductive structure electrically connected with the lower end of the conductive column and a chip PAD of the first chip on the first plastic packaging layer; and forming a second conductive structure electrically connected with the upper end of the conductive column and the chip PAD of the second chip on the second plastic packaging layer.
7. The method as claimed in claim 6, wherein before the second chip is mounted, a conductive bump is formed on a PAD of the second chip in advance; and after the second plastic packaging layer is thinned, the conductive salient points on the chip PAD of the second chip are exposed.
8. The method as claimed in claim 6, wherein the step S7 is performed by a first conductive structure forming process including: forming at least one first metal redistribution layer electrically connected with the lower end of the conductive column and the first chip on the first plastic package layer, and covering a first insulating layer on each first metal redistribution layer; and forming at least one second metal redistribution layer electrically connected with the upper end of the conductive column and the second chip on the second plastic packaging layer, and covering a second insulating layer on each second metal redistribution layer respectively.
9. The method as claimed in claim 8, further comprising a step S8 of forming openings on the first insulating layer and the second insulating layer, respectively, forming an electrical lead-out structure electrically connected to the first metal redistribution layer on the opening of the first insulating layer, and forming an under bump metallurgy layer electrically connected to the second metal redistribution layer on the opening of the second insulating layer.
10. The method as claimed in claim 9, wherein the electrically conducting structure is one of a solder ball, a metal bump and a conductive paste.
CN202211054666.6A 2022-08-31 2022-08-31 Three-dimensional integrated fan-out type packaging structure and manufacturing method thereof Pending CN115295529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211054666.6A CN115295529A (en) 2022-08-31 2022-08-31 Three-dimensional integrated fan-out type packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211054666.6A CN115295529A (en) 2022-08-31 2022-08-31 Three-dimensional integrated fan-out type packaging structure and manufacturing method thereof

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CN115295529A true CN115295529A (en) 2022-11-04

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