CN100539122C - Package of system package - Google Patents
Package of system package Download PDFInfo
- Publication number
- CN100539122C CN100539122C CN 200610108555 CN200610108555A CN100539122C CN 100539122 C CN100539122 C CN 100539122C CN 200610108555 CN200610108555 CN 200610108555 CN 200610108555 A CN200610108555 A CN 200610108555A CN 100539122 C CN100539122 C CN 100539122C
- Authority
- CN
- China
- Prior art keywords
- packaging body
- support plate
- chip
- resisting layer
- welding resisting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000004806 packaging method and process Methods 0.000 claims abstract description 61
- 238000003466 welding Methods 0.000 claims abstract description 30
- 239000000084 colloidal system Substances 0.000 claims abstract description 24
- 238000012856 packing Methods 0.000 claims description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 18
- 230000004308 accommodation Effects 0.000 claims description 12
- 241000218202 Coptis Species 0.000 claims description 7
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 4
- 238000000465 moulding Methods 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 238000000034 method Methods 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000007789 sealing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Packaging Frangible Articles (AREA)
Abstract
A system-in-package (SIP) package comprises a carrier plate with a molding area and a peripheral area defined, at least one chip arranged in the molding area, a packaging colloid arranged in the molding area and covering the chip, a plurality of welding pads respectively arranged on the surface of the carrier plate in the peripheral area, and a solder mask layer covering the peripheral area and exposing partial surfaces of the welding pads, wherein at least one accommodating space is formed in the solder mask layer.
Description
[technical field]
The invention provides a kind of packaging body of system in package, refer to a kind of system in package body that forms welding resisting layer in the encapsulating carrier plate neighboring area especially with accommodation space.
[background technology]
Along with electronic product function and the rapid increase of application, encapsulation technology also continues to develop to directions such as three dimension scales to multicore sheet, two-dimentional yardstick towards high density, microminiature, single-chip, so occurred at present with seen in the past conventional package kenel in design, makings gone up and the last distinct advanced encapsulating structure of material application, as wafer-level packaging (wafer level package), three-dimension packaging, multicore sheet encapsulation MCP (multi-chip package) and system in package (system in package, the encapsulation pattern of super-high density such as SIP).Wherein, optimal situation is in a silicon, all integrated circuits can be held into, and promptly (system on chip is best SoC) to the systematization chip.Yet, with complicated gradually circuit function concentrate on process technique, have any problem in the chip, die size also can significantly increase, and causes the complicated of chip processing procedure, and then yield is descended and cost rises.So compare with the SoC technology, emphasize that volume is little, high frequency, at a high speed, short production cycle and the SIP of systematization encapsulation technology cheaply (system in package) be just for reaching aforementioned target, and can integrate the preferable method for packing with different circuit function chips.
Please refer to Fig. 1.Fig. 1 is the schematic diagram of the packaging body 10 of existing system encapsulation.As shown in Figure 1, the packaging body 10 of existing system encapsulation includes a support plate 16, and definition has envelope (molding area) 30 and surrounding zones, film district (periphery area) 32 on the surface of support plate 16.Wherein, include the adhesion layer 14 that at least one 12, one of chip that are arranged at support plate 16 surfaces is arranged at support plate 16 and chip chamber in the envelope film district 30, and be covered in the packing colloid 24 on chip 12 and the part support plate 16.Simultaneously, packaging body 10 includes some the bonding wires 18 that utilize the routing mode to form in addition and electrically connects chip 12 and support plate 16, and be arranged at support plate 16 another lip-deep several tin balls 22, so that tin ball 22 is electrically connected with chip 12 by the circuit (not shown) of support plate 16 inside.In addition, include a welding resisting layer (solder mask) 34 (being commonly called as green lacquer) in the surrounding zone 32, and several are arranged at the weld pad 36 on support plate 16 surfaces, wherein the level height on weld pad 36 surfaces flushes with the level height on welding resisting layer 34 surfaces.
Yet the packaging body 10 of existing system encapsulation is when sealing the film processing procedure, and the packing colloid 24 that covers chip 12 and support plate 16 surfaces overflows envelope film district 30 through regular meeting and flows out to 32 surfaces, surrounding zone.Because the level height on welding resisting layer 36 surfaces flushes with the level height on weld pad 36 surfaces, therefore when sealing the film processing procedure, unnecessary packing colloid 24 will inevasible covering be arranged at several weld pads 36 and welding resisting layers 34 on 32 surfaces, surrounding zone, and then influence subsequent element or the tin ball bonding connects in (ball mounting) processing procedure, adhere to passive component (not shown), driving component (not shown), the yield of tin ball (not shown) on weld pad 36 and stability.
[summary of the invention]
The object of the present invention is to provide a kind of packaging body that forms welding resisting layer in the encapsulating carrier plate neighboring area, cause problems such as weld pad pollution because of packing colloid is excessive to improve existing packaging body with accommodation space.
For reaching aforementioned purpose, the present invention discloses a kind of system in package (system-in-package, SIP) packaging body, this packaging body includes a definition the support plate of envelope mould district and surrounding zone, be arranged at least one chip in this envelope mould district, be arranged in this envelope mould district and cover the packing colloid of this chip, the weld pad on several support plate surfaces that are arranged at this surrounding zone respectively, and be covered in this surrounding zone and expose the respectively welding resisting layer of the part surface of this weld pad, and be formed with at least one accommodation space in this welding resisting layer.
Because the present invention is provided with a welding resisting layer with at least one accommodation space in the surrounding zone of support plate, therefore when encapsulating structure seals the film processing procedure, the packing colloid that overflows envelope film district can effectively be contained in the accommodation space of this welding resisting layer, improving existing encapsulating structure pollutes weld pad because of packing colloid is excessive problem, and then promote the tin ball bonding and connect the yield of (ball mounting) processing procedure on weld pad with stable.
[description of drawings]
Fig. 1 is the schematic diagram of the packaging body of existing system encapsulation.
Fig. 2 and Fig. 3 are the following packaging body schematic diagram of preferred embodiment of the present invention.
Fig. 4 and Fig. 5 are the packaging body schematic diagram of another embodiment of the present invention system in package.
[embodiment]
Please refer to Fig. 2 and Fig. 3.Fig. 2 and Fig. 3 are following packaging body 60 schematic diagrames of preferred embodiment system in package of the present invention.As Fig. 2 and shown in Figure 3, packaging body 60 down of the present invention includes a support plate 62, and definition is gone up on support plate 62 surfaces 64 and one surrounding zone (peripheryarea) 66, an envelope film district (molding area), and with the thickness distribution of support plate 62, the thickness in envelope film district 64 is greater than the thickness of surrounding zone 66.Wherein, include at least one chip 68 in the envelope film district 64, for example one be arranged at adhesion layer 70 and that support plate 62 surperficial crystal covered chips, are arranged at support plate 62 and 68 of chips and be covered in packing colloid 72 on chip 68 and the part support plate 62.Simultaneously, following packaging body 60 includes some the gold threads 74 that utilize the routing mode to form in addition, be used for being electrically connected chip 68 and support plate 62, and several are arranged at the tin ball 76 of the lower surface of support plate 62 so that tin ball 76 by support plate 62 inside the circuit (not shown) and be electrically connected with chip 68.
In addition, packaging body as the existing system encapsulation, also include a welding resisting layer 80 in the surrounding zone 66 of the present invention and several are arranged at the weld pad 82 on support plate 62 surfaces, be used for cooperating the tin ball bonding to connect processing procedures such as (ballmounting), with passive component (not shown), driving component (not shown), chip (not shown) or the packaging body (not shown) that is electrically connected other.Wherein, the level height on weld pad 82 surfaces is except the level height more than or equal to envelope 64 surfaces, film district, and also the while is greater than the level height on welding resisting layer 80 surfaces.In addition, 62 of packing colloid 72 and support plates have a contact-making surface 78, and contact-making surface 78 is lower than the open surfaces of welding resisting layer 80 in weld pad 82, as shown in Figure 2, or flush with the open surfaces of weld pad 82, as shown in Figure 3.
It should be noted that welding resisting layer 80 of the present invention except being arranged at support plate 62 surface and surrounding several weld pads 82, and include an accommodation space 84 simultaneously, be formed between the weld pad 82.When therefore packaging body 60 seals the film processing procedure instantly, be covered in chip 68 and the packing colloid 72 of part support plate 62 as the envelope film district 64 of overflowing support plate 62, can take advantage of a situation in the accommodation space 84 that is contained in welding resisting layer 80, and then the packing colloid of avoiding overflowing 72 covers each weld pad 82 surfaces that are arranged at surrounding zone 66.Wherein, weld pad 82 can utilize the mode of metal layer stack, for example form a first metal layer 86 on support plate 62 surfaces earlier, on the first metal layer 86, pile up one second metal level 88 then, and cooperate the welding resisting layer 80 of multilayer or the mode of etching welding resisting layer 80 to form accommodation space 84.
Please refer to Fig. 4 and Fig. 5.Fig. 4 and Fig. 5 are packaging body 92 schematic diagrames of another embodiment of the present invention system in package.As Fig. 4 and shown in Figure 5, down packaging body 60 of the present invention can cooperate packaging body 90 on again and form the packaging body 92 of a system in package.As before described, following packaging body 60 includes a support plate 62, and support plate 62 surperficial upward definition have an envelope film district (molding area) and a surrounding zone (peripheryarea).Wherein, envelope includes at least one chip 68 in the film district, and the adhesion layer 70 and that the crystal covered chip, that for example is arranged at support plate 62 surfaces is arranged at support plate 62 and 68 of chips is covered in the packing colloid 72 on chip 68 and the part support plate 62.Simultaneously, following packaging body 60 includes some the gold threads 74 that utilize the routing mode to form in addition, be used for being electrically connected chip 68 and support plate 62, and several are arranged at the tin ball 76 of support plate 62 lower surfaces, so that tin ball 76 is electrically connected with chip 68 by the circuit (not shown) of support plate 62 inside.
In addition, last packaging body 90 includes a support plate 94, at least one chip 96,98 is located at support plate 94 surfaces.Wherein, chip 96 is to utilize some gold threads 102 to utilize the routing mode to connect support plate 94, and chip 98 then is to utilize several tin balls 100 to be connected in support plate 94 surfaces in the chip package mode.Simultaneously, last packaging body 90 includes a packing colloid 104 in addition and is covered on chip 96,98, gold thread 102 and the support plate 94.As shown in Figure 4, following packaging body 60 utilizes several tin balls 106 to be connected with last packaging body 90.Yet, be not limited thereto adhesive means, the present invention also can be provided with another support plate 108 between packaging body 60 and the last packaging body 90 down, and is connected packaging body 60 and last packaging body 90 down with support plate 108 by several tin balls 110, to form the packaging body 92 of system in package, as shown in Figure 5.
Therefore, compare with the packaging body of existing system encapsulation, the present invention is by establishing in the surrounding zone of support plate Put a welding resisting layer with at least one accommodation space, so when packaging body carries out the sealer processing procedure, overflow The packing colloid that goes out the sealer district just can effectively be contained in the accommodation space of this welding resisting layer, to improve existing envelope The dress body pollutes the problem of weld pad because packing colloid is excessive, and then the ball bonding of lifting tin meets (ball mounting) The yield of processing procedure on weld pad and stability.
Claims (10)
1. the packaging body of a system in package, this packaging body includes: a support plate, the surface definition has an envelope mould district and a surrounding zone on this support plate; At least one chip is arranged in this envelope mould district; One packing colloid is arranged in this envelope mould district and covers this chip; Several weld pads are arranged at the support plate surface of this surrounding zone respectively; And a welding resisting layer, be covered in this surrounding zone; Lower surface at support plate is provided with several tin balls; It is characterized in that: the level height on aforementioned weld pad surface is more than or equal to the level height on this surface, envelope mould district; Packing colloid and this support plate tool one contact-making surface, this contact-making surface is lower than the open surfaces of this welding resisting layer at aforementioned weld pad; Aforementioned welding resisting layer exposes the respectively part surface of this weld pad to the open air, and is formed with at least one accommodation space in this welding resisting layer.
2. as claim 1 a described packaging body, it is characterized in that: aforementioned chip is a crystal covered chip.
3. as claim 1 a described packaging body, it is characterized in that: this packaging body includes some gold threads in addition, is used for being electrically connected this chip and this support plate and is covered by aforementioned packing colloid.
4. as claim 1 a described packaging body, it is characterized in that: the level height on aforementioned weld pad surface is greater than the level height on welding resisting layer surface.
5. the packaging body of a system in package is characterized in that: this packaging body includes packaging body on the packaging body and; Wherein descend packaging body to include first support plate that the upper surface definition has an envelope mould district and a surrounding zone; Be arranged at least one first chip in this envelope mould district; Be arranged in this envelope mould district and cover first packing colloid of this first chip; Be arranged at several weld pads on the first support plate surface of this surrounding zone respectively, the level height on aforementioned weld pad surface is more than or equal to the level height on this surface, envelope mould district; And be covered in this surrounding zone and expose the respectively welding resisting layer of the part surface of this weld pad to the open air, this first packing colloid and this first support plate tool, one contact-making surface, this contact-making surface is lower than the open surfaces of this welding resisting layer at those weld pads, and is formed with at least one accommodation space in this welding resisting layer; Lower surface at this first support plate is provided with several tin balls; It includes one second support plate wherein to go up packaging body; Be located at least one second chip on this second support plate surface; Cover second packing colloid of this second chip and several tin ball bond in the lower surface of this first upper surface of said carrier plate and this second support plate.
6. packaging body as claimed in claim 5 is characterized in that: this first chip and this second chip are a crystal covered chip.
7. packaging body as claimed in claim 5 is characterized in that: this time packaging body includes some gold threads in addition, is used for being electrically connected this first chip and this first support plate and is covered by aforementioned first packing colloid.
8. packaging body as claimed in claim 5 is characterized in that: packaging body includes some gold threads in addition on this, is used for being electrically connected this second chip and this second support plate and is covered by aforementioned second packing colloid.
9. packaging body as claimed in claim 5 is characterized in that: the level height on aforementioned weld pad surface is greater than the level height on this welding resisting layer surface.
10. packaging body as claimed in claim 5 is characterized in that: this packaging body includes one the 3rd support plate in addition, and this time packaging body is to utilize the 3rd support plate and these tin balls to go up packaging body with this to be connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610108555 CN100539122C (en) | 2006-07-21 | 2006-07-21 | Package of system package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610108555 CN100539122C (en) | 2006-07-21 | 2006-07-21 | Package of system package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101110409A CN101110409A (en) | 2008-01-23 |
| CN100539122C true CN100539122C (en) | 2009-09-09 |
Family
ID=39042390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610108555 Active CN100539122C (en) | 2006-07-21 | 2006-07-21 | Package of system package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100539122C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI442530B (en) * | 2009-10-14 | 2014-06-21 | Advanced Semiconductor Eng | Package carrier, package structure and process of fabricating package carrier |
| CN102569274A (en) * | 2012-03-21 | 2012-07-11 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN117253860A (en) * | 2022-06-10 | 2023-12-19 | 礼鼎半导体科技秦皇岛有限公司 | Package substrate, package structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002124528A (en) * | 2000-10-13 | 2002-04-26 | Dekusutaa Kk | Method of sealing multi chips |
| CN1348204A (en) * | 2001-10-19 | 2002-05-08 | 全懋精密科技股份有限公司 | A substrate structure for integrated circuit packaging and its manufacturing method |
| US6388333B1 (en) * | 1999-11-30 | 2002-05-14 | Fujitsu Limited | Semiconductor device having protruding electrodes higher than a sealed portion |
| US6400007B1 (en) * | 2001-04-16 | 2002-06-04 | Kingpak Technology Inc. | Stacked structure of semiconductor means and method for manufacturing the same |
| CN2566454Y (en) * | 2002-08-21 | 2003-08-13 | 南茂科技股份有限公司 | Circuit board to prevent mold overflow |
-
2006
- 2006-07-21 CN CN 200610108555 patent/CN100539122C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388333B1 (en) * | 1999-11-30 | 2002-05-14 | Fujitsu Limited | Semiconductor device having protruding electrodes higher than a sealed portion |
| JP2002124528A (en) * | 2000-10-13 | 2002-04-26 | Dekusutaa Kk | Method of sealing multi chips |
| US6400007B1 (en) * | 2001-04-16 | 2002-06-04 | Kingpak Technology Inc. | Stacked structure of semiconductor means and method for manufacturing the same |
| CN1348204A (en) * | 2001-10-19 | 2002-05-08 | 全懋精密科技股份有限公司 | A substrate structure for integrated circuit packaging and its manufacturing method |
| CN2566454Y (en) * | 2002-08-21 | 2003-08-13 | 南茂科技股份有限公司 | Circuit board to prevent mold overflow |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101110409A (en) | 2008-01-23 |
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