CN112563233B - Planar packaging part and production method thereof - Google Patents

Planar packaging part and production method thereof Download PDF

Info

Publication number
CN112563233B
CN112563233B CN202011426250.3A CN202011426250A CN112563233B CN 112563233 B CN112563233 B CN 112563233B CN 202011426250 A CN202011426250 A CN 202011426250A CN 112563233 B CN112563233 B CN 112563233B
Authority
CN
China
Prior art keywords
chip
island
base island
package
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011426250.3A
Other languages
Chinese (zh)
Other versions
CN112563233A (en
Inventor
徐尚军
周金成
闫景涛
郭鹏
李习周
何文海
陈国岚
王立国
李新平
李东
何海清
王钰中
杨保书
冯苗
陈涛
孙伟洪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TIANSHUI 749 ELECTRONIC CO LTD
Original Assignee
TIANSHUI 749 ELECTRONIC CO LTD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TIANSHUI 749 ELECTRONIC CO LTD filed Critical TIANSHUI 749 ELECTRONIC CO LTD
Priority to CN202011426250.3A priority Critical patent/CN112563233B/en
Publication of CN112563233A publication Critical patent/CN112563233A/en
Application granted granted Critical
Publication of CN112563233B publication Critical patent/CN112563233B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention provides a planar package and a production method, comprising: a base island; the chip is pasted on the base island; the inner pin is connected with the chip through a welding wire; the outer pin is connected with the inner pin; the interconnection island is arranged on the strip-shaped structure on the inner pins and enables the outer pins to be interconnected together; and the plastic package body is fixedly sealed on the base island, the inner pins, the welding wires, the chip and the interconnection island are all packaged inside, the outer pins are outside the plastic package body, and all the outer pins are positioned on the same plane. According to the invention, the ground wire can be directly arranged between the grounding end of the chip and the interconnection island, so that the ground wire is prevented from being arranged at the edge of the base island. Therefore, the external PCB wiring design of the whole packaging part can be simplified, the size of the base island in the packaging part is adjusted to be more adaptive to the size of the chip, and meanwhile, the base island does not need to be plated with silver (the bonding property of silver and a plastic packaging material contact surface is poor), so that the risk of carrier layering is reduced; routing on the interconnection island improves the flexibility of routing, and can effectively avoid the conditions of wire crossing and dense routing.

Description

Planar packaging part and production method thereof
Technical Field
The invention belongs to the technical field of planar packaging parts, and particularly relates to a planar packaging part and a production method thereof.
Background
At present, electronic products are developed in a direction of multifunction and miniaturization, and thus, high-speed and high-density design requirements are put on a packaging technology. SMT (Surface Mounting Technology) packaging Technology has been developed, and is represented by the following forms: PLCC, SOP, SOJ, TSOP, TSSOP, PQFP, QFJ, LQFP, TQFP, and the like. Among them, the LOW-Profile Quad package (LQFP) is one of surface mount packages, and plastic packages account for most of the existing packages, and are suitable for miniaturized high-pin thin product packages, mainly applied to digital logic circuits such as microprocessors and gate arrays, and analog and hybrid large-scale integrated circuits, and have mature production process and wide application.
When the conventional LQFP meets the routing requirement of a base island, silver is required to be plated on the surface of the base island, and layering is easy to occur. When the LQFP planar package has a plurality of external pins connected to the same potential, all the corresponding internal pins need to be directly connected to the base island, and the intersection of the bonding wires may occur, thereby causing a problem that the bonding is difficult to be realized or the reliability is reduced due to dense bonding.
In the prior invention (CN 102522392A), a solution to solve the above problem is disclosed by using a ground ring structure, that is, a connecting rib at four corners inside the package is connected to a ring island surrounding the base island, and the ring island is connected to the base island by a base island connecting rib. The area around the chip must be increased to avoid being affected by glue, the area of the base island must be increased, the base island must be plated with silver for routing, but the bonding property of silver and plastic package materials is poor, so that the probability of layering is greatly improved, the condition of wire crossing or dense wire routing can occur when the number of base island wire routing is large in the common lead frame, the electrical performance is affected, and the potential risk of the problems of welding wire reliability and failure caused by layering is huge.
In addition, although the conventional LQFP package is provided with the grounding ring with the annular structure, in order to avoid wire bonding on the base island, the connecting ribs at four corners inside the package body are connected with the annular island surrounding the base island, and the ground wire can be directly bonded on the grounding ring, the LQFP package is often provided with a plurality of pins connected with the same potential, and at the moment, the wire bonding of the conventional LQFP package is still various and scattered, so that the reliability of the whole package cannot be improved.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a planar package and a method for manufacturing the same, which can enhance design reliability and improve feasibility of a manufacturing process.
In order to achieve the purpose, the invention adopts the following technical scheme:
the planar package of the present invention includes: a base island; at least one chip adhered to the base island; the inner pin is connected with the chip through a welding wire; the outer pin is connected with the inner pin; the interconnection island is arranged on the strip-shaped structure on the inner pins to interconnect the outer pins together; and a plastic package body which is fixedly sealed on the base island and internally packages the inner pins, the welding wires, the chip and the interconnection island, wherein the outer pins are outside the plastic package body, and all the outer pins are in the same plane.
According to the plane packaging piece, the ground wire can be directly arranged between the grounding end of the chip and the interconnection island, and the ground wire is prevented from being arranged at the edge of the base island. Therefore, the external PCB wiring design of the whole packaging part can be simplified, the size of the base island in the packaging part is adjusted to be more adaptive to the size of the chip, and meanwhile, the base island does not need to be plated with silver (the bonding property of silver and a plastic packaging material contact surface is poor), so that the risk of carrier layering is reduced; routing on the interconnection island improves the flexibility of routing, and can effectively avoid the conditions of wire crossing and dense routing.
In the planar package, the lower end surface of the base island is located outside the package, or the lower end surface of the base island is located inside the package.
In the planar package, the interconnection island is disposed outside the base island and is flush with the inner leads, and the base island is connected to the ribs at four corners inside the planar package.
In the planar package, the ground ring has a ring-shaped structure in which a lower end surface is located higher than an upper end surface of the base island.
In the planar package, the lower end surface of the interconnection island is higher than the upper end surface of the base island, and the interconnection island and the base island are connected through a rib plate.
In addition, the chip comprises two chips, namely a first chip and a second chip; the first chip and the second chip are arranged in an up-and-down stacked mode.
The first chip is bonded on the upper end face of the base island through the first bonding part; the second chip is bonded on the upper end face of the first chip through the second bonding portion.
And the second chip is connected with the interconnection island through a first welding wire, the first chip is connected with the inner pin through a second welding wire, and the first chip is connected with the second chip through a third welding wire.
The invention also provides a production method of the planar packaging part, which comprises the following steps:
step one, thinning the wafer:
for a single chip package, thinning the wafer to 200-280 μm, and sticking an adhesive film on the back of the wafer; for the double-chip stacked package, the first chip thins the wafer to 200-280 μm, the second chip thins the wafer to 200-280 μm, and the wafer is pasted with a DAF film;
step two, scribing:
setting the scribing advancing speed within 10mm/s to scribe the wafer;
step three, core loading:
the lead frame is processed by adopting a double-sided roughening process, an interconnection island is preset on the lead frame, the position of the lower end face of the interconnection island is higher than the position of the upper end face of a base island, the interconnection island is connected with the base island through a rib plate, for a single-chip packaging piece, the lead frame processed by adopting the double-sided roughening process is adhered with a chip by adopting conductive adhesive, after the adhesive is dispensed on the base island, a chip is adhered to the base island, the fact that a colloid is filled between the chip and the base island is ensured, no gap is left, the thickness of the colloid is controlled to be 10-50 mu m, the climbing height of the side face of the chip is not more than 75% of the thickness of the chip, after all chips are adhered, the lead frame adhered with the chip is baked for 3 hours at 175 ℃ by adopting an anti-oxidation baking process; for a double-chip stacked package, a first chip is mounted, a first chip directly adhered to a base island is mounted by the same method as a single-chip package, a second chip is mounted, a second chip with an adhesive film is directly adhered to the first chip, and after all the chips are adhered, the lead frame adhered with the chips is baked for 3 hours at the temperature of 150 ℃ by adopting an anti-oxidation baking process;
step four, pressure welding:
bonding the single chip package by using a gold wire with 3N purity; for a dual chip package: bonding the lead frame processed by the double-sided roughening process, selecting a gold wire with 3N purity, bonding a second bonding wire between the first chip and the inner pin, bonding a third bonding wire between the first chip and the second chip, and finally bonding a first bonding wire between the second chip and the interconnection island;
step five, before plastic package, carrying out plasma cleaning on the frame which is subjected to pressure welding, removing contamination in the pressure welding process, and immediately carrying out plastic package on the frame which is subjected to plasma cleaning;
step six, plastic packaging;
seventhly, cutting middle ribs;
step eight, electroplating;
and step nine, printing, testing, inspecting and warehousing the electroplated plastic package part in sequence to obtain the LQFP planar package part with the interconnection islands.
Compared with the prior art, the invention has the following beneficial effects:
according to the technical scheme of the invention, the ground wire can be directly arranged between the grounding end of the chip and the interconnection island, so that the ground wire is prevented from being arranged at the edge of the base island. Therefore, the external PCB wiring design of the whole packaging part can be simplified, the size of the base island in the packaging part is adjusted to be more adaptive to the size of the chip, and meanwhile, the base island does not need to be plated with silver (the bonding property of silver and a plastic packaging material contact surface is poor), so that the risk of carrier layering is reduced; routing on the interconnection island improves the flexibility of routing, and can effectively avoid the conditions of wire crossing and dense routing.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a single chip package in a planar package according to the present invention.
Fig. 2 is a schematic structural diagram of a dual-chip package in a planar package according to the present invention.
Fig. 3 is a schematic structural diagram of a lead frame and interconnection islands of the planar package according to the present invention.
In the figure: 1. the chip comprises a base island, 2 interconnection islands, 3 outer pins, 4 plastic package bodies, 5 first welding lines, 6 inner pins, 7 first chips, 8 first bonding parts, 9 second chips, 10 second bonding parts, 11 second welding lines, 12 rib plates, 13 third welding lines and 14 grounding rings.
Detailed Description
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The following detailed description is exemplary in nature and is intended to provide further details of the invention. Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention.
The package of the present invention has two forms of single chip planar package and double chip planar package, fig. 1 is a structural schematic diagram of the single chip planar package, and fig. 2 is a structural schematic diagram of the double chip planar package.
As shown in fig. 1, the planar package of the present invention includes: the semiconductor package comprises a base island 1, an interconnection island 2, an outer pin 3, a plastic package body 4, a first welding line 5, an inner pin 6, a first chip 7, a first bonding part 8, a second welding line 11 and a rib plate 12.
The first chip 7 is bonded and fixed to the upper end surface of the base island 1 by a first bonding portion 8, and the first bonding portion 8 may be made of an insulating paste or a conductive paste. The first chip 7 is connected with the inner pin 6 through the second welding line 11 after being adhered to the upper end face of the base island 1, and the inner pin 6 is connected with the outer pin 3.
And strip-shaped structure small islands with the interconnection function are designed on the inner pins 6 to form interconnection islands 2, and the interconnection islands 2 enable the outer pins 3 to be also interconnected together. The interconnection island 2 is arranged outside the base island 1 and is in the same plane with the inner pin 6. The first chip 7 is connected to the interconnection island 2 by a first bonding wire 5. The base island 1 is directly connected with the rib plates 12 at four corners inside the packaging body, and other inner pins 6 are not affected. In addition, the plastic package body 4 is fixedly sealed around the base island 1, in the embodiment shown in fig. 1, the base island 1, the interconnection island 2, the first bonding wire 5, the inner lead 6, the first chip 7 and the second bonding wire 11 are all sealed in the plastic package body 4, the outer lead 3 is located outside the plastic package body 4, and all the outer leads 3 are located on the same plane.
Here, the lower end face of the interconnection island 2 is higher than the upper end face of the base island 1, and the interconnection island 2 and the base island 1 are connected through the rib 12.
In addition, in the present embodiment, the lower end surface of the base island 1 is encapsulated in the plastic encapsulation 4, so that the single chip encapsulation part with the carrier not exposed is formed.
Next, the structure of the dual chip package will be described in detail with reference to fig. 2.
As shown, in contrast to the single chip package of fig. 1, in the dual chip package, the first chip 7 and the second chip 9 are stacked up and down. The first chip 7 is bonded to the upper end surface of the base island 1 via the first bonding portion 8, and then the second chip 9 is bonded to the upper end surface of the first chip 7 via the second bonding portion 10. The second chip 9 is connected with the interconnection island 2 through the first bonding wire 5, the first chip 7 is connected with the inner pin 6 through the second bonding wire 11, and the first chip 7 and the second chip 9 are connected through the third bonding wire 13. Here, the second adhesive portion 10 may be formed of a wafer back side DAF film.
Like the single chip package, as in the embodiment of fig. 2, the lower end surface of the base island 1 is encapsulated in the plastic package body 4 to form a carrier-exposed dual chip package, and in the present invention, the lower end surface of the base island 1 may not be encapsulated in the plastic package body 4 to form a carrier-exposed dual chip package.
The design of the interconnect islands 2 simplifies the routing design of the circuit peripheral PCB, a function that is not available with the ground rings used in the prior art. The position and the design of the interconnection island 2 can be flexibly set according to actual needs, and the position without the interconnection island 2 outside the base island 1 can realize the increase of the area of a carrier by moving back the inner pin 6, thereby increasing the adaptability of various chip areas. This function is also not available in the ground ring used in the prior art because the ring outside the base island 1 defines the area of the base island 1, which is difficult to meet the large chip size package requirement. Moreover, the interconnection island 2 can effectively reduce the possibility of water vapor intrusion from the outside and improve the reliability, and the function is not possessed by the grounding ring used in the prior art, because the four-corner connecting ribs in the design of the grounding ring are connected with the carrier and the grounding ring, the routing and the chip part are not effectively isolated. The interconnection island 2 can transfer the carrier routing to the grounding ring routing, so that the carrier can be free from silver plating treatment, the layering probability is reduced, the reliability is improved, and the function of the interconnection island is consistent with that of the grounding ring.
As shown in fig. 1 and 2, the flat package of the present invention may be provided with a ground ring 14. The lower end face of the grounding ring 14 is higher than the upper end face of the base island 1, is connected with the base island 1 through the rib plate 12, and forms a ring shape along the edge direction of the base island 1.
In addition, fig. 3 is a schematic structural diagram of the lead frame and the interconnection island 2 of the planar package according to the present invention. As shown in the figure, the base island 1 is rectangular, the interconnection island 2 is arranged in a strip structure of the inner pin 6 on each side of the lead frame, and the interconnection island 2 is connected with the base island 1 through the rib plate 12. Four angles of the base island 1 are respectively connected with the frame through rib plates 12, so that the flatness of the base island 1 is ensured, and the strength is also increased.
Here, the shape of the base island 1 is not limited to a square shape, and may be a rectangular shape or the like. The shape of the interconnection island 2 is also not limited to a stripe structure as long as it has an interconnection function so that the outer leads 3 can be interconnected together. Also, the interconnection island 2 need not be provided on the inner lead on each side of the lead frame.
The production process flow of the planar packaging part is as follows:
1, single chip Package
Thinning a wafer, scribing the wafer, mounting a core, press welding, cleaning before plastic packaging, plastic packaging and post curing, cutting a middle rib, electroplating, printing and cutting the rib, testing, inspecting, packaging and warehousing;
2, double chip package
Thinning a wafer, scribing the wafer, mounting a core on a double chip, press welding, cleaning before plastic packaging, plastic packaging and post curing, cutting a middle rib, electroplating, printing and cutting the rib, testing, inspecting, packaging and warehousing.
In addition, the invention also provides a production method of the planar packaging part, which comprises the following steps:
step 1: wafer thinning
For a single chip package: thinning the wafer to 200-280 μm by the existing chip warpage prevention process, and sticking a common adhesive film on the back of the wafer; for a dual chip package: the wafer where the first chip 7 is located is thinned in the same way as a single chip package; thinning the wafer where the second chip 9 is located to 200-280 μm by using the existing chip warpage prevention process, and attaching a DAF film on the back of the wafer;
step 2: scribing
During scribing, setting the scribing advancing speed within 10mm/s, and adopting the anti-cracking process for control;
and step 3: upper core
The lead frame is processed by a double-sided roughening process, the lead frame is preset with an interconnection island 2, the position of the lower end face of the interconnection island 2 is higher than the position of the upper end face of the base island 1, and the interconnection island 2 is connected with the base island 1 through a rib plate 12; for a single chip package: the lead frame processed by the double-sided roughening process is used, the chips are adhered by the conductive adhesive of the first adhering part 8, after the adhesive is dispensed on the base island 1, one chip is adhered to the base island 1, the situation that the space between the chip and the base island 1 is filled with the adhesive is ensured, no gap is left, the thickness of the adhesive is controlled to be 10-50 microns, the side climbing height of the chip is not more than 75% of the thickness of the chip, and after all the chips are adhered, the lead frame adhered with the chips is baked for 3 hours at 175 ℃ by adopting an anti-oxidation baking process; for a dual chip package: core feeding for the first time: a first chip 7 directly adhered on the base island 1, which is cored using the same method as the single chip package; and (3) core feeding for the second time: directly adhering the second chip 9 with the adhesive film on the back to the first chip 7, and baking the lead frame adhered with the chips for 3 hours at 150 ℃ by adopting an anti-oxidation baking process after all the chips are adhered;
and 4, step 4: pressure welding
Bonding the single chip packaging part by using a gold wire with 3N purity; for a dual chip package: the lead frame processed by the double-sided roughening process is used for pressure welding, a gold wire with 3N purity is selected, a second welding wire 11 between the first chip 7 and the inner pin 6 is firstly pressure welded, a third welding wire 13 between the first chip 7 and the second chip 9 is then pressure welded, and finally a first welding wire 5 between the second chip 9 and the interconnection island 2 is pressure welded;
and 5: before plastic package, carrying out plasma cleaning on the frame which is subjected to pressure welding, removing contamination in the pressure welding process, immediately carrying out plastic package on the frame which is subjected to plasma cleaning, and preventing secondary contamination;
step 6: plastic packaging by adopting the same process as the conventional common LQFP package;
and 7: adopting the same process as the prior common LQFP package to cut the middle ribs;
and 8: electroplating by adopting the same process as the prior common LQFP package;
and step 9: and printing, testing, inspecting and warehousing the electroplated plastic package in sequence by adopting the same process as the conventional common LQFP package to obtain the LQFP planar package with the interconnection island 2.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.

Claims (7)

1. A planar package, comprising:
a base island;
at least one chip adhered to the base island;
the inner pin is connected with the chip through a welding wire;
the outer pin is connected with the inner pin;
the interconnection island is arranged on the strip-shaped structure on the inner pins to interconnect the outer pins together;
a plastic package body which is fixedly sealed on the base island and internally packages the inner pins, the welding lines, the chip and the interconnection island, the outer pins are arranged outside the plastic package body, and all the outer pins are positioned on the same plane;
the position of the lower end face of the grounding ring is higher than that of the upper end face of the base island, so that a ring-shaped structure is formed and is connected with the base island through a rib plate;
the position of the lower end face of the interconnection island is higher than that of the upper end face of the base island, and the interconnection island is connected with the base island through a rib plate.
2. The planar package according to claim 1, wherein the lower end surface of the base island is located outside the molding package, or the lower end surface of the base island is located inside the molding package.
3. The planar package of claim 1, wherein the interconnection island is disposed outside the base island and is coplanar with the inner leads, and the base island is connected to four corner ribs inside the planar package.
4. The planar package of claim 1, wherein the chip comprises two pieces, namely a first chip and a second chip; the first chip and the second chip are arranged in an up-and-down stacked mode.
5. The planar package of claim 4, wherein the first chip is bonded to the upper end surface of the base island by a first bonding portion; the second chip is bonded on the upper end face of the first chip through the second bonding portion.
6. The planar package of claim 5, wherein the second chip is connected to the interconnection islands by first bonding wires, the first chip is connected to the inner leads by second bonding wires, and the first chip and the second chip are connected by third bonding wires.
7. A method for producing a planar package, the planar package comprising:
a base island;
at least one chip adhered to the base island;
the inner pin is connected with the chip through a welding wire;
the outer pin is connected with the inner pin;
the interconnection island is arranged on the strip-shaped structure on the inner pins to interconnect the outer pins together;
a plastic package body which is fixedly sealed on the base island and internally packages the inner pins, the welding wires, the chip and the interconnection island, wherein the outer pins are outside the plastic package body, and all the outer pins are in the same plane;
the position of the lower end face of the grounding ring is higher than that of the upper end face of the base island, so that a ring-shaped structure is formed and is connected with the base island through a rib plate;
the position of the lower end face of the interconnection island is higher than that of the upper end face of the base island, and the interconnection island is connected with the base island through a rib plate;
the lower end surface of the base island is positioned outside the plastic package body, or the lower end surface of the base island is positioned in the plastic package body;
the interconnection island is arranged outside the base island and is positioned on the same plane with the inner pin, and the base island is connected with the connecting ribs at the four corners inside the planar packaging body;
the production method comprises the following steps:
step one, thinning the wafer:
for a single chip package, thinning the wafer to 200-280 μm, and sticking an adhesive film on the back of the wafer; for the double-chip stacked package, the first chip thins the wafer to 200-280 μm, the second chip thins the wafer to 200-280 μm, and the wafer is pasted with a DAF film;
step two, scribing:
setting the scribing advancing speed within 10mm/s to scribe the wafer;
step three, core loading:
the lead frame is processed by adopting a double-sided roughening process, an interconnection island is preset on the lead frame, the position of the lower end face of the interconnection island is higher than the position of the upper end face of a base island, the interconnection island is connected with the base island through a rib plate, for a single-chip packaging piece, the lead frame processed by adopting the double-sided roughening process is adhered with a chip by adopting conductive adhesive, after the adhesive is dispensed on the base island, a chip is adhered to the base island, the fact that a colloid is filled between the chip and the base island is ensured, no gap is left, the thickness of the colloid is controlled to be 10-50 mu m, the climbing height of the side face of the chip is not more than 75% of the thickness of the chip, after all chips are adhered, the lead frame adhered with the chip is baked for 3 hours at 175 ℃ by adopting an anti-oxidation baking process; for a double-chip stacked package, a first chip is mounted, a first chip directly adhered to a base island is mounted by the same method as a single-chip package, a second chip is mounted, a second chip with an adhesive film is directly adhered to the first chip, and after all the chips are adhered, the lead frame adhered with the chips is baked for 3 hours at the temperature of 150 ℃ by adopting an anti-oxidation baking process;
step four, pressure welding:
bonding the single chip packaging part by using a gold wire with 3N purity; for a dual chip package: bonding the lead frame processed by the double-sided roughening process, selecting a gold wire with 3N purity, bonding a second bonding wire between the first chip and the inner pin, bonding a third bonding wire between the first chip and the second chip, and finally bonding a first bonding wire between the second chip and the interconnection island;
step five, before plastic package, carrying out plasma cleaning on the frame which is subjected to pressure welding, removing contamination in the pressure welding process, and immediately carrying out plastic package on the frame which is subjected to plasma cleaning;
step six, plastic packaging;
seventhly, cutting middle ribs;
step eight, electroplating;
and step nine, printing, testing, inspecting and warehousing the electroplated plastic package part in sequence to obtain the LQFP planar package part with the interconnection islands.
CN202011426250.3A 2020-12-09 2020-12-09 Planar packaging part and production method thereof Active CN112563233B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011426250.3A CN112563233B (en) 2020-12-09 2020-12-09 Planar packaging part and production method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011426250.3A CN112563233B (en) 2020-12-09 2020-12-09 Planar packaging part and production method thereof

Publications (2)

Publication Number Publication Date
CN112563233A CN112563233A (en) 2021-03-26
CN112563233B true CN112563233B (en) 2023-04-11

Family

ID=75059993

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011426250.3A Active CN112563233B (en) 2020-12-09 2020-12-09 Planar packaging part and production method thereof

Country Status (1)

Country Link
CN (1) CN112563233B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809037A (en) * 2021-09-22 2021-12-17 宁波港波电子有限公司 Chip packaging structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4705881B2 (en) * 2006-05-09 2011-06-22 パナソニック株式会社 Lead frame and semiconductor device using the same
CN102522392B (en) * 2011-12-31 2014-11-05 天水华天科技股份有限公司 e/LQFP (low-profile quad flat package) planar packaging part with grounded ring and production method of e/LQFP planar packaging part with grounded ring
CN205723522U (en) * 2016-04-26 2016-11-23 上海爱矽半导体科技有限公司 A kind of lead frame
CN212113711U (en) * 2020-06-15 2020-12-08 杰群电子科技（东莞）有限公司 Lead frame and TO packaging structure

Also Published As

Publication number Publication date
CN112563233A (en) 2021-03-26

Similar Documents

Publication Publication Date Title
US20030092205A1 (en) Crack-preventive semiconductor package
JP3837215B2 (en) Individual semiconductor device and manufacturing method thereof
WO2006018671A1 (en) Mixed wire semiconductor lead frame package
JPH09312375A (en) Lead frame, semiconductor device and manufacture thereof
KR20010014945A (en) Method of manufacturing a semiconductor device
CN112563233B (en) Planar packaging part and production method thereof
JP2003174131A (en) Resin-sealed semiconductor device and method of manufacturing the same
US20150084171A1 (en) No-lead semiconductor package and method of manufacturing the same
JP2003318360A (en) Semiconductor device and method of manufacturing the same
JPH07153904A (en) Manufacture of laminar type semiconductor device, and semiconductor package manufactured thereby
CN215183913U (en) Quad flat non-leaded package structure
KR100206082B1 (en) Semiconductor device and method for manufacturing the same
CN101211794A (en) Method for manufacturing a leadframe, packaging method for semiconductor element and semiconductor package product
CN216871961U (en) Semiconductor device with a plurality of semiconductor chips
US20200321228A1 (en) Method of manufacturing a lead frame, method of manufacturing an electronic apparatus, and electronic apparatus
US20040159929A1 (en) Semiconductor die package having two die paddles
JPS6370532A (en) Semiconductor device
CN218827104U (en) Chip packaging structure with short wiring length
CN219958992U (en) QFN packaging structure of hybrid interconnection
CN106298749B (en) Light emitting diode, electronic device and manufacturing method thereof
CN218160365U (en) Packaging structure
CN220627806U (en) Novel packaging structure's power module
CN218996696U (en) Packaging structure for improving chip pin density
CN214956854U (en) Chip packaging structure
CN113629034A (en) Low-cost and high-applicability SOP chip sealing frame and packaging process

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant