CN113629034A - Low-cost and high-applicability SOP chip sealing frame and packaging process - Google Patents
Low-cost and high-applicability SOP chip sealing frame and packaging process Download PDFInfo
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- CN113629034A CN113629034A CN202111190040.3A CN202111190040A CN113629034A CN 113629034 A CN113629034 A CN 113629034A CN 202111190040 A CN202111190040 A CN 202111190040A CN 113629034 A CN113629034 A CN 113629034A
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- 238000007789 sealing Methods 0.000 title claims abstract description 32
- 238000012858 packaging process Methods 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 78
- 238000004806 packaging method and process Methods 0.000 claims abstract description 30
- 239000004033 plastic Substances 0.000 claims description 34
- 239000011521 glass Substances 0.000 claims description 24
- 239000005022 packaging material Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 238000001816 cooling Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 238000007664 blowing Methods 0.000 claims description 3
- 230000001680 brushing effect Effects 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 239000000047 product Substances 0.000 description 22
- 239000008710 crystal-8 Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009954 braiding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a low-cost and high-applicability SOP chip sealing frame and a packaging process, and belongs to the technical field of integrated circuits. The invention adopts an integral slide base island, and a chip area and a crystal area are planned on the slide base plate, so that chip main bodies and crystals with different sizes can be installed, the compatibility is better, the chip main bodies are placed in the specified chip area, the crystals are placed in the crystal area, the chip main bodies and the crystals work normally and do not influence each other, the chip packaging design mode is simpler, the product strength is higher, and the quality is better.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-cost and high-applicability SOP chip sealing frame and a packaging process.
Background
The packaging frame is used as a basic support of a packaging link, the molding structure of a product is determined, along with diversification and complex functions of the product, and a single packaging form can not meet the functional requirements of the current product design.
Traditional SOP chip package is only to a certain product, the encapsulation frame can only satisfy our current product demand, and close to the SIP level of chip and crystal, then need customize special frame, along with the size constantly change of chip and crystal, single frame can not satisfy the requirement of a plurality of products already, so on and so on, then need to customize diversified frame can satisfy the design size of our chip, and to us, the manpower, material resources, financial resources consume greatly, can't satisfy present product market demand.
And the chip and the crystal of the traditional SOP chip packaging frame generally adopt an independent chip carrying base island, the packaging frame is provided with a plurality of containing cavities and a plurality of wiring channels, the uneven distribution of the internal quality can be caused after the product is packaged, the layering phenomenon can be easily caused, and the product is easy to damage.
In the aspect of process design, when the chip and the crystal are sealed, a plurality of independent manufacturing processes are required to be coordinated and matched with each other to meet the current requirement, so that the complexity of the process and the fault tolerance of the product are greatly increased, and the periodicity of the product is greatly increased.
For the reasons mentioned above, in order to meet the package design requirements of the current products, the process design is sacrificed and the chip package cost is increased, and aiming at the problems existing in the prior art, the invention aims to provide an SOP chip sealing frame and a package process with low cost and strong applicability, which have obvious advantages in the aspects of process flow and cost reduction.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a low-cost and high-applicability SOP chip sealing frame and a packaging process, so as to solve the problems that the packaging frame in the prior art can only meet the current product requirements, a single frame cannot meet the requirements of a plurality of products along with the continuous change of the sizes of chips and crystals, and an integrated circuit board is complex in structure and poor in overall performance of the products.
In order to achieve the purpose, the invention adopts the following technical scheme:
the utility model provides a low-cost SOP chip that suitability is strong closes a frame, is including closing a frame, close a frame including plastic packaging material frame, slide glass base island and a plurality of pin, slide glass base island sets up on the plastic packaging material frame, the pin divides two sets of symmetries to set up plastic packaging material frame both sides, it is regional with the crystal to divide into chip on the slide glass base island, be provided with the chip main part on the chip region, be provided with the crystal on the crystal region, the chip main part pass through the lead wire respectively with the crystal with the pin electricity is connected.
On the basis of the above scheme, further, the material of plastic envelope material frame is epoxy, and material stable in structure, intensity is high, and is not fragile to the radiating effect is good.
On the basis of the scheme, the slide glass base island and the pins are made of copper, and the surfaces of the slide glass base island and the pins are plated with silver, so that signal attenuation can be reduced, and the signal transmission quality and efficiency are ensured.
On the basis of the scheme, further, the chip region and the crystal region have the minimum distance of 0.1mm, so that the minimum distance between the chip region and the crystal region can be satisfied, a certain space is reserved between the chip main body and the crystal, and the chip main body and the crystal can work normally without mutual influence.
On the basis of the scheme, further, the maximum boundary size of the chip region and the crystal region is matched with the boundary size of the slide glass substrate island, so that the maximum size of the current chip main body and the size sum of crystals can be contained, the chip main bodies and the crystals with different sizes can be installed, and the compatibility is good.
On the basis of the above scheme, further, the model of the chip main body is: R1V1, wherein the crystal is of the type: SMD crystal.
On the basis of the scheme, the number of the pins in each group is seven, the two groups of pins are arranged in an axisymmetric manner by taking the vertical central line of the plastic package frame as an axis, the pins in each group are respectively numbered as one, two, three, four, five, six and seven from top to bottom, the number of the leads is ten, one side of the chip main body is respectively and electrically connected with the first, second, third, fourth and sixth pins in the group of pins through the leads, and the fifth and seventh pins are not connected with the wires; the input end of the chip main body is electrically connected with the anode of the crystal through one lead, and the output end of the chip main body is electrically connected with the cathode of the crystal through the other lead; the other side of the chip main body is respectively and electrically connected with the second, the fourth and the sixth pins in the other group of pins through the leads, and the first, the third, the fifth and the seventh pins are not connected with wires.
On the basis of the scheme, the lead, the pin, the crystal and the chip body are further connected by adopting a bonding alloy wire process, and the stable connection structure and the stable conductivity are ensured by adopting the mode.
A packaging process of an SOP chip sealing frame with low cost and strong applicability comprises the following steps:
the method comprises the following steps that firstly, a slide glass base island and a plurality of pins are packaged by a plastic package frame to form a sealed frame;
secondly, brushing a layer of conductive adhesive on the slide glass substrate island;
thirdly, the first chip loading machine gripper sucks the cut chip main body from the wafer, presses downwards after reaching the appointed chip area, enables the chip main body to be in contact with the chip loading base island, and enables the chip main body to be fixed on the chip loading base island through conductive adhesive;
fourthly, a second chip loader gripper sucks the crystal from the braid, the second chip loader gripper sucks the front side of the crystal, the second chip loader gripper rotates 180 degrees, the back side of the crystal faces upwards, a chip mounting device sucks the back side of the crystal, the second chip loader gripper is loosened, the chip mounting device moves downwards after moving to the crystal area in parallel, the crystal is in contact with the chip carrying base island, the front side of the crystal is fixed on the chip carrying base island through a conductive adhesive, and the chip mounting device is a crystal mounting and picking device;
fifthly, electrically connecting the chip main body with each pin through a lead, wherein the crystal is electrically connected with the chip main body through the lead;
and sixthly, putting the whole sealing frame into a mold press grinding tool, injecting plastic packaging material at high temperature, surrounding the plastic packaging material frame, the slide glass substrate island, the chip main body, the crystal and the pins to form a packaging part, cooling the whole packaging part in a cold air blowing mode, and forming a plastic packaging body by the plastic packaging material under the cooling action.
On the basis of the scheme, further, the sealed frame packaging part after being subjected to plastic packaging is placed into an ultrasonic scanner to detect whether an air hole exists or not, so that the layering condition of the packaging part is detected, and the quality of a product is guaranteed.
The invention has the beneficial effects that:
the SOP chip sealing frame and the packaging process provided by the invention have the advantages that:
the invention adopts an integral slide base island, a chip area and a crystal area are planned on the slide base plate, chip main bodies and crystals with different sizes can be fixed, the compatibility is better, the chip main bodies are placed in the specified chip area, the crystals are placed in the crystal area, the chip main bodies and the crystals work normally and do not influence each other, the chip packaging design mode is simpler, the product strength is higher, the quality is better, a mold does not need to be redesigned for many times, the mold opening times and cost are reduced, the production period of the product is greatly shortened, the use flexibility is improved, an additional packaging structure is not needed to be added, and the input cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic plane structure diagram of an SOP chip sealing frame with low cost and strong applicability according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an SOP chip-on-package frame chip and a crystal with low cost and high applicability according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a chip region and a crystal region of an SOP chip sealing frame with low cost and high applicability according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a chip of an SOP chip sealing frame with low cost and strong applicability according to an embodiment of the present invention, which is connected to a pin through a lead;
fig. 5 is a schematic diagram of a packaging process of the SOP chip sealing frame with low cost and strong applicability according to the embodiment of the present invention.
Reference numerals:
1. closing and sealing the frame; 2. plastic packaging material frames; 3. carrying a glass substrate; 4. a pin; 5. a chip region; 6. a crystal region; 7. a chip body; 8. a crystal; 9. a lead wire; 10. a wafer; 11. a first die bonder gripper; 12. braiding; 13. a second chip mounting machine gripper; 14. a patch device.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
As shown in fig. 1 to 5, schematic structural diagrams of an SOP chip sealing frame and a packaging process with low cost and strong applicability provided by embodiments of the present invention are illustrated with reference to the accompanying drawings, and specific structures and steps are as follows.
The invention provides a low-cost and high-applicability SOP chip sealing frame, which comprises a sealing frame 1, wherein the sealing frame 1 comprises a plastic package frame 2, a slide substrate 3 and a plurality of pins 4, the slide substrate 3 is arranged on the plastic package frame 2, the pins 4 are symmetrically arranged on two sides of the plastic package frame 2 in two groups, the slide substrate 3 is divided into a chip area 5 and a crystal area 6, a chip main body 7 is arranged on the chip area 5, a crystal 8 is arranged on the crystal area 6, and the chip main body 7 is electrically connected with the crystal 8 and the pins 4 through leads 9.
It needs to be supplemented that the plastic package material frame 2 is made of epoxy resin, and has the advantages of stable material structure, high strength, difficult damage and good heat dissipation effect.
It is necessary to supplement that the material of the slide glass base island 3 and the pin 4 are both copper, and the surfaces of the slide glass base island 3 and the pin 4 are plated with silver, so that signal attenuation can be reduced, and the signal transmission quality and efficiency can be ensured.
It is supplementary to need, chip region 5 and crystal region 6 minimum separation distance 0.1mm satisfy the minimum interval size between the two for leave certain space between chip main part 7 and the crystal 8, guarantee that chip main part 7 and crystal 8 can normally work, do not influence each other.
It is supplementary to be added that the maximum boundary size of the chip region 5 and the crystal region 6 is matched with the boundary size of the slide base island 3, so as to ensure that the current maximum size of the chip body 7 and the size sum of the crystal 8 can be accommodated, the chip bodies 7 and the crystals 8 with different sizes can be installed, and the compatibility is good.
It should be added that the model number of the chip body 7 is: R1V1, crystal 8 type: SMD crystal.
It needs to be supplemented that the number of each group of pins 4 is seven, and two groups of pins 4 are arranged in an axisymmetric manner by taking the vertical central line of the plastic package frame 2 as an axis, each group of pins 4 is respectively numbered as one, two, three, four, five, six and seven from top to bottom, the number of the leads 9 is ten, one side of the chip main body 7 is respectively electrically connected with the first, second, third, fourth and sixth pins 4 in the group of pins 4 through the leads 9, and the fifth and seventh pins 4 are not connected with wires; the input end of the chip main body 7 is electrically connected with the anode of the crystal 8 through one lead 9, and the output end of the chip main body 7 is electrically connected with the cathode of the crystal 8 through the other lead 9; the other side of the chip body 7 is electrically connected with the second, fourth and sixth pins 4 in the other group of pins 4 through leads 9 respectively, and the first, third and fifth and seventh pins 4 are not connected with wires.
It should be added that the leads 9 are connected with the leads 4, the crystal 8 and the chip body 7 by a bonding alloy wire process, and in this way, the connection structure and the conductivity are stable.
A packaging process of an SOP chip sealing frame with low cost and strong applicability comprises the following steps:
firstly, packaging a slide glass base island 3 and a plurality of pins 4 by using a plastic packaging material frame 2 to form a sealed frame 1;
secondly, brushing a layer of conductive adhesive on the slide glass substrate 3;
thirdly, the first chip loader gripper 11 sucks the cut chip main body 7 from the wafer 10, presses the chip main body 7 downwards after reaching the appointed chip area 5, so that the chip main body 7 is contacted with the chip loading base island 3, and the chip main body 7 is fixed on the chip loading base island 3 through a conductive adhesive;
fourthly, the second chip loader gripper 13 sucks the crystal 8 from the braid 12, the second chip loader gripper 13 sucks the front side of the crystal 8, the second chip loader gripper 13 rotates 180 degrees, the back side of the crystal 8 faces upwards, the chip mounting device 14 sucks the back side of the crystal 8, the second chip loader gripper 13 is released, the chip mounting device 14 moves downwards after moving to the crystal area 6 in parallel, the crystal 8 is in contact with the chip carrying base island 3, the front side of the crystal 8 is fixed on the chip carrying base island 3 through conductive adhesive, and the chip mounting device 14 is a crystal mounting and picking device;
fifthly, electrically connecting the chip body 7 with each pin 4 through a lead 9, and electrically connecting the crystal 8 with the chip body 7 through the lead 9;
and sixthly, putting the whole sealing frame 1 into a mold of a mold press, injecting plastic packaging material at high temperature, surrounding the plastic packaging material frame 2, the slide glass substrate 3, the chip main body 7, the crystal 8 and the pins 4 to form a packaging part, cooling the whole packaging part in a cold air blowing mode, and forming a plastic packaging body by the plastic packaging material under the cooling action.
It needs to be supplemented that the packaging part of the sealed frame 1 after plastic packaging is placed into an ultrasonic scanner to detect whether a gas hole exists, so that the layering condition of the packaging part is detected, and the quality of a product is ensured.
The SOP chip sealing frame and the packaging process provided by the embodiment of the invention have low cost and strong applicability, and can obtain the following technical effects: the invention adopts an integral chip-carrying base island, a chip area and a crystal area are planned on the chip-carrying substrate, chip main bodies and crystals with different sizes can be fixed, the compatibility is better, the chip main bodies are placed in the specified chip area, the crystals are placed in the crystal area, the chip main bodies and the crystals work normally and do not influence each other, the chip packaging design mode is simpler, the product strength is higher, the quality is better, a mold does not need to be redesigned for many times, the mold opening times and cost are reduced, the production period of the product is greatly shortened, the use flexibility is improved, an additional packaging structure is not needed to be added, the input cost is reduced, and the problems of complex structure of an integrated circuit board and poor integral performance of the product are avoided.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The utility model provides a low-cost SOP chip that suitability is strong closes frame of sealing, closes frame (1) including closing, its characterized in that: close encapsulation frame (1) including plastic packaging material frame (2), slide glass base island (3) and a plurality of pin (4), slide glass base island (3) set up on plastic packaging material frame (2), pin (4) divide into two sets of symmetry and set up plastic packaging material frame (2) both sides, divide into chip region (5) and crystal region (6) on slide glass base island (3), be provided with chip main part (7) on chip region (5), be provided with crystal (8) on crystal region (6), chip main part (7) through lead wire (9) respectively with crystal (8) with pin (4) electricity is connected.
2. The low-cost and high-applicability SOP chip close-sealing frame according to claim 1, characterized in that: the plastic packaging material frame (2) is made of epoxy resin.
3. The low-cost and high-applicability SOP chip close-sealing frame according to claim 1, characterized in that: the slide glass base island (3) and the pin (4) are both made of copper, and the surfaces of the slide glass base island (3) and the pin (4) are plated with silver.
4. The low-cost and high-applicability SOP chip close-sealing frame according to claim 1, characterized in that: the chip region (5) and the crystal region (6) are separated by a minimum distance of 0.1 mm.
5. The low-cost and high-applicability SOP chip close-sealing frame according to claim 1, characterized in that: the maximum boundary dimensions of the chip region (5) and the crystal region (6) are matched with the boundary dimensions of the slide glass base island (3).
6. The low-cost and high-applicability SOP chip close-sealing frame according to claim 3, characterized in that: the type of the chip main body (7) is as follows: R1V1, wherein the model of the crystal (8) is as follows: SMD crystal.
7. The low-cost and high-applicability SOP chip close-sealing frame according to claim 1, characterized in that: the number of each group of pins (4) is seven, the two groups of pins (4) are arranged in an axisymmetric mode by taking a vertical central line of a plastic package frame (2) as an axis, the pins (4) in each group are respectively numbered as a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin and a seventh pin from top to bottom, the number of the leads (9) is ten, one side of the chip main body (7) is respectively and electrically connected with the first pin, the second pin, the third pin, the fourth pin and the sixth pin (4) in the group of pins (4) through the leads (9), and the fifth pin and the seventh pin (4) are not connected with a wire; the input end of the chip main body (7) is electrically connected with the anode of the crystal (8) through one lead (9), and the output end of the chip main body (7) is electrically connected with the cathode of the crystal (8) through the other lead (9); the other side of the chip body (7) is respectively and electrically connected with the second, fourth and sixth pins (4) in another group of pins (4) through the leads (9), and the first, third, fifth and seventh pins (4) are not connected with wires.
8. The low-cost and high-applicability SOP chip close-sealing frame according to claim 1, characterized in that: the lead (9) is connected with the pin (4), the crystal (8) and the chip body (7) by adopting a bonding alloy wire process.
9. The packaging process of the SOP chip sealing frame is low in cost and high in applicability, and is characterized in that: the method comprises the following steps:
firstly, packaging a slide glass base island (3) and a plurality of pins (4) by using a plastic packaging material frame (2) to form a sealing frame (1);
secondly, brushing a layer of conductive adhesive on the slide glass substrate island (3);
thirdly, the first chip loading machine gripper (11) sucks the cut chip main body (7) from the wafer (10), presses downwards after reaching the appointed chip area (5), so that the chip main body (7) is contacted with the chip loading base island (3), and the chip main body (7) is fixed on the chip loading base island (3) through conductive adhesive;
fourthly, a second chip loader gripper (13) sucks the crystal (8) from a braid (12), the second chip loader gripper (13) sucks the front side of the crystal (8), the second chip loader gripper (13) rotates 180 degrees to enable the back side of the crystal (8) to face upwards, a chip mounting device (14) sucks the back side of the crystal (8), the second chip loader gripper (13) is loosened, the chip mounting device (14) moves downwards after moving to a crystal area (6) in parallel to enable the crystal (8) to be in contact with the chip mounting base island (3), and the front side of the crystal (8) is fixed on the chip mounting base island (3) through conductive adhesive;
fifthly, electrically connecting the chip body (7) with each pin (4) through a lead (9), and electrically connecting the crystal (8) with the chip body (7) through the lead (9);
and sixthly, putting the whole sealing frame (1) into a mold press grinding tool, injecting plastic packaging material at high temperature, surrounding the plastic packaging material frame (2), the slide glass base island (3), the chip main body (7), the crystal (8) and the pin (4) to form a packaging part, cooling the whole packaging part in a cold air blowing mode, and forming a plastic packaging body by the plastic packaging material under the cooling effect.
10. The packaging process of the SOP chip close packaging frame with low cost and strong applicability according to claim 9, characterized in that: and (3) placing the packaged part of the sealed frame (1) after plastic packaging into an ultrasonic scanner to detect whether a gas hole exists or not, so that the layering condition of the packaged part is detected.
Priority Applications (1)
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| US20150054145A1 (en) * | 2013-08-23 | 2015-02-26 | Texas Instruments Incorporated | Integrated circuit package with die attach paddle having at least one recessed portion |
| US20170033055A1 (en) * | 2015-07-27 | 2017-02-02 | Semiconductor Components Industries, Llc | Semiconductor leadframes and packages with solder dams and related methods |
| CN108269778A (en) * | 2018-01-09 | 2018-07-10 | 深圳电通纬创微电子股份有限公司 | A kind of biradical island SOP chip-packaging structures |
| CN109979892A (en) * | 2019-03-29 | 2019-07-05 | 无锡红光微电子股份有限公司 | The biradical island packaging frame of ESOP8 |
| CN111354646A (en) * | 2018-12-24 | 2020-06-30 | 意法半导体股份有限公司 | Method of manufacturing a semiconductor device and corresponding semiconductor device |
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| US20150054145A1 (en) * | 2013-08-23 | 2015-02-26 | Texas Instruments Incorporated | Integrated circuit package with die attach paddle having at least one recessed portion |
| US20170033055A1 (en) * | 2015-07-27 | 2017-02-02 | Semiconductor Components Industries, Llc | Semiconductor leadframes and packages with solder dams and related methods |
| CN108269778A (en) * | 2018-01-09 | 2018-07-10 | 深圳电通纬创微电子股份有限公司 | A kind of biradical island SOP chip-packaging structures |
| CN111354646A (en) * | 2018-12-24 | 2020-06-30 | 意法半导体股份有限公司 | Method of manufacturing a semiconductor device and corresponding semiconductor device |
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