CN102569274A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

Info

Publication number
CN102569274A
CN102569274A CN2012100763456A CN201210076345A CN102569274A CN 102569274 A CN102569274 A CN 102569274A CN 2012100763456 A CN2012100763456 A CN 2012100763456A CN 201210076345 A CN201210076345 A CN 201210076345A CN 102569274 A CN102569274 A CN 102569274A
Authority
CN
China
Prior art keywords
substrate
pad
upper surface
surface
die
Prior art date
Application number
CN2012100763456A
Other languages
Chinese (zh)
Inventor
李瑜镛
金锡奉
Original Assignee
日月光半导体制造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日月光半导体制造股份有限公司 filed Critical 日月光半导体制造股份有限公司
Priority to CN2012100763456A priority Critical patent/CN102569274A/en
Publication of CN102569274A publication Critical patent/CN102569274A/en

Links

Abstract

The invention relates to a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure comprises a first substrate, a first tube core, first sealing glue, a second substrate and at least one conduction column, wherein the first tube core is electrically connected to the upper surface of the first substrate; the first sealing glue covers the upper surfaces of the first tube core and the first substrate; the lower surface of the second substrate is adhered to the first sealing glue; the conduction columns pass through the first substrate, the first sealing glue and the second substrate; and the conduction columns are used as assemblies which are electrically connected in the vertical direction, and thus the distance between every two conduction columns can be shortened.

Description

半导体封装结构及其制造方法 The semiconductor package structure and a manufacturing method

技术领域 FIELD

[0001] 本发明关于一种半导体封装结构及其制造方法,详言之,关于一种堆栈式半导体封装结构及其制造方法。 [0001] The present invention relates to a semiconductor package structure and a manufacturing method, detail, package structure and to a method of manufacturing a semiconductor stacked.

背景技术 Background technique

[0002] 已知堆栈式半导体封装结构具有一上封装结构、一下封装结构及多个焊球。 [0002] Known stacked on the semiconductor package having a package structure and the package structure at a plurality of solder balls. 这些焊球位于该下封装结构的基板上。 These solder balls located on the lower substrate of the package structure. 该上封装结构的下表面接触这些焊球,以电性连接至该下封装结构。 The structure of the lower surface of the package contacting the solder balls, to be electrically connected to the lower package. 在该已知堆栈式半导体封装结构中,这些焊球为球状,因此二个焊球间的间距无法有效缩小,否则容易发生桥接(Bridge)的问题,进而造成短路的情况。 In this known structure stacked semiconductor package, spherical solder balls, and therefore the spacing between the two balls can not be effectively reduced, or prone to problems bridge (Bridge), thereby causing a short circuit.

[0003] 因此,有必要提供一种半导体封装结构及其制造方法,以解决上述问题。 [0003] Accordingly, there is a need for a semiconductor package structure and a manufacturing method to solve the above problems.

发明内容 SUMMARY

[0004] 本发明提供一种半导体封装结构,其包括一第一基板、一第一管芯、一第一封胶、 一第二基板及至少一导通柱。 [0004] The present invention provides a semiconductor package, which includes a first substrate, a first die, a first sealant, a second substrate and at least one conductive via. 该第一基板具有一上表面及一下表面。 The first substrate having an upper surface and a lower surface. 该第一管芯邻接于该第一基板的上表面,且电性连接至该第一基板的上表面。 The first die adjacent to the upper surface of the first substrate, and electrically connected to the upper surface of the first substrate. 该第一封胶包覆该第一管芯及该第一基板的上表面。 The first sealant covering the upper surface of the first die and the first substrate. 该第二基板具有一上表面及一下表面,该第二基板的下表面黏附于该第一封胶上。 The second substrate having an upper surface and a lower surface, the lower surface of the second substrate is adhered to the first sealant. 该导通柱贯穿该第一基板、该第一封胶及该第二基板。 The first conductive via through the substrate, the first sealant and the second substrate.

[0005] 在本发明中,该导通柱用以作为垂直方向电性连接的组件。 [0005] In the present invention, the assembly is used as a conductive via electrically connected to the vertical direction. 由于该导通柱的外径比已知焊球小,因此可缩小彼此间距且增加密度。 Since the outer diameter of the conductive pillar is smaller than the known solder balls, thereby reducing the gap to each other and increase the density.

[0006] 本发明另提供一种半导体封装结构的制造方法,其包括以下步骤:(a)提供一第一基板,该第一基板具有一上表面及一下表面;(b)附着一第一管芯于该第一基板的上表面,且电性连接该第一管芯至该第一基板的上表面;(c)形成一第一封胶以包覆该第一管芯及该第一基板的上表面;(d)提供一第二基板,该第二基板具有一上表面及一下表面,且黏附该第二基板的下表面于该第一封胶上;(e)形成至少一贯穿孔以贯穿该第一基板、该第一封胶及该第二基板;及(f)形成一导电金属于该至少一贯穿孔内以形成至少一导通柱。 [0006] The present invention further provides a method of manufacturing a semiconductor package, comprising the steps of: (a) providing a first substrate, the first substrate having an upper surface and a lower surface; (b) attaching a first pipe on the core surface of the first substrate and electrically connected to the first die to the upper surface of the first substrate; (c) forming a first sealant to cover the first die and the first substrate upper surface; (d) providing a second substrate, the second substrate having an upper surface and a lower surface, and the adhesion of the lower surface of the second substrate on the first sealant; (e) forming at least one hole through the first substrate, the first sealant and the second substrate; and (f) forming a conductive metal within the at least one through hole to form at least one conductive via.

附图说明 BRIEF DESCRIPTION

[0007] 图1显示本发明半导体封装结构的一实施例的示意图;及 [0007] FIG. 1 shows a schematic embodiment of a semiconductor package of the present invention; and

[0008] 图2至图10显示本发明半导体封装结构的制造方法的一实施例的示意图。 [0008] Figures 2 to 10 show a schematic of an embodiment of a method of manufacturing a semiconductor package of the present invention.

具体实施方式 Detailed ways

[0009] 参考图1,显示本发明半导体封装结构的一实施例的示意图。 [0009] Referring to FIG. 1, a schematic of an embodiment of the present invention is a semiconductor package structure. 该半导体封装结构1 包括一第一基板10、一第一管芯12、多条第一导线13、一第一封胶14、一第二基板16、一第二管芯18、多条第二导线19、一第二封胶20、至少一导通柱22、一中间胶层M及多个焊球26。 The semiconductor package 10 comprises a structure 1, a first die 12, a first plurality of wires 13, a first sealant 14, a second substrate 16, a second die 18, a first plurality of second substrate conductor 19, a second sealant 20, at least a conducting post 22, an intermediate adhesive layer and a plurality of solder balls 26 M. [0010] 该第一基板10,例如一有机基板,具有一上表面101、一下表面102、至少一第一上焊垫103及至少一第一下焊垫104。 [0010] The first substrate 10, for example, an organic substrate having an upper surface 101, a lower surface 102, at least a first upper pad 103 and at least a first pad 104. 该至少一第一上焊垫103邻接于该第一基板10的上表面101,该至少一第一下焊垫104邻接于该第一基板10的下表面102。 On the at least one first abutment pad 103 on the surface 101 of the first substrate 10, the at least one first pad 104 adjacent to the lower surface 102 of the first substrate 10.

[0011] 该第一管芯12邻接于该第一基板10的上表面101,且电性连接至该第一基板10 的上表面101。 [0011] The first die 12 abuts the upper surface 101 of the first substrate 10, and electrically connected to the upper surface 101 of the first substrate 10. 在本实施例中,该第一管芯12利用一第一胶层121黏附于该第一基板10的上表面101,且利用这些第一导线13电性连接至该第一基板10的上表面101。 In the present embodiment, the first die 12 using a first adhesive layer 121 adhered to the upper surface 101 of the first substrate 10, and the first use of these wires 13 is electrically connected to the upper surface of the first substrate 10 101. 然而,在其它实施例中,该第一管芯12利用倒装焊方式电性连接至该第一基板10的上表面101。 However, in other embodiments, the first die 12 is connected to an upper surface 101 of the first substrate 10 using a flip-chip manner electrically.

[0012] 该第一封胶14包覆该第一管芯12、这些第一导线13及该第一基板10的上表面101。 [0012] The first sealant 14 encapsulates the first die 12, the upper surface 101 of the first conductor 13 and the first substrate 10. 该中间胶层M位于该第一封胶14的上表面,其中该中间胶层M的表面积实质上等于该第一封胶14的上表面的表面积。 M The intermediate adhesive layer located on the surface of the first sealant 14, wherein the surface area of ​​the M intermediate adhesive layer is substantially equal to the first sealing surface area of ​​the upper surface 14 of the glue.

[0013] 该第二基板16,例如一有机基板,具有一上表面161、一下表面162、至少一第二上焊垫163及至少一第二下焊垫164。 [0013] The second substrate 16, for example, an organic substrate having an upper surface 161, a lower surface 162, at least 163 pads and at least one second lower pads 164 on a second. 该第二基板16的下表面162利用该中间胶层M黏附于该第一封胶上14。 The lower surface of the second substrate 16 by the intermediate 162 M adhesive layer adhered to the first sealant 14. 该至少一第二上焊垫163邻接于该第二基板16的上表面161,该至少一第二下焊垫164邻接于该第二基板16的下表面162。 The at least a second pad 163 on the upper surface 161 adjacent to the second substrate 16, the at least a second lower pad 164 adjacent to the second surface 16 of the lower substrate 162.

[0014] 该第二管芯18邻接于该第二基板16的上表面161,且电性连接至该第二基板16 的上表面161。 [0014] The second die 18 adjacent to the upper surface 161 of the second substrate 16, and electrically connected to the upper surface 161 of the second substrate 16. 在本实施例中,该第二管芯18利用一第二胶层181黏附于该第二基板16的上表面161,且利用这些第二导线19电性连接至该第二基板16的上表面161。 In the present embodiment, the second die 18 by means of a second adhesive layer 181 adhered to the upper surface 161 of the second substrate 16, and the use of these second wires 19 is electrically connected to the upper surface of the second substrate 16 161. 然而,在其它实施例中,该第二管芯18利用倒装焊方式电性连接至该第二基板16的上表面161。 However, in other embodiments, the second die 18 using a flip-chip electrically connected to the upper surface 161 of the second substrate 16.

[0015] 该第二封胶20包覆该第二管芯18、这些第二导线19及该第二基板16的上表面161。 [0015] The second encapsulant 20 encapsulates the second die 18, the upper surface 161 of the second lead 19 and the second substrate 16.

[0016] 该至少一导通柱22贯穿该第一基板10、该第一封胶14及该第二基板16。 [0016] The at least one conductive via 22 penetrating the first substrate 10, the first sealant 14 and the second substrate 16. 在本实施例中,该至少一导通柱22的材质为铜,其贯穿该至少一第一上焊垫103、该至少一第一下焊垫104、该至少一第二上焊垫163及该至少一第二下焊垫164,且该至少一导通柱22的二端分别显露于该第一基板10的下表面102及该第二基板16的上表面161。 In the present embodiment, the material of the at least one conductive via 22 is made of copper, through which the at least one first upper pads 103, at the at least one first pad 104, the pad 163 and at least a second the at least one second lower pad 164, and the second end of the at least one guide post 22 are exposed on the lower surface 102 of the first substrate 10 and the upper surface 161 of the second substrate 16.

[0017] 这些焊球沈位于该第一基板10的该至少一第一下焊垫104上,且电性连接至该至少一导通柱22。 [0017] These balls sink located on the at least a first lower pad 104 of the first substrate 10, and electrically connected to the at least one conductive via 22.

[0018] 在本实施例中,该至少一导通柱22用以作为垂直方向电性连接的组件。 [0018] In the present embodiment, the at least one conductive via 22 is used as a component of the vertical direction electrically connected. 由于该至少一导通柱22的外径比已知焊球小,因此可缩小彼此间距且增加密度。 Since the outer diameter of the at least one conductive post 22 is smaller than the known solder balls, thereby reducing the gap to each other and increase the density.

[0019] 参考图2至图10,显示本发明半导体封装结构的制造方法的一实施例的示意图。 [0019] Referring to FIG. 2 to FIG. 10, a schematic diagram illustrating an embodiment of a method of manufacturing a semiconductor package of the present invention. 参考图2,提供一第一基板10。 Referring to FIG. 2, a first substrate 10. 该第一基板10,例如一有机基板,具有一上表面101、一下表面102、至少一第一上焊垫103及至少一第一下焊垫104。 The first substrate 10, for example, an organic substrate having an upper surface 101, a lower surface 102, at least a first upper pad 103 and at least a first pad 104. 该至少一第一上焊垫103邻接于该第一基板10的上表面101,该至少一第一下焊垫104邻接于该第一基板10的下表面102。 On the at least one first abutment pad 103 on the surface 101 of the first substrate 10, the at least one first pad 104 adjacent to the lower surface 102 of the first substrate 10.

[0020] 参考图3,附着一第一管芯12于该第一基板10的上表面101,且电性连接该第一管芯12至该第一基板10的上表面101。 [0020] Referring to FIG 3, a first die 12 attached to the upper surface 101 of the first substrate 10, and electrically connected to the first die 12 to the upper surface 101 of the first substrate 10. 在本实施例中,该第一管芯12利用一第一胶层121 黏附于该第一基板10的上表面101,且利用多条第一导线13电性连接至该第一基板10的上表面101。 In the present embodiment, the first die 12 using a first adhesive layer 121 is adhered to the upper surface 101 of the first substrate 10, and using a plurality of first lead 13 is electrically connected to the first substrate 10 surface 101. 然而,在其它实施例中,该第一管芯12利用倒装焊方式电性连接至该第一基板10的上表面101。 However, in other embodiments, the first die 12 is connected to an upper surface 101 of the first substrate 10 using a flip-chip manner electrically.

[0021] 参考图4,形成一第一封胶14以包覆该第一管芯12、这些第一导线13及该第一基板10的上表面101。 [0021] Referring to FIG 4, a first sealant 14 is formed to cover the first die 12, the upper surface 101 of the first lead 13 and the first substrate 10. [0022] 参考图5,提供一第二基板16。 [0022] Referring to Figure 5, a second substrate 16. 该第二基板16,例如一有机基板,具有一上表面161、一下表面162、至少一第二上焊垫163及至少一第二下焊垫164。 The second substrate 16, for example, an organic substrate having an upper surface 161, a lower surface 162, at least 163 pads and at least one second lower pads 164 on a second. 该第二基板16的下表面162利用一中间胶层M黏附于该第一封胶上14,其中该中间胶层M的表面积实质上等于该第一封胶14的上表面的表面积。 The lower surface of the second substrate 16 using a 162 M intermediate adhesive layer adhered to the first sealant 14, wherein the surface area of ​​the M intermediate adhesive layer is substantially equal to the upper surface of the first sealant 14 surface area. 该至少一第二上焊垫163邻接于该第二基板16的上表面161,该至少一第二下焊垫164邻接于该第二基板16的下表面162。 The at least a second pad 163 on the upper surface 161 adjacent to the second substrate 16, the at least a second lower pad 164 adjacent to the second surface 16 of the lower substrate 162.

[0023] 参考图6,以机械钻孔或激光钻孔方式形成至少一贯穿孔观以贯穿该第一基板10、该第一封胶14、该中间胶层M及该第二基板16。 [0023] Referring to FIG. 6, mechanical drilling or laser drilling at least one hole is formed to penetrate the concept of the first substrate 10, the first sealant 14, the M intermediate adhesive layer 16 and the second substrate. 在本实施例中,该至少一贯穿孔观贯穿该至少一第一上焊垫103、该至少一第一下焊垫104、该至少一第二上焊垫163及该至少一第二下焊垫164。 In the present embodiment, the concept of the at least one hole through at least a first pad 103 on the at least one first pad 104 at the at least one second pad 163 and the at least one second lower pads 164.

[0024] 参考图7,以电镀方式形成一导电金属(例如铜)于该至少一贯穿孔观内以形成至少一导通柱22。 [0024] Referring to Figure 7, is formed by electroplating a conductive metal (e.g. copper) in the through hole to form at least within the concept of the at least one conductive via 22. 该至少一导通柱22贯穿该至少一第一上焊垫103、该第一基板10、该至少一第一下焊垫104、该第一封胶14、该中间胶层24、该至少一第二上焊垫163、该第二基板16及该至少一第二下焊垫164,且该至少一导通柱22的二端分别显露于该第一基板10的下表面102及该第二基板16的上表面161。 The at least one conductive via 22 penetrating the at least one first pad 103 on the first substrate 10, at the at least one first pad 104, the first sealant 14, the intermediate adhesive layer 24, the at least one the second pad 163, the second substrate 16, and the at least a second lower pad 164, and the second end of the at least one guide post 22 are exposed on the lower surface of the first substrate 10 and the second 102 upper surface 161 of substrate 16.

[0025] 参考图8,附着一第二管芯18于该第二基板16的上表面161,且电性连接该第二管芯18至该第二基板16的上表面161。 [0025] Referring to Figure 8, a second die 18 attached to the upper surface 161 of the second substrate 16, and electrically connected to the second die 18 to the upper surface 161 of the second substrate 16. 在本实施例中,该第二管芯18利用一第二胶层181 黏附于该第二基板16的上表面161,且利用多条第二导线19电性连接至该第二基板16的上表面161。 In the present embodiment, the second die 18 by means of a second adhesive layer 181 adhered to the upper surface 161 of the second substrate 16, and using a plurality of second wire 19 is electrically connected to the second substrate 16 surface 161. 然而,在其它实施例中,该第二管芯18利用倒装焊方式电性连接至该第二基板16的上表面161。 However, in other embodiments, the second die 18 using a flip-chip electrically connected to the upper surface 161 of the second substrate 16.

[0026] 参考图9,形成一第二封胶20以包覆该第二管芯18、这些第二导线19及该第二基板16的上表面161。 [0026] Referring to FIG 9, a second sealant 20 is formed to cover the second die 18, the upper surface 161 of the second lead 19 and the second substrate 16. 接着,形成多个焊球沈于该第一基板10的该至少一第一下焊垫104 上,以电性连接至该至少一导通柱22。 Next, a plurality of solder balls on the sink at least a first lower pad 104 of the first substrate 10, to be electrically connected to the at least one conductive via 22.

[0027] 参考图10,进行切割步骤,以切割该第一基板10、该第一封胶14、该中间胶层24、 该第二基板16及该第二封胶20,而制得多个如图1所示的该半导体封装结构1。 [0027] Referring to FIG 10, a cutting step to cut the first substrate 10, the first sealant 14, the intermediate adhesive layer 24, the second substrate 16 and the second sealant 20, a plurality of prepared the semiconductor package as shown in FIG 11.

[0028] 上述实施例仅为说明本发明的原理及其功效,而非用以限制本发明。 [0028] The above-described embodiments are illustrative only of the principles and effect of the present invention, not to limit the present invention. 因此,了解此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。 Thus, to understand this technique of the embodiments described above those modifications and variations still off the spirit of the present invention. 本发明的权利范围应如后述的权利要求范围所列。 Scope of the present invention should be described later as claimed in claim listed range.

Claims (15)

1. 一种半导体封装结构,包括:一第一基板,具有一上表面及一下表面;一第一管芯,邻接于该第一基板的上表面,且电性连接至该第一基板的上表面;一第一封胶,包覆该第一管芯及该第一基板的上表面;一第二基板,具有一上表面及一下表面,该第二基板的下表面黏附于该第一封胶上;及至少一导通柱,贯穿该第一基板、该第一封胶及该第二基板。 A semiconductor package, comprising: a first substrate having an upper surface and a lower surface; a first die, adjacent to the upper surface of the first substrate and electrically connected to the first substrate, surface; a first sealant, covering the first die and the upper surface of the first substrate; a second substrate having an upper surface and a lower surface, the lower surface of the second substrate is adhered to the first seal glue; and at least one conductive via, penetrating the first substrate, the first sealant and the second substrate.
2.如权利要求1所述的半导体封装结构,其特征在于,该第一基板还具有至少一第一上焊垫及至少一第一下焊垫,该至少一第一上焊垫邻接于该第一基板的上表面,该至少一第一下焊垫邻接于该第一基板的下表面,且该至少一导通柱贯穿该至少一第一上焊垫及该至少一第一下焊垫。 2. The semiconductor package according to claim 1, wherein the first substrate further having at least one first and at least one pad on the first pad, the at least one first pad adjacent to the upper the upper surface of the first substrate, the at least one first pad adjacent to the lower surface of the first substrate and the at least one conductive via through the at least one first pad on the first and the at least one lower pad .
3.如权利要求1所述的半导体封装结构,其特征在于,还包括一中间胶层,该第二基板的下表面利用该中间胶层黏附于该第一封胶上,且该至少一导通柱贯穿该中间胶层。 3. The semiconductor package according to claim 1, characterized by further comprising an intermediate adhesive layer, the lower surface of the second substrate by the intermediate adhesive layer adhered to the first sealant, and the at least one guide pillars through the intermediate adhesive layer.
4.如权利要求1所述的半导体封装结构,其特征在于,该第二基板还具有至少一第二上焊垫及至少一第二下焊垫,该至少一第二上焊垫邻接于该第二基板的上表面,该至少一第二下焊垫邻接于该第二基板的下表面,且该至少一导通柱贯穿该至少一第二上焊垫及该至少一第二下焊垫。 4. The semiconductor package according to claim 1, wherein the second substrate further having at least on a second pad and at least one second lower pad, the pad adjacent to the at least one second upper surface of the second substrate, the at least a second pad adjacent to the lower surface of the second substrate and the at least one conductive via through the at least one second bonding pad and the lower pad at least a second .
5.如权利要求1所述的半导体封装结构,其特征在于,该至少一导通柱的二端分别显露于该第一基板的下表面及该第二基板的上表面。 5. The semiconductor package according to claim 1, wherein the at least two ends of a conducting posts are exposed on the lower surface of the first substrate and the second substrate.
6.如权利要求1所述的半导体封装结构,其特征在于,还包括一第二管芯,邻接于该第二基板的上表面,且电性连接至该第二基板的上表面。 The semiconductor package as claimed in claim 1, characterized by further comprising a second die adjacent to the upper surface of the second substrate and electrically connected to the upper surface of the second substrate.
7.如权利要求6所述的半导体封装结构,其特征在于,还包括一第二封胶,其包覆该第二管芯及该第二基板的上表面。 7. The semiconductor package as claimed in claim 6 which covers the upper surface of the second die and the second substrate, characterized in that, further comprising a second sealant.
8. 一种半导体封装结构的制造方法,包括以下步骤:(a)提供一第一基板,该第一基板具有一上表面及一下表面;(b)附着一第一管芯于该第一基板的上表面,且电性连接该第一管芯至该第一基板的上表面;(c)形成一第一封胶以包覆该第一管芯及该第一基板的上表面;(d)提供一第二基板,该第二基板具有一上表面及一下表面,且黏附该第二基板的下表面于该第一封胶上;(e)形成至少一贯穿孔以贯穿该第一基板、该第一封胶及该第二基板;及(f)形成一导电金属于该至少一贯穿孔内以形成至少一导通柱。 A method for manufacturing a semiconductor package, comprising the steps of: (a) providing a first substrate, the first substrate having an upper surface and a lower surface; (b) attaching a first die to the first substrate the upper surface and the upper surface of the first die to the first substrate and electrically connected; (c) forming a first sealant to cover the upper surface of the first die and the first substrate; (D ) providing a second substrate, the second substrate having an upper surface and a lower surface, and the adhesion of the lower surface of the second substrate on the first sealant; the first substrate through at least one hole (e) forming, the first sealant and the second substrate; and (f) forming a conductive metal within the at least one through hole to form at least one conductive via.
9.如权利要求8所述的制造方法,其特征在于,该步骤(a)中,该第一基板还具有至少一第一上焊垫及至少一第一下焊垫,该至少一第一上焊垫邻接于该第一基板的上表面,该至少一第一下焊垫邻接于该第一基板的下表面,且该步骤(e)中,该至少一贯穿孔贯穿该至少一第一上焊垫及该至少一第一下焊垫。 9. The manufacturing method according to claim 8, wherein the step (a), the first substrate further having at least one first and at least one pad on the first pad, the at least one first the pad adjacent to the upper surface of the first substrate, the at least one first pad adjacent to the lower surface of the first substrate, and the step (e), the at least one hole through at least a first upper pad and the at least a first lower pad.
10.如权利要求8所述的制造方法,其特征在于,该步骤(d)中,该第二基板的下表面利用一中间胶层黏附于该第一封胶上;该步骤(e)中,该至少一贯穿孔贯穿该中间胶层;且该步骤(f)中,该至少一导通柱贯穿该中间胶层。 10. The manufacturing method according to claim 8, wherein the step (d), the lower surface of the second substrate using an intermediate adhesive layer adhered to the first sealant; the step (e), the at least one through hole penetrating the intermediate adhesive layer; and the step (f), the at least one conductive via through the intermediate adhesive layer.
11.如权利要求8所述的制造方法,其特征在于,该步骤(d)中,该第二基板还具有至少一第二上焊垫及至少一第二下焊垫,该至少一第二上焊垫邻接于该第二基板的上表面,该至少一第二下焊垫邻接于该第二基板的下表面,且该步骤(e)中,该至少一贯穿孔贯穿该至少一第二上焊垫及该至少一第二下焊垫。 11. The manufacturing method according to claim 8, wherein the step (d), the second substrate further having at least on a second pad and at least one second lower pads, the at least one second the pad adjacent to the upper surface of the second substrate, the at least one second pad adjacent to the lower surface of the second substrate, and the step (e), the at least one hole through at least one second upper the at least one pad and the second pad.
12.如权利要求8所述的制造方法,其特征在于,该步骤(f)中,该至少一导通柱的二端分别显露于该第一基板的下表面及该第二基板的上表面。 12. The method according to claim 8, wherein the step (f), the two ends of the at least one conductive via are exposed on the lower surface of the first substrate and the second substrate, .
13.如权利要求8所述的制造方法,其特征在于,还包括一附着一第二管芯于该第二基板的上表面,且电性连接该第二管芯至该第二基板的上表面的步骤。 13. The manufacturing method according to claim 8, wherein the upper surface further comprises a second attaching a die to the second substrate and electrically connected to the second die to said second substrate step surface.
14.如权利要求13所述的制造方法,其特征在于,还包括一形成一第二封胶以包覆该第二管芯及该第二基板的上表面的步骤。 14. The manufacturing method according to claim 13, characterized in that, further comprising a sealant forming a second coating step to the second die and the upper surface of the second substrate.
15.如权利要求14所述的制造方法,其特征在于,还包括一切割该第一基板、该第一封胶、该第二基板及该第二封胶的步骤。 The manufacturing method according to claim 14, wherein the first substrate further comprises a cutting, the first sealant, the second step of the second substrate and the glue seal.
CN2012100763456A 2012-03-21 2012-03-21 Semiconductor package structure and manufacturing method thereof CN102569274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012100763456A CN102569274A (en) 2012-03-21 2012-03-21 Semiconductor package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012100763456A CN102569274A (en) 2012-03-21 2012-03-21 Semiconductor package structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN102569274A true CN102569274A (en) 2012-07-11

Family

ID=46414305

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012100763456A CN102569274A (en) 2012-03-21 2012-03-21 Semiconductor package structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN102569274A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040056277A1 (en) * 2002-09-17 2004-03-25 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
CN1933147A (en) * 2005-09-15 2007-03-21 南茂科技股份有限公司 Chip packaging body and stack chip packaging structure
CN101047167A (en) * 2006-03-29 2007-10-03 海力士半导体有限公司 Semiconductor package stack with through-via connection
CN101110409A (en) * 2006-07-21 2008-01-23 日月光半导体制造股份有限公司 System packaging package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040056277A1 (en) * 2002-09-17 2004-03-25 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
CN1933147A (en) * 2005-09-15 2007-03-21 南茂科技股份有限公司 Chip packaging body and stack chip packaging structure
CN101047167A (en) * 2006-03-29 2007-10-03 海力士半导体有限公司 Semiconductor package stack with through-via connection
CN101110409A (en) * 2006-07-21 2008-01-23 日月光半导体制造股份有限公司 System packaging package

Similar Documents

Publication Publication Date Title
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
CN101506975B (en) Stack die packages
JP4503039B2 (en) Circuit device
JP5032623B2 (en) A semiconductor memory device
JP2008171938A (en) Semiconductor device and its manufacturing method
JP2009124151A (en) Laminated semiconductor package with improved bonding reliability
US20130026657A1 (en) Semiconductor package and method of fabricating the same
CN100479135C (en) Semiconductor device and a method for manufacturing of the same
JP2006190771A (en) Semiconductor device
US7928551B2 (en) Semiconductor device and method of manufacturing the same
CN102299082B (en) Producing method of semiconductor bearing element and producing method of package using the semiconductor bearing element
JP2009295959A (en) Semiconductor device, and method for manufacturing thereof
CN101060087A (en) Electrode, manufacturing method of the same, and semiconductor device having the same
CN103730448A (en) Package substrate and method of fabricating the same
US7002251B2 (en) Semiconductor device
JP2007088453A (en) Method of manufacturing stack die package
CN102044520A (en) Package carrier plate, package structure and manufacturing process of package carrier plate
KR100817076B1 (en) Partially insulating coated metal wire for wire bonding and wire bonding method of semiconductor package using the same
JP2011155203A (en) Semiconductor device
CN103681365B (en) Laminated package structure and fabrication method
US9425152B2 (en) Method for fabricating EMI shielding package structure
TW200947654A (en) Stacked type chip package structure and method of fabricating the same
CN102044600A (en) Light-emitting diode (LED) encapsulating structure and preparation method thereof
US8884429B2 (en) Package structure having embedded electronic component and fabrication method thereof
US8999759B2 (en) Method for fabricating packaging structure having embedded semiconductor element

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)