CN114361045A - Deep hole processing method based on semiconductor packaging - Google Patents
Deep hole processing method based on semiconductor packaging Download PDFInfo
- Publication number
- CN114361045A CN114361045A CN202210254633.XA CN202210254633A CN114361045A CN 114361045 A CN114361045 A CN 114361045A CN 202210254633 A CN202210254633 A CN 202210254633A CN 114361045 A CN114361045 A CN 114361045A
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- Prior art keywords
- deep hole
- conductive block
- substrate
- hole processing
- processing method
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000009713 electroplating Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000012858 packaging process Methods 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000003754 machining Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 7
- 238000012360 testing method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- -1 gold tin copper aluminum Chemical compound 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention provides a deep hole processing method based on semiconductor packaging, which is characterized in that when all plastic packaged components are mounted on a substrate, a conductive block is simultaneously mounted on the substrate, the conductive block and the components are positioned on the same side of the substrate, then each component and the conductive block which need to be subjected to plastic packaging are subjected to plastic packaging to form a plastic packaging body, and deep hole processing is carried out at the position, positioned on the conductive block, of the plastic packaging body in the deep hole processing in the later period to form a deep hole until the conductive block is exposed, so that the depth of the deep hole can be shortened, and particularly in the plastic packaging body with a thicker thickness.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a deep hole processing method based on semiconductor packaging.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures such as inspection, Test, packaging and the like, and finally warehousing and shipping.
In the prior art, during semiconductor packaging, each component is attached to a substrate, then plastic packaging is performed, in order to connect a redistribution layer connected with the component with an external pin outside a plastic packaging body, generally, holes need to be formed in the plastic packaging body, then electroplating is performed in the holes, so that the redistribution layer which is not on the same side of the plastic packaging body is connected with the external pin, but if the thickness of the plastic packaging body is thick, electroplating is performed in the holes, incomplete electroplating is easily caused, or an electroplated metal side wall cannot be formed, poor contact is caused, and the defective rate of chips is greatly increased.
Disclosure of Invention
The invention provides a deep hole processing method based on semiconductor packaging, which can solve the problems.
The technical scheme adopted by the invention is as follows:
the deep hole processing method based on semiconductor packaging comprises the steps of providing a substrate, mounting each component to be subjected to plastic packaging on the substrate, and mounting a conductive block on the substrate, wherein the conductive block and the component are positioned on the same side of the substrate;
plastically packaging each component and the conductive block which need to be plastically packaged to form a plastic package body;
deep hole machining is carried out on the position, located on the conductive block, of the plastic package body, and deep holes are formed until the conductive block is exposed;
electroplating in the deep hole to form a conductive layer with electrical connection;
and carrying out a subsequent conventional semiconductor packaging process.
Further, the conductive block is a passive metal block.
Further, the conductive block is conductive resin.
Further, deep hole processing is carried out on the position, located on the plastic package body, of the conductive block in a laser drilling or etching mode.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, when all the components which are subjected to plastic packaging are mounted on the substrate, the conductive blocks are simultaneously mounted on the substrate, the conductive blocks and the components are positioned at the same side of the substrate, then each component and the conductive block which are required to be subjected to plastic packaging are subjected to plastic packaging to form a plastic packaging body, and deep hole processing is carried out at the position, positioned on the conductive block, of the plastic packaging body in the later deep hole processing to form a deep hole until the conductive block is exposed, so that the depth of the deep hole can be shortened, especially in the plastic packaging body with thicker thickness.
Drawings
Fig. 1 is a schematic diagram of a deep hole structure in the deep hole processing method based on semiconductor packaging provided by the invention.
Detailed Description
The present invention will now be described in connection with particular embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functionality throughout.
The directional phrases used in this disclosure include, for example: upper, lower, left, right, front, rear, inner, outer, front, rear, side, etc. are directions with reference to the drawings only, and the embodiments described below by referring to the drawings and directional terms used are exemplary only for explaining the present invention, and are not to be construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials that one of ordinary skill in the art would recognize for other processes and/or uses of other materials.
Referring to fig. 1, fig. 1 is a schematic view of a deep hole structure in a deep hole processing method based on semiconductor package according to the present invention.
A deep hole processing method based on semiconductor packaging is provided, a substrate 10 is provided, each component 20 needing plastic packaging is mounted on the substrate 10, a conductive block 30 is mounted on the substrate 10, and the conductive block 30 and the component 20 are both positioned on the same side of the substrate 10; plastically packaging each component 20 and the conductive block 30 which need to be plastically packaged to form a plastic package body 40; deep hole machining is carried out on the position, located on the conductive block 30, of the plastic package body 40, and a deep hole 50 is formed until the conductive block 30 is exposed; electroplating in the deep hole 50 to form a conductive layer with electrical connection; and carrying out a subsequent conventional semiconductor packaging process. The conductive block 30 is a passive metal block or conductive resin, and is cheap, easy to obtain and low in cost. Deep hole processing is carried out on the position, located on the conductive block 30, of the plastic package body 40 in a laser drilling or etching mode, the process flow is convenient, and the production efficiency is improved.
According to the invention, when all the components which are subjected to plastic packaging are mounted on the substrate 10, the conductive block 30 is mounted on the substrate 10 at the same time, the conductive block 30 and the components are positioned at the same side of the substrate 10, then all the components which are required to be subjected to plastic packaging and the conductive block 30 are subjected to plastic packaging to form the plastic packaging body 40, and deep hole processing is carried out at the position, which is positioned on the conductive block 30, of the plastic packaging body 40 in the later deep hole processing to form a deep hole until the conductive block 30 is exposed, so that the depth of the deep hole can be shortened, especially in the plastic packaging body 40 with a thicker thickness.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (4)
1. The deep hole processing method based on semiconductor packaging is characterized by comprising the steps of providing a substrate (10), mounting each component (20) needing plastic packaging on the substrate (10), mounting a conductive block (30) on the substrate (10), wherein the conductive block (30) and the component (20) are positioned on the same side of the substrate (10);
plastically packaging each component (20) and the conductive block (30) which need to be plastically packaged to form a plastic packaging body (40);
deep hole machining is carried out on the position, located on the conductive block (30), of the plastic package body (40) to form a deep hole (50) until the conductive block (30) is exposed;
electroplating in the deep hole (50) to form a conductive layer with electrical connection;
and carrying out a subsequent conventional semiconductor packaging process.
2. The semiconductor package based deep hole processing method according to claim 1, wherein the conductive block (30) is a passive metal block.
3. The semiconductor package based deep hole processing method according to claim 1, wherein the conductive block (30) is a conductive resin.
4. The semiconductor package based deep hole processing method according to claim 1, wherein deep hole processing is performed by laser drilling or etching at a position of the conductive block (30) on the plastic package body (40).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210254633.XA CN114361045A (en) | 2022-03-16 | 2022-03-16 | Deep hole processing method based on semiconductor packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210254633.XA CN114361045A (en) | 2022-03-16 | 2022-03-16 | Deep hole processing method based on semiconductor packaging |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114361045A true CN114361045A (en) | 2022-04-15 |
Family
ID=81095107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210254633.XA Pending CN114361045A (en) | 2022-03-16 | 2022-03-16 | Deep hole processing method based on semiconductor packaging |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114361045A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120326170A1 (en) * | 2011-06-22 | 2012-12-27 | Yong Liu | Wafer level molded opto-couplers |
| CN110473795A (en) * | 2019-09-02 | 2019-11-19 | 合肥矽迈微电子科技有限公司 | A kind of the layering insulation package structure and technique of large size chip |
| CN110556343A (en) * | 2019-10-11 | 2019-12-10 | 合肥矽迈微电子科技有限公司 | Packaging structure and packaging process for preventing layering |
| CN111211096A (en) * | 2020-01-10 | 2020-05-29 | 珠海格力电器股份有限公司 | Chip module packaging structure and packaging method |
| CN113725094A (en) * | 2021-11-01 | 2021-11-30 | 深圳中科四合科技有限公司 | Multi-chip hybrid packaging method and multi-chip hybrid packaging structure |
-
2022
- 2022-03-16 CN CN202210254633.XA patent/CN114361045A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120326170A1 (en) * | 2011-06-22 | 2012-12-27 | Yong Liu | Wafer level molded opto-couplers |
| CN110473795A (en) * | 2019-09-02 | 2019-11-19 | 合肥矽迈微电子科技有限公司 | A kind of the layering insulation package structure and technique of large size chip |
| CN110556343A (en) * | 2019-10-11 | 2019-12-10 | 合肥矽迈微电子科技有限公司 | Packaging structure and packaging process for preventing layering |
| CN111211096A (en) * | 2020-01-10 | 2020-05-29 | 珠海格力电器股份有限公司 | Chip module packaging structure and packaging method |
| CN113725094A (en) * | 2021-11-01 | 2021-11-30 | 深圳中科四合科技有限公司 | Multi-chip hybrid packaging method and multi-chip hybrid packaging structure |
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| PB01 | Publication | ||
| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220415 |
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| RJ01 | Rejection of invention patent application after publication |