CN102468260B - Lead frame with compatible high voltage and low voltage, lead frame array and packaging structure thereof - Google Patents
Lead frame with compatible high voltage and low voltage, lead frame array and packaging structure thereof Download PDFInfo
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- CN102468260B CN102468260B CN201010548604.1A CN201010548604A CN102468260B CN 102468260 B CN102468260 B CN 102468260B CN 201010548604 A CN201010548604 A CN 201010548604A CN 102468260 B CN102468260 B CN 102468260B
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- 238000004806 packaging method and process Methods 0.000 title abstract description 9
- 238000005538 encapsulation Methods 0.000 claims description 49
- 238000013461 design Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 8
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- 238000012856 packing Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 206010057855 Hypotelorism of orbit Diseases 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a lead frame with compatible high voltage and low voltage, a lead frame array and a packaging structure of the lead frame array and belongs to the technical field of chip packaging. The lead frame comprises pins, wherein the pins comprise a first pin and a second pin which are adjacently arranged; the first pin is used for outputting/inputting first voltage; and the second pin is used for outputting/inputting second voltage. The distance between the first pin and the second pin is set so that the second pin is prevented from being affected by the crosstalk of a voltage output signal of the first pin, wherein the first voltage is between 100V to 800V; and the second voltage is less than or equal to 50V. Under the condition that the area of the lead frame is not increased, the second pin can be prevented from being affected by the crosstalk of the high voltage signal of the first pin, so the output/input of the high voltage and the output/input of the low voltage are compatible at the same time, and the lead frame is suitable for packaging a chip with high power in a mode of low cost.
Description
Technical field
The invention belongs to chip encapsulation technology field, be specifically related to a kind of lead frame, relate in particular to a kind of can be compatible high low-voltage lead frame, array of leadframes and encapsulating structure thereof of input/output simultaneously.
Background technology
In recent decades, chip encapsulation technology is being followed the development of IC (integrated circuit) always, and generation IC just has corresponding generation encapsulation technology to match.Packing forms generically refers to installs the shell that semiconductor integrated circuit chip is used; it not only plays a part to install, fixes, seals, protects chip and strengthens the aspects such as electric heating property; but also by the contact on chip, be wired on the pin of package casing, in these, pin is connected with other devices by the wire on printed circuit board (PCB) again.Therefore, the lead frame of the effects such as packing forms generally comprises for installing, fixing and lead-in wire, also comprise simultaneously for the protection of the effects such as chip, sealing, and the packaging body (Package Body) that matches of lead frame.
Along with the development of encapsulation technology, chip area is with the ratio of package area more and more close to 1, and applicable frequency is more and more higher, and heat resistance is become better and better, and weight is lighter, and reliability is higher; Pin number also increases simultaneously, and the spacing between pin is also more and more less.
Wherein, SOIC (Small Outline Integrated Circuit, small outline integrated circuit) encapsulation is essentially identical packing forms with SOP (Small Outline Package, little outline packages).It is widely used in the encapsulation of various chips.Figure 1 shows that the encapsulating structure schematic diagram of the SOIC packing forms of prior art.As shown in Figure 1, this encapsulating structure comprises the lead frame of SOIC encapsulation, packed a certain chip and packaging body 11.The lead frame of SOIC encapsulation comprises the interior pin and the outer pin that with inner island, with the chip on island, are electrically connected.In the embodiment shown in fig. 1, the lead frame of this SOIC encapsulation is the lead frame of 8 pins, wherein shows 8 outer pins, and 131,133 is two outer pins wherein.Normally, according to the relevant criterion of SOIC encapsulation, the center distance between outer pin 131,133 is 0.127 millimeter, is also the D1=0.127 millimeter shown in Fig. 1.
, notice meanwhile, when the chip of packaged high-power, the power drives chip that such as Switching Power Supply is used etc.The voltage of its some end output (or input) is relatively high, and for example its operating voltage can be up to 380 volts.When the lead frame that adopts SOIC to encapsulate encapsulates the high-power chip that comprises the type, there is a certain pin output (or input) high voltage (for example 350V) and the situation of another adjacent leads output (or input) low-voltage (for example 5V).Take the encapsulating structure of SOIC shown in Fig. 1 as example, if pin 131 is for exporting (or input) high voltage, pin 133 for output (or input) low-voltage.This is can be because the high voltage signal that the mutual spacing between pin 131 and pin 133 too closely causes pin 131 to export (or input) produces and crosstalks pin 133, for example, when the dust stratification forming in long-time use, or in wet environment, between pin 131 and pin 133, can leak electricity because height voltage difference adds hypotelorism, thereby high pressure can be crosstalked into low pressure pin.Above crosstalk phenomenon easily causes the phenomenons such as the punch through damage of chip.
For avoiding this phenomenon to occur, can adopt the relative larger lead frame of spacing between pin to encapsulate, for example, by originally adopting SOIC encapsulation to change into, adopt the larger DIP form of pin-pitch to encapsulate.The shortcoming of this method is: (1) likely DIP form encapsulates and be not suitable for the encapsulation of this kind of high-power chip; (2) the relatively large general volume of encapsulating structure of spacing is larger, for example, with material (spun gold) more, and therefore cost is higher; (3) sometimes due to output (or input) overtension, even if adopt other relatively large packing forms of pin-pitch can not avoid because high-voltage signal causes the problem of crosstalking.
In view of this, be necessary to propose the compatible high low-voltage of a kind of novel energy lead frame of input/output simultaneously.
Summary of the invention
The technical problem to be solved in the present invention is to avoid the high voltage signal inputing or outputing due to high voltage pin that adjacent low-voltage pin is caused and crosstalked.
For solving above technical problem, according to one aspect of the present invention, a kind of lead frame is provided, comprise pin, described pin comprises the first pin and second pin of adjacent setting, described the first pin is for input/output the first voltage, and described the second pin is for input/output second voltage, spacing between described the first pin and described the second pin is set so that described the second pin is avoided the crosstalking of Voltage-output signal of described the first pin;
Wherein, described the first voltage refers to the voltage between 100 volts to 800 volts, and described second voltage refers to the voltage that is less than or equal to 50 volts.
According to the better embodiment of lead frame provided by the invention, described lead frame is improved and is designed by the low-voltage lead frame to for input/output second voltage, by removing a pin of described low-voltage lead frame, two pins adjacent with the pin of this removal are defined as respectively described the first pin and described the second pin.
Preferably, the pin of described lead frame also comprises multiple the 3rd pins for input/output second voltage, spacing between described the first pin and described the second pin is the twice of the spacing between described the second pin and described the 3rd pin, or is the twice of spacing between adjacent described the 3rd pin.
According to lead frame provided by the present invention, wherein, spacing centered by described spacing.
According to the better embodiment of lead frame provided by the invention, the second pin is directly connected with same island with the form that merges output with the 3rd pin described in one of them simultaneously.
According to the better embodiment of lead frame provided by the invention, described lead frame comprises the first island and the second island, and described the first island is used for placing the high-tension chip of input/output, and described the second island is for placing the chip of input/output low-voltage.
Preferably, the first pin is directly connected with described the first island.
Preferably, the spacing range between described the first island and described the second island is greater than or equal to 0.25 millimeter.
Preferably, described the first pin is arranged on the end of place pin arrangements.
According to lead frame provided by the present invention, wherein, described pin is interior pin and/or outer pin.
According to lead frame provided by the present invention, wherein, described lead frame can be for small outline integrated circuit is encapsulation, the lead frame in line encapsulation of biserial, little outline packages or thin little outline packages.
According to another aspect of the present invention, a kind of array of leadframes is provided, its comprise multiple by row and column arrange the above and any lead frame.
According to of the present invention, provide a kind of encapsulating structure more on the one hand, it comprise the above and any lead frame.
Technique effect of the present invention is, by the spacing between high-tension the first pin of input/output and the second pin of input/output low-voltage is set, in the case of not increasing the area of lead frame, can make the second pin avoid crosstalking from the high voltage signal of the first pin, thereby compatible high low-voltage input/output simultaneously, is applicable to the high-power chip of low-cost package.
Accompanying drawing explanation
Fig. 1 is the encapsulating structure schematic diagram of the SOIC packing forms of prior art;
Fig. 2 is the structural representation of the lead frame of the SOIC encapsulation that provides according to the first embodiment of the present invention;
Fig. 3 is the later structural representation of lead frame gold wire bonding chip of the encapsulation of SOIC shown in Fig. 2;
Fig. 4 is according to the encapsulating structure schematic diagram of the lead frame of the SOIC encapsulation shown in the Fig. 2 of comprising of the present invention
Fig. 5 arranges according to the lead frame of the SOIC encapsulation shown in Fig. 2 the array of leadframes schematic diagram forming
Fig. 6 is the structural representation of the DIP lead frame that provides according to the second embodiment of the present invention;
Structural representation when Fig. 7 is the outer pin of the lead frame strip of DIP shown in Fig. 6;
Fig. 8 arranges according to the DIP lead frame shown in Fig. 7 the array of leadframes schematic diagram forming.
Embodiment
The present invention is now more fully described with reference to the accompanying drawings, shown in the drawings of exemplary embodiment of the present invention.But the present invention can realize according to a lot of different forms, and should not be understood to be limited to the embodiment of these elaborations.On the contrary, provide these embodiment to make the disclosure become thorough and complete, and design of the present invention is passed to those skilled in the art completely.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region.In the accompanying drawings, identical label refers to identical element or parts, therefore will omit description of them.
In this application, high voltage refers to the voltage between 100 volts to 800 volts, and low-voltage refers to the voltage that is less than or equal to 50 volts.
The structural representation of the lead frame of the SOIC encapsulation providing according to the first embodiment of the present invention is provided.In embodiment illustrated in fig. 2, the outer pin of the lead frame 20 of not shown SOIC encapsulation.As shown in Figure 2, the lead frame 20 of SOIC encapsulation comprises island 231 and 233 and the interior pin 251,2531,2532,2533,2534,2535,2536 that distributes with island around.Wherein interior pin 251 is for the high-tension interior pin of input/output (being called for short " high-pressure internal guiding pin "), and interior pin 2531,2532,2533,2534,2535,2536 is the interior pin (being called for short " pin in low pressure ") for input/output low-voltage.In this embodiment, be provided with two islands 231,233 on lead frame 20, therefore it can be used for encapsulating two chips simultaneously, particularly, places the high-tension chip of input/output on island 231, places the chip of input/output low-voltage on island 233.It will be appreciated by those skilled in the art that, the island of greater number can also be set on lead frame, it is specifically determined by packaged number of chips, for example, can comprise three islands, on one of them island, place the high-tension chip of input/output, on two other island, place the chip of input/output low-voltage; Certainly the quantity of island also can be 1, and the chip of placing on this island had both comprised high-tension input/output end, also comprised the input/output end of low-voltage.Therefore, the concrete quantity of island is not to be subject to embodiment of the present invention restriction.Normally, the lead frame 20 of this embodiment is mainly used in encapsulating two dissimilar chips, I/O in the time of with compatible high voltage and low-voltage.In addition, in this embodiment, island 231 and island 233 separate independent design according to high-low pressure, also corresponding increase of its spacing D3 (as shown in Figure 2), the size of D3 is not less than (being more than or equal to) 0.25 millimeter, for example D3 can be 0.335 millimeter, thereby can effectively realize the high-low pressure isolation between island.
Continue to refer to Fig. 2, in this embodiment, this lead frame 20 is that traditional SOIC8 lead frame is improved and designed, and therefore designs, processes relatively simple.Traditional SOIC8 lead frame is for I/O low-voltage, and wherein, 8 interior pins divide two rows evenly distributed, by removing pin in one of them, can increase the wherein adjacent spacing of two interior pins.In this embodiment, for the high-tension interior pin 251 of input/output and for the interior pin originally arranging between the interior pin 2531 of input/output low-voltage, be removed, thereby make the centre-to-centre spacing D2 (as shown in Figure 2) between interior pin 251 and interior pin 2531 become original twice (for example D2 is the twice of the D1 in Fig. 1, is also 0.254 millimeter). Pin 2532,2533,2534,2535 and 2536 is owing to being for input/output low-voltage equally in other, therefore itself and traditional design are basic identical, also in pin 2532,2533,2534,2535 and 2536 center distance be each other generally 0.127 millimeter.Further, in this embodiment, island 231 with for the high-tension interior pin 251 of input/output, be directly connected, the port of chip arranging on island 231 also can be connected to interior pin 251 with gold wire bonding, thereby realizes high-tension input/output encapsulation.Therefore, for example, during low-voltage that high voltage, interior pin 2531 input/output that interior pin 251 input/output is 200 volts are 5 volts, because the center distance between two pins widens (edge spacing is corresponding widening also), form after plastic-sealed body its plastic-sealed body isolation effect also better, thereby can effectively avoid on interior pin 251 the internal pin 2531 of voltage signal to cause, crosstalk.In the case of the interior pin 2531 adjacent with interior pin 251 avoided crosstalking, other also must avoid crosstalking from farther interior pin with interior pin 251.
It should be noted that, in above embodiment, be by traditional SOI C8 lead frame being removed to a pin between interior pin 251 and interior pin 2531, increasing the distance between interior pin, thereby avoid between interior pin due to crosstalking that high-voltage signal causes another pin.But this is not restrictive.Those skilled in the art can be under the instruction of above embodiment, traditional SIOC8 lead frame is removed to pin in two or more to increase the spacing between pin in high-pressure internal guiding pin and low pressure, for example, in the situation that pin number allows, can also remove interior pin 2531, thereby increase the spacing between pin 2532 in high-pressure internal guiding pin 251 and low pressure; In addition, can also directly design the spacing increasing between high-pressure internal guiding pin and the interior pin of low pressure avoids crosstalking, for example design in high-pressure internal guiding pin and low pressure the spacing range between pin for being not less than 0.25 millimeter, spacing relative decrease between pin in other low pressure simultaneously, thus can guarantee that the lead frame area entirety of SOIC encapsulation does not increase.
Also it should be noted that, in above embodiment, only schematically illustrate the situation that only comprises a high-pressure internal guiding pin, due in actual applications, High voltage output/the input of chip is relatively less, and a high-pressure internal guiding pin can be connected with multiple High voltage outputs/input while gold wire bonding of chip simultaneously, and therefore, next high-pressure internal guiding pin of ordinary circumstance can meet the package requirements of high pressure chip.But, in specific (special) requirements situation, for example, in much more relatively situations of the High voltage output/input of chip, also can increase the quantity of the high-pressure internal guiding pin of lead frame, be for example set to 2.Preferably, each high-pressure internal guiding pin is arranged on the end of interior pin arrangements, example as shown in Figure 2, the left-end point of pin arrangements in interior pin 251 rows of being arranged on (in this embodiment mesohigh, pin is 1), like this, only have one (for example, in pin 2531) with the adjacent interior pin of high-pressure internal guiding pin 251, only need to increase the spacing between the interior pin of a low pressure and high-pressure internal guiding pin, be conducive to the area of maximum possible saving chip.
Further, in this embodiment, in low pressure, pin 2531 and 2532 is to be directly connected between island 233, and therefore, interior pin 2531 and 2532 is to merge output, thereby can allow the larger electric current of interior pin 2531 output relative to 2532.
The lead frame 20 of this SOIC encapsulation also comprises the outer pin corresponding with pin in each (not shown in Fig. 2), in the encapsulating structure shown in Fig. 4, shows outer pin, hereinafter will be explained.
Figure 3 shows that the later structural representation of lead frame gold wire bonding chip of the encapsulation of SOIC shown in Fig. 2.In this embodiment, the packaged chip of lead frame of SOIC encapsulation is exemplary.Dotted line is depicted as the spun gold that bonding connects, and its concrete connected mode is exemplary.The back side of packaged chip also can directly be connected with island, thereby realizes from interior pin 251,2531 or 2533 input/outputs.In this embodiment, the chip of placing on island 231 has high voltage input/output end, and this high voltage input/output end is directly connected with high-pressure internal guiding pin 251 gold wire bondings.Because the spacing between pin 2531 in high-pressure internal guiding pin 251 and low pressure is enough large, can compatible encapsulation high pressure chip and low pressure chip encapsulate simultaneously, and in low pressure, pin is avoided the crosstalking of voltage signal of high-pressure internal guiding pin 251.
Figure 4 shows that according to the encapsulating structure schematic diagram of the lead frame of the SOIC encapsulation shown in the Fig. 2 of comprising of the present invention.In the structure shown in Fig. 3, form after packaging body 21, can form the encapsulating structure shown in Fig. 4.Usually, packaging body 21 forms by plastic packaging.Wherein can find out, the lead frame 20 of the SOIC encapsulation shown in Fig. 2 can also comprise outer pin 271, 2731, 2732, 2733, 2734, 2735, 2736, outer pin 271, 2731, 2732, 2733, 2734, 2735, 2736 are connected respectively in interior pin 251, 2531, 2532, 2533, 2534, 2535, 2536 form with the lead frame shown in Fig. 2, therefore, the 271st, for the high-tension outer pin of input/output (referred to as " the outer pin of high pressure "), 2731, 2732, 2733, 2734, 2735 and 2736 is the outer pins (referred to as " the outer pin of low pressure ") for input/output low-voltage.In this embodiment, similarly, by remove pin outside between outer pin 271 and outer pin 2731 in the lead frame of traditional SOIC8, outer pin 271 and 2731 between center distance by original D 1 (as shown in Figure 1), be increased to the D2 shown in Fig. 2, particularly, D2 becomes the twice (for example becoming 0.254 millimeter from 0.127 millimeter) of D1.In the design of lead-in wire circle, outer pin is aimed at design successively corresponding to interior pin arrangements, therefore, such as the design of the above-described spacing about interior pin, can analogize in the design that is applied to outer pin.Due to widening of the spacing between the outer pin 271 of high pressure and the adjacent outer pin 2731 of low pressure, can avoid outer pin 2731 to avoid crosstalking from the high-voltage signal of the outer pin 271 of outer pin.
Figure 5 shows that according to the lead frame of the SOIC encapsulation shown in Fig. 2 and arrange the array of leadframes schematic diagram forming.Due in actual package process, be to the encapsulation formation simultaneously side by side of multiple chips.Therefore, before encapsulation, the lead frame of SIOC encapsulation is not unit independently, but the form that the lead frame 20 of the SIOC encapsulation shown in multiple Fig. 2 is arranged by multiple lines and multiple rows forms the array of leadframes of SIOC encapsulation, is conducive to like this efficient encapsulation.In this is embodiment illustrated in fig. 5, schematically provide the lead frame 20 that 5 row 4 are listed as and arranged the array of leadframes 30 forming, but this is not restrictive, the concrete quantity of array of leadframes, spread pattern are not limited by the embodiment of the present invention, for example, can also be that 32 lead frames, 20 arrangements that 8 row 4 are listed as form.
The lead frame of above-described SOIC encapsulation, for avoid high pressure pin to the crosstalking of adjacent low pressure pin, in the case of the area of lead frame does not increase, can realize compatible high low-voltage input/output simultaneously.Although the above embodiment only describes with the lead frame of SOIC encapsulation, but art technology discloses according to the fundamental design idea of the lead frame of above SOIC encapsulation, this fundamental design idea can be analogized and be applied in other packing forms, for example, DIP (Double In-line Package, the in line encapsulation of biserial), SSOP (Small OutlinePackage, little outline packages), TSSOP (Thin Small Outline Package, thin little outline packages), SDIP (Small Double In-line Package, the in line encapsulation of little spacing biserial) etc., thereby technical problem more than same solution also reaches essentially identical technique effect.
For making exemplary illustration, below take the lead frame of DIP as example, describe in detail and how to apply above fundamental design idea.
The structural representation of the DIP lead frame providing according to the second embodiment of the present invention is provided.In the embodiment shown in fig. 6, the outer pin of not shown DIP lead frame 60.As shown in Figure 6, DIP lead frame 60 comprises island 631 and 633 and the interior pin 651,6531,6532,6533,6534,6535,6536 that around distributes with island.Wherein interior pin 651 is for the high-tension interior pin of input/output (being called for short " high-pressure internal guiding pin "), and interior pin 6531,6532,6533,6534,6535,6536 is the interior pin (being called for short " pin in low pressure ") for input/output low-voltage.In this embodiment, be provided with two islands 631,633 on lead frame 60, therefore it can be used for encapsulating two chips simultaneously, particularly, places the high-tension chip of input/output on island 631, places the chip of input/output low-voltage on island 633.It will be appreciated by those skilled in the art that, the island of greater number can also be set on lead frame, it is specifically determined by packaged number of chips, for example, can comprise three islands, on one of them island, place the high-tension chip of input/output, on two other island, place the chip of input/output low-voltage; Certainly the quantity of island also can be 1, and the chip of placing on this island both comprised high-tension input/output end, also comprised the input/output end of low-voltage, and usually, this chip is relatively less.Therefore, the concrete quantity of island is not to be subject to embodiment of the present invention restriction.Normally, the lead frame 60 of this embodiment is mainly used in encapsulating two dissimilar chips, I/O in the time of with compatible high voltage and low-voltage.In addition, in this embodiment, island 631 and island 633 separate independent design according to high-low pressure, also corresponding increase of its spacing D5 (as shown in Figure 6), the size range of D5 is for being more than or equal to 0.25 millimeter, for example D5 can be 0.35 millimeter, thereby can effectively realize the high-low pressure isolation between island.
Continue to refer to Fig. 6, in this embodiment, this lead frame 60 is that traditional DIP8 lead frame is improved and designed, and therefore designs, processes relatively simple.Traditional DIP8 lead frame is for I/O low-voltage, and wherein, 8 interior pins divide two rows evenly distributed, by removing pin in one of them, can increase the wherein adjacent spacing of two interior pins.In this embodiment, for the high-tension interior pin 651 of input/output and for the interior pin originally arranging between the interior pin 6531 of input/output low-voltage, be removed, thereby make the centre-to-centre spacing D4 (as shown in Figure 6) between interior pin 651 and interior pin 6531 become original twice (for example D4 is 0.508 millimeter).Pin 6532,6533,6534,6535 and 6536 is owing to being for input/output low-voltage equally in other, therefore itself and traditional design are basic identical, also in pin 6532,6533,6534,6535 and 6536 center distance be each other generally 0.254 millimeter.Further, in this embodiment, island 631 with for the high-tension interior pin 651 of input/output, be directly connected, the port of chip arranging on island 631 also can be connected to interior pin 651 with gold wire bonding, thereby realizes high-tension input/output encapsulation.Therefore, for example, during low-voltage that high voltage, interior pin 6531 input/output that interior pin 651 input/output is 200 volts are 5 volts, because the center distance between two pins widens (edge spacing is corresponding widening also), form after plastic-sealed body its plastic-sealed body isolation effect also better, thereby can effectively avoid on interior pin 651 the internal pin 6351 of voltage signal to cause, crosstalk.In the case of the interior pin 6351 adjacent with interior pin 651 avoided crosstalking, other also must avoid crosstalking from farther interior pin with interior pin 651.
It should be noted that, in above embodiment, be that a pin by traditional DIP8 lead frame is removed between interior pin 651 and interior pin 6531 increases the distance between interior pin, thereby avoid between interior pin due to crosstalking that high-voltage signal causes another pin.But this is not restrictive.Those skilled in the art can be under the instruction of above embodiment, traditional DIP8 lead frame is removed to pin in two or more to increase the spacing between pin in high-pressure internal guiding pin and low pressure, for example, in the situation that pin number allows, can also remove interior pin 6531, thereby increase the spacing between pin 6532 in high-pressure internal guiding pin 651 and low pressure; In addition, also can directly design the spacing between pin in increase high-pressure internal guiding pin and low pressure, avoid crosstalking, for example design the spacing range between pin in high-pressure internal guiding pin and low pressure and be not less than 0.508 millimeter, spacing relative decrease between pin in other low pressure simultaneously, thus can guarantee that the lead frame area entirety of DIP encapsulation does not increase.
Also it should be noted that, in above embodiment, only schematically illustrate the situation that only comprises a high-pressure internal guiding pin, due in actual applications, High voltage output/the input of chip is relatively less, and a high-pressure internal guiding pin can be connected with multiple High voltage outputs/input while gold wire bonding of chip simultaneously, and therefore, next high-pressure internal guiding pin of ordinary circumstance can meet the package requirements of high pressure chip.But, in specific (special) requirements situation, for example, in much more relatively situations of the High voltage output/input of chip, can increase the quantity of the high-pressure internal guiding pin of lead frame, be for example set to 2.Preferably, each high-pressure internal guiding pin is arranged on the end of interior pin arrangements, example as shown in Figure 6, the left-end point of interior pin 651 row's of being arranged on pin arrangements, like this, only have one (for example, in pin 6531) with the adjacent interior pin of high-pressure internal guiding pin 651, only need to increase the spacing between the interior pin of a low pressure and high-pressure internal guiding pin, be conducive to the area of maximum possible saving chip.
Further, in this embodiment, between interior pin 6534 and island 633, be directly connected, therefore, the interior pin 6534 in low pressure in pin can be for drawing the electrode at the back side of the chip of placing on island 633.
Structural representation while Figure 7 shows that the outer pin of the lead frame strip of DIP shown in Fig. 6.As shown in Figure 7, DIP lead frame 60 can also comprise outer pin 671, 6731, 6732, 6733, 6734, 6735, 6736, shown in Fig. 6, outer pin 671, 6731, 6732, 6733, 6734, 6735, 6736 are connected respectively in interior pin 651, 6531, 6532, 6533, 6534, 6535, 6536 synchronize and form with the lead frame shown in Fig. 6, therefore, the 671st, for the high-tension outer pin of input/output (referred to as " the outer pin of high pressure "), 6731, 6732, 6733, 6734, 6735 and 6736 is the outer pins (referred to as " the outer pin of low pressure ") for input/output low-voltage.In this embodiment, similarly, by remove pin outside between outer pin 671 and outer pin 6731 in traditional DIP8 lead frame, outer pin 671 and 6731 between center distance become original twice, for example from original 0.254 millimeter, become 0.508 millimeter.In the design of lead frame, outer pin is aimed at design successively corresponding to interior pin arrangements, therefore, such as the design of the above-described spacing about interior pin, can analogize in the design that is applied to outer pin.Due to widening of the spacing between the outer pin 671 of high pressure and the adjacent outer pin 6731 of low pressure, can avoid outer pin 6731 to avoid crosstalking from the high-voltage signal of the outer pin 671 of outer pin.
Figure 8 shows that according to the DIP lead frame shown in Fig. 7 and arrange the array of leadframes schematic diagram forming.Due in actual package process, be to the encapsulation formation simultaneously side by side of multiple chips.Therefore, before encapsulation, DIP lead frame is not unit independently, but the form that the DIP lead frame shown in multiple Fig. 7 60 is arranged by multiple lines and multiple rows forms DIP array of leadframes, is conducive to like this efficient encapsulation.In this is embodiment illustrated in fig. 8, schematically provide the lead frame 60 that 3 row 2 are listed as and arranged the array of leadframes 70 forming, but this is not restrictive, the concrete quantity of array of leadframes, spread pattern are not limited by the embodiment of the present invention, for example, can also be that 16 lead frames, 60 arrangements that 8 row 2 are listed as form.
Above example has mainly illustrated lead frame of the present invention, array of leadframes and encapsulating structure.Although only some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can implement not departing from its purport and scope with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, and in the situation that not departing from spirit of the present invention as defined in appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (11)
1. a lead frame, comprise pin, it is characterized in that, described pin comprises the first pin and second pin of adjacent setting, described the first pin is for input/output the first voltage, described the second pin is for input/output second voltage, spacing between described the first pin and described the second pin is set so that described the second pin is avoided the crosstalking of Voltage-output signal of described the first pin;
Wherein, described the first voltage refers to the voltage between 100 volts to 800 volts, and described second voltage refers to the voltage that is less than or equal to 50 volts;
Described lead frame comprises the first island and the second island, and described the first island is used for placing the high-tension chip of input/output, and described the second island is for placing the chip of input/output low-voltage; Spacing range between described the first island and described the second island is for being more than or equal to 0.25 millimeter.
2. lead frame as claimed in claim 1, it is characterized in that, described lead frame is improved and is designed by the low-voltage lead frame to for input/output second voltage, by removing a pin of described low-voltage lead frame, two pins adjacent with the pin of this removal are defined as respectively described the first pin and described the second pin.
3. lead frame as claimed in claim 2, it is characterized in that, the pin of described lead frame also comprises multiple the 3rd pins for input/output second voltage, spacing between described the first pin and described the second pin is the twice of the spacing between described the second pin and described the 3rd pin, or is the twice of spacing between adjacent described the 3rd pin.
4. the lead frame as described in claim 1 or 2 or 3, is characterized in that spacing centered by described spacing.
5. lead frame as claimed in claim 3, is characterized in that, the second pin is directly connected with same island with the form that merges output with the 3rd pin described in one of them simultaneously.
6. lead frame as claimed in claim 1, is characterized in that, the first pin is directly connected with described the first island.
7. lead frame as claimed in claim 1 or 2, is characterized in that, described pin is interior pin and/or outer pin.
8. lead frame as claimed in claim 1 or 2, is characterized in that, described the first pin is arranged on the end of place pin arrangements.
9. lead frame as claimed in claim 1 or 2, is characterized in that, described lead frame is that small outline integrated circuit is encapsulation, the in line encapsulation of biserial, little spacing biserial lead frame in line encapsulation, little outline packages or thin little outline packages.
10. an array of leadframes, is characterized in that, comprises multiple lead frames as claimed in any one of claims 1-9 wherein of arranging by row and column.
11. 1 kinds of encapsulating structures, is characterized in that, comprise lead frame as claimed in any one of claims 1-9 wherein.
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| CN102468260B true CN102468260B (en) | 2014-04-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101661893A (en) * | 2008-08-29 | 2010-03-03 | 三洋电机株式会社 | Resin sealing type semiconductor device and method of manufacturing the same, and lead frame |
| CN201829477U (en) * | 2009-12-18 | 2011-05-11 | 无锡华润安盛科技有限公司 | Plastic biserial collinear packaging plastic package body, plastic package body array and packaging device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661893A (en) * | 2008-08-29 | 2010-03-03 | 三洋电机株式会社 | Resin sealing type semiconductor device and method of manufacturing the same, and lead frame |
| CN201829477U (en) * | 2009-12-18 | 2011-05-11 | 无锡华润安盛科技有限公司 | Plastic biserial collinear packaging plastic package body, plastic package body array and packaging device |
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Denomination of invention: Lead frames, lead frame arrays, and their packaging structures that are compatible with high and low voltages Granted publication date: 20140430 Pledgee: Bank of China Limited Wuxi Branch Pledgor: WUXI CHINA RESOURCE MICRO-ASSEMBLY TECH., Ltd. Registration number: Y2024980040722 |