CN206806338U - It is thinned the encapsulating structure that splices of dual chip - Google Patents
It is thinned the encapsulating structure that splices of dual chip Download PDFInfo
- Publication number
- CN206806338U CN206806338U CN201720516992.2U CN201720516992U CN206806338U CN 206806338 U CN206806338 U CN 206806338U CN 201720516992 U CN201720516992 U CN 201720516992U CN 206806338 U CN206806338 U CN 206806338U
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- CN
- China
- Prior art keywords
- chip
- circuit board
- weld pad
- hollow hole
- dual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000009977 dual effect Effects 0.000 title claims abstract description 17
- 229920000297 Rayon Polymers 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000019491 signal transduction Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A kind of encapsulating structure that splices for being thinned dual chip, including one first chip, one first side include multiple weld pads；One second chip application viscose is attached to above first chip, and one first side includes multiple weld pads；One circuit board, it forms a central hollow hole and a first side hollow hole；Circuit board position between the central hollow hole and the first side hollow hole forms first side weld pad；It is attached in the assembled state above first chip below the circuit board so that second chip is located inside the central hollow hole；The weld pad of the first side of first chip is located inside the first side hollow hole of the circuit board and is exposed in the first side hollow hole；The weld pad of the first side of first chip and the first side weld pad at the circuit board position are connected during connection using the first wire, the second wire is reapplied and connects the first side weld pad at the circuit board position and the weld pad of the first side of second chip.
Description
Technical field
Semiconductor package is the utility model is related to, especially a kind of encapsulating structure that splices for being thinned dual chip.
Background technology
(as shown in Figure 5) is by a DRAM generally for DSP (digital processing unit) chipset feature in the prior art
10 ' are placed on a circuit board 30 ', then DSP 20 ' is placed on DRAM 10 ', and apply wire 51 ' to connect DRAM 10 ' and electricity
Road plate 30 ', and another group of wire 52 ' of application connects DSP 20 ' and DRAM 10 '.
The thickness direction of this structure includes the height of circuit board 30 ', DRAM 10 ', DSP 20 ' and the wire 52 ' of connection
Degree.And an encapsulating structure 60 ' must be added in the periphery of said structure.So integral thickness except necessary DRAM 10 ' and
DSP 20 ' outside, in addition to circuit board 30 ' and the thickness of the height of wire 52 '.So overall chipset feature forms certain height
Degree.
In the application of electronic installation, more and more thinner is typically required, relatively the thickness of the component of the inside also must be a large amount of
Reduction.Therefore in a number of applications, the thickness of electronic installation is often limited to the thickness of said chip group.Inventor is based on
For a long time for the understanding of encapsulation, it is desirable that proposing a kind of brand-new packing forms, whole chip is reduced using the technology of encapsulation
The thickness of group, the relative thickness for reducing the electronic installation for installing the chipset.
Utility model content
So the purpose of this utility model is, solves the problems, such as in above-mentioned prior art, one is proposed in the utility model
The encapsulating structure that splices of kind slimming dual chip, the second chip above the first chip is placed in the central hollow out of circuit board
In hole, so the thickness of overall chipset encapsulating structure is reduced, and the height of the wire of signal transduction is also greatly reduced.Institute
Greatly reduced with the chipset integral thickness formed using technology of the present utility model, and in many semiconductor chips
Overall thickness is reduced using above needing badly, and reduces the thickness and contact wiring height of the second chip in the utility model simultaneously
The thickness presented, this fails to reach in the prior art.
To reach above-mentioned purpose, a kind of encapsulating structure that splices for being thinned dual chip is proposed in the utility model, including：One
First chip, one first side include multiple weld pads, for input or output signal or electric power；One second chip, using glutinous
Glue is attached to the top of first chip, and one first side includes multiple weld pads, for input or output signal or electric power；One
Circuit board, the wherein circuit board form a central hollow hole and a first side hollow hole；The central hollow hole and this first
Circuit board position between the hollow hole of side forms first side weld pad；Wherein first chip in the assembled state is upper
Side is attached to the lower section of the circuit board, and causes second chip to be located at the inside of the central hollow hole；And first chip
The weld pad of first side is located inside the first side hollow hole of the circuit board, and is exposed in the first side hollow hole；
During connection, the weld pad of the first side of first chip is connected to first side at the circuit board position using the first wire
Side weld pad, reapply the first side that the first side weld pad at the circuit board position is connected to second chip by the second wire
The weld pad on side, and the signal of first chip or electric power one are connected to be connected to second chip by this.Wherein
One second side of first chip includes multiple weld pads, for input or output signal or electric power；The one of second chip
Dual side-edge includes multiple weld pads, for input or output signal or electric power；The circuit board forms a second side hollow hole；At this
Circuit board position between central hollow hole and the second side hollow hole forms second side weld pad；Wherein in assembling shape
Under state, the weld pad of the second side of first chip is located inside the second side hollow hole of the circuit board, and is exposed at this
In the hollow hole of second side；During connection, the weld pad of the second side of first chip is connected to the circuit using privates
The second side weld pad at position, reapplies privates and is connected to the second side weld pad at the circuit board position above plate
The weld pad of the second side of second chip, and the signal of first chip or electric power one are connected to connect by this
To second chip.Wherein weld pad, and the front or behind of the circuit board are configured in addition in the front or behind of second chip
Also weld pad is configured；The weld pad in front of second chip is connected into weld pad in front of the circuit board using the 5th wire, or using
Six wires connect the weld pad at the second chip rear the weld pad at the circuit board rear.One encapsulated layer, for by the central hollow out
Hole, first side hollow hole filling encapsulating material, and cause a chipset is integrally formed, other convenient electronic circuits make
With.
Wherein, first chip is a DRAM, and second chip is a dsp chip.
Wherein, the size of the DRAM is 7.7mm × 7.4mm, and the size of the dsp chip is 5.2mm × 5.2mm,
The size of the circuit board is 8mm × 8mm.
Brief description of the drawings
Fig. 1 shows the utility model component combination diagram.
Fig. 2 shows the utility model component compound section figure.
Fig. 3 shows the combination diagram of the first chip of the present utility model, the second chip and circuit board.
Fig. 4 shows another component combination diagram of the utility model.
Fig. 5 shows the schematic cross-section of the chipset feature of prior art.
Description of reference numerals
The chips of 10- first
10’-DRAM
15- weld pads
The chips of 20- second
20’-DSP
25- weld pads
26- weld pads
30- circuit boards
30 '-circuit board
Weld pad on the left of 32-
Weld pad on the right side of 34-
36- weld pads
40- centers hollow hole
Hollow hole on the left of 42-
Hollow hole on the right side of 44-
The wires of 51- first
51 '-apply wire
The wires of 52- second
52 '-wire
53- privates
54- privates
The wires of 55- the 5th
The wires of 56- the 6th
60- encapsulated layers
70- viscoses.
Embodiment
Feature and its advantage of the present utility model can be further understood that by the description below, during reading and refer to attached
Figure.
Now with regard to structure composition of the present utility model, and the effect of can be generated and advantage, coordinate accompanying drawing, lift the utility model
A preferred embodiment describe in detail it is as follows.
It refer to shown in Fig. 1 to Fig. 4, the encapsulating structure that splices of display slimming dual chip of the present utility model, including under
Row component：
One first chip 10, its left and right sides include multiple weld pads 15 (as shown in Figure 3), for input or output signal
Or electric power.
One second chip 20, the top (as shown in Figure 2) of first chip 10 is attached to using viscose 70, its left and right sides
Side includes multiple weld pads 25 (as shown in Figure 3), for input or output signal or electric power.
One circuit board 30, the wherein circuit board 30 form a central hollow hole 40, a left side hollow hole 42 and a right side and engraved
Emptying aperture 44.Above the central hollow hole 40 and circuit board 30 on the left of this between hollow hole 42 position formed on the left of weld pad 32；
And above the central hollow hole 40 and circuit board 30 on the right side of this between hollow hole 44 position formed on the right side of weld pad 34.
Wherein the top of first chip 10 is attached to the lower section of the circuit board 30 in the assembled state, and cause this second
Chip 20 is located at the inside of the central hollow hole 40.And the weld pad 15 in the left side of the first chip 10 is located at the left side of the circuit board 30
Inside side hollow hole 42, and it is exposed in the left side hollow hole 42；And the weld pad 15 on the right side of the first chip 10 is located at the circuit
Inside the right side hollow hole 44 of plate 30, and it is exposed in the right side hollow hole 44.
During connection, the weld pad 15 in the left side of the first chip 10 is connected to the upper portion of circuit board 30 using the first wire 51
The left side weld pad 32 of position, reapplies the second wire 52 and the left side weld pad 32 at the top position of circuit board 30 is connected into second core
The weld pad 25 in the left side of piece 20, and allow first chip 10 signal or electric power by this one connect be connected to this second
Chip 20.
Likewise, the weld pad 15 on the right side of the first chip 10 is connected to the upper portion of circuit board 30 using privates 53
The right side weld pad 34 of position, reapplies privates 54 and the right side weld pad 34 at the top position of circuit board 30 is connected into second core
The weld pad 25 on the right side of piece 20, and allow first chip 10 signal or electric power by this one connect be connected to this second
Chip 20.
As shown in figure 4, the utility model can also configure weld pad 26 in addition in the front of second chip 20 and rear, and
The front and rear of the circuit board 30 also configure weld pad 36.The weld pad 26 in the front of the second chip 20 is connected using the 5th wire 55
The weld pad 36 in the front of circuit board 30 is connect, and the weld pad at the rear of the second chip 20 is connected into the circuit board using the 6th wire 56
The weld pad 36 at 30 rears, therefore the signal of second chip 20 can be configured by the front and rear of the circuit board 30
Weld pad 36 transmits or by outside input outward.And the electric power or signal of first chip 10 can also be passed using this path
It is defeated.
As shown in Fig. 1 and Fig. 4, the utility model also includes an encapsulated layer 60, for the central hollow hole 40, left side to be engraved
Emptying aperture 42 and right side hollow hole 44 fill encapsulating material, and cause a chipset is integrally formed, other convenient electronic circuits
Use.
In preferred embodiment of the present utility model, its structure is same as an explanation example, and wherein first chip 10 is one
DRAM (such as LPDDRDRAM), and second chip 20 is a dsp chip.Therefore entire combination is into a chip that can be actually used
Group.Wherein the size of the DRAM is 7.7mm × 7.4mm, and the size of the dsp chip is 5.2mm × 5.2mm, the circuit board
30 size is 8mm × 8mm.The appropriate portion for cutting the central hollow hole 40, left side hollow hole 42 and right side hollow hole 44
Position then can be configured to the structure of described above.
The advantages of the utility model is that the second chip above the first chip is placed in the central hollow hole of circuit board
It is interior, so the thickness of overall chipset encapsulating structure is reduced, and the height of the wire of signal transduction is also greatly reduced.So
The chipset integral thickness formed using technology of the present utility model greatly reduces, and answering in many semiconductor chips
Use to need badly and to reduce overall thickness, and reduce thickness and the contact wiring height institute of the second chip in the utility model simultaneously
The thickness of presentation, this fails to reach in the prior art.
In summary, the design of consideration of the utility model hommization, quite meets actual demand.It specifically improves existing skill
The defects of art, substantially there is breakthrough progress advantage compared to prior art, there is the enhancement of effect really, and non-be easy to reach
Into.The utility model does not disclose or is exposed in domestic document and in the market with foreign countries, has met the regulation of Patent Law.
Above-mentioned detailed description is illustrating for a possible embodiments of the present utility model, but the embodiment is not used
To limit the scope of protection of the utility model, all equivalence enforcements or change without departing from carried out by the utility model skill spirit,
It should be contained in the scope of protection of the utility model.
Claims (6)
- A kind of 1. encapsulating structure that splices for being thinned dual chip, it is characterised in that including：One first chip, one first side include multiple weld pads, for input or output signal or electric power；One second chip, the top of first chip is attached to using viscose, one first side includes multiple weld pads, for defeated Enter or output signal or electric power；One circuit board, wherein, the circuit board forms a central hollow hole and a first side hollow hole；In the central hollow hole and Circuit board position between the first side hollow hole forms first side weld pad；Wherein, the lower section of the circuit board is attached to above first chip in the assembled state, and causes the second chip position In the inside of the central hollow hole；And the weld pad of the first side of first chip is located at the first side hollow out of the circuit board Inside hole, and it is exposed in the first side hollow hole；During connection, the weld pad of the first side of first chip is connected to the of the circuit board position using the first wire One side solder pad, reapply the first side weld pad at the circuit board position is connected to second chip by the second wire The weld pad of one side, and the signal of first chip or electric power one are connected to be connected to second chip by this.
- 2. the encapsulating structure that splices of slimming dual chip as claimed in claim 1, it is characterised in that the one the of first chip Dual side-edge includes multiple weld pads, for input or output signal or electric power；Wherein, a second side of second chip includes multiple weld pads, for input or output signal or electric power；Wherein, the circuit board forms a second side hollow hole；Between the central hollow hole and the second side hollow hole Circuit board position forms second side weld pad；Wherein, in the assembled state, the weld pad of the second side of first chip is located at the second side hollow out of the circuit board Inside hole, and it is exposed in the second side hollow hole；During connection, the weld pad of the second side of first chip is connected to the of the circuit board position using privates Dual side-edge weld pad, reapply the second side weld pad at the circuit board position is connected to second chip by privates The weld pad of dual side-edge, and the signal of first chip or electric power one are connected to be connected to second chip by this.
- 3. the encapsulating structure that splices of slimming dual chip as claimed in claim 1, it is characterised in that before second chip Side or rear configure weld pad in addition, and the front or behind of the circuit board also configures weld pad；Using the 5th wire by second core Weld pad in front of piece connects the weld pad in front of the circuit board, or the 6th wire of application should by the weld pad connection at the second chip rear The weld pad at circuit board rear.
- 4. the encapsulating structure that splices of slimming dual chip as claimed in claim 1, it is characterised in that also including an encapsulated layer, For the central hollow hole, first side hollow hole to be filled into encapsulating material, and to be integrally formed a chipset, it is convenient its The use of his electronic circuit.
- 5. the encapsulating structure that splices of slimming dual chip as claimed in claim 1 or 2 or 3 or 4, it is characterised in that this first Chip is a DRAM, and second chip is a dsp chip.
- 6. the encapsulating structure that splices of slimming dual chip as claimed in claim 5, it is characterised in that the size of the DRAM is 7.7mm × 7.4mm, and the size of the dsp chip is 5.2mm × 5.2mm, the size of the circuit board is 8mm × 8mm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720516992.2U CN206806338U (en) | 2017-05-10 | 2017-05-10 | It is thinned the encapsulating structure that splices of dual chip |
| PCT/CN2017/116948 WO2018205625A1 (en) | 2017-05-10 | 2017-12-18 | Thinned double-chip spliced package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720516992.2U CN206806338U (en) | 2017-05-10 | 2017-05-10 | It is thinned the encapsulating structure that splices of dual chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206806338U true CN206806338U (en) | 2017-12-26 |
Family
ID=60740355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720516992.2U Expired - Fee Related CN206806338U (en) | 2017-05-10 | 2017-05-10 | It is thinned the encapsulating structure that splices of dual chip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN206806338U (en) |
| WO (1) | WO2018205625A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878408A (en) * | 2017-05-10 | 2018-11-23 | 叶秀慧 | It is thinned the encapsulating structure that splices of dual chip |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201302B1 (en) * | 1998-12-31 | 2001-03-13 | Sampo Semiconductor Corporation | Semiconductor package having multi-dies |
| US20020105789A1 (en) * | 2001-02-02 | 2002-08-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package for multi-chip stacks |
| CN2664079Y (en) * | 2003-10-14 | 2004-12-15 | 胜开科技股份有限公司 | Small-sized memory card structure |
| CN2762351Y (en) * | 2004-12-30 | 2006-03-01 | 昆达电脑科技(昆山)有限公司 | Multi-chip mounting structure |
| CN201174381Y (en) * | 2008-03-28 | 2008-12-31 | 菱生精密工业股份有限公司 | Construction reducing thickness of integrated circuit package |
| CN103915423A (en) * | 2014-04-04 | 2014-07-09 | 华进半导体封装先导技术研发中心有限公司 | Three-dimensional stack-packaging structure and method for chips |
| CN103904066A (en) * | 2014-04-04 | 2014-07-02 | 华进半导体封装先导技术研发中心有限公司 | Flip chip stacking packaging structure and packaging method |
-
2017
- 2017-05-10 CN CN201720516992.2U patent/CN206806338U/en not_active Expired - Fee Related
- 2017-12-18 WO PCT/CN2017/116948 patent/WO2018205625A1/en active Application Filing
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878408A (en) * | 2017-05-10 | 2018-11-23 | 叶秀慧 | It is thinned the encapsulating structure that splices of dual chip |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018205625A1 (en) | 2018-11-15 |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171226 |