CN104167403B - Lead frame for multi-pin encapsulation - Google Patents
Lead frame for multi-pin encapsulation Download PDFInfo
- Publication number
- CN104167403B CN104167403B CN201410410154.8A CN201410410154A CN104167403B CN 104167403 B CN104167403 B CN 104167403B CN 201410410154 A CN201410410154 A CN 201410410154A CN 104167403 B CN104167403 B CN 104167403B
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- Prior art keywords
- base island
- pin
- wire bonding
- bonding area
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000005538 encapsulation Methods 0.000 title abstract 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a lead frame for multi-pin encapsulation. The lead frame for multi-pin encapsulation comprises a base island area used for containing a chip, and a plurality of pins. The base island area comprises a first base island and a second base island, wherein the first base island and the second base island are close to each other and are isolated. The left side and the right side of the base island area are respectively provided with a plurality of routing areas, and the upper portion and the lower portion of the base island area are only provided with the pins connected with the first base island and the second base island respectively and are not provided with routing areas. Specifically, the first base island and the second base island are located on the left portion and the right portion of the base island area respectively and are isolated by an inclined isolating belt. According to the lead frame for the multi-pin encapsulation, an original lead frame is reasonably and locally changed, the area, capable of being encapsulated, of the chip is enlarged under the premise that cost is barely increased, and the need for encapsulating large-size chips can be met.
Description
Technical Field
The invention relates to a packaging structure of an integrated circuit, in particular to a lead frame for packaging an integrated circuit chip.
Background
The lead frame is used as a chip carrier of an integrated circuit, realizes the electrical connection between the leading-out end of an internal circuit of the chip and an external lead by means of bonding materials (gold wires, aluminum wires and copper wires), forms a key structural member of an electrical circuit, and plays a role of a bridge connected with an external lead.
As integrated circuits are increasingly miniaturized, the package size of the integrated circuits is required to be reduced in order to comply with the development, but as the package size of the integrated circuits is reduced, the lead frame of the integrated circuits tends to be reduced, while simply reducing the lead frame of the integrated circuits in equal proportion may reduce the chip area of the package proportionally, which is not desirable for the integrated circuits.
A conventional lead frame of an integrated circuit packaged by 6 pins is shown in fig. 1, and mainly comprises pins 3, a wire bonding area 4 connected with the pins 3, and a base island 1, which are made of metal materials. The base island 1 is used for placing a chip, the pins 3 are external leads of the packaged integrated circuit, and the black areas are completely wrapped by plastic packaging materials after packaging, so that metal wires connected with the chip and the external pins can be connected to a wire bonding area only and cannot be connected to other places, and connection of the chip circuit terminals and the pins is achieved. As can be seen from this figure, the chip must be placed on the base island 1, and therefore the chip size using this packaged lead frame must be smaller than the size of the base island. Because the size of the chip base island is influenced by the middle wire bonding area in the Y direction, the base island is smaller, so that the circuit area which can be packaged by the lead frame is smaller, and the requirements of some large chips cannot be met.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a multi-pin packaged lead frame capable of enlarging the area of a base island region, so that the area of a chip capable of being packaged is enlarged. The technical scheme adopted by the invention is as follows:
a multi-pin packaged lead frame comprises a base island region for placing a chip and a plurality of pins, wherein the base island region comprises a first base island and a second base island which are close to each other but isolated; a plurality of wire bonding areas are arranged on the left side and the right side of the base island area, but only pins respectively connected with the first base island and the second base island are arranged below and above the base island area, and the wire bonding areas are not arranged.
Specifically, the first base island and the second base island are respectively positioned at the left part and the right part of the base island region and are isolated by the oblique isolation belt;
a first pin is arranged at the upper left of the base island region, a second pin is arranged in the middle of the upper side of the base island region, and a third pin is arranged at the upper right of the base island region; a fourth pin is arranged on the lower left side, a fifth pin is arranged in the middle of the lower side, and a sixth pin is arranged on the lower right side; the second pin is integrally connected with the second base island, and the fifth pin is integrally connected with the first base island;
the left side of the first base island is provided with:
the first wire bonding area is positioned above the left side, the second wire bonding area is positioned in the middle of the left side, and the third wire bonding area is positioned below the left side, wherein the first wire bonding area is integrally connected with the first pin, the second wire bonding area is integrally connected with the first base island, and the third wire bonding area is integrally connected with the fourth pin;
the right side of the second base island is provided with:
the fourth wire bonding area is located above the right side, the fifth wire bonding area is located in the middle of the right side, and the sixth wire bonding area is located below the right side, wherein the fourth wire bonding area is integrally connected with the third pins, the fifth wire bonding area is integrally connected with the second base island, and the sixth wire bonding area is integrally connected with the sixth pins.
Furthermore, the first base island, the second wire bonding area and the fifth pin are made of an integrated copper sheet.
Furthermore, the second base island, the fifth wire bonding area and the second pin are made of an integrated copper sheet.
The invention has the advantages that: the invention reasonably and locally changes the original lead frame, enlarges the area of the chip which can be packaged on the premise of hardly increasing the cost, and can meet the packaging requirement of the chip with larger size.
Drawings
Fig. 1 is a diagram of a conventional 6-pin package lead frame.
Fig. 2 is a 6-pin package lead frame diagram of the present invention.
Fig. 3 is a diagram of a conventional 6-pin packaged lead frame after chip mounting and bonding.
Fig. 4 is a schematic diagram of the 6-pin package lead frame of the present invention after chip mounting and bonding.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 3, when a conventional 6-pin lead frame is used for packaging, a chip 100 is mounted on a base island 1, the back surface of the chip 100 is attached to the base island, and the front surface having a bonding pad 101 faces upward, so that the bonding pad 101 and a bonding area 4 are connected by using a bonding wire 6. The base island 1 is usually a copper sheet, and the base island 1, a routing area in the middle of the left side and a routing area in the middle of the right side are integrated into a whole; the base island connects two wire bonding areas 4, and one wire bonding area in the middle of the left side and the right side is wasted due to the connection. Above and in the middle of the base island there is also a wire bonding area integral with the pin 3, which limits the size of the base island in the Y direction. It is evident from fig. 3 that the chip area placed is small.
In this embodiment, a lead frame for 6-pin package is proposed, as shown in fig. 2, the basic structure is to divide the original island into two parts, which become a island region.
The first base island 1-1 and the second base island 1-2 are respectively positioned at the left part and the right part of the base island region and are isolated by an oblique isolation belt 5; spaced apart, as shown in fig. 4, a single chip 100 may span over two base islands. The oblique isolation strip 5 is obtained by obliquely removing the strip-shaped copper sheet from a single base island.
A first pin 31 is arranged at the upper left of the base island region, a second pin 32 is arranged in the middle of the upper side of the base island region, and a third pin 33 is arranged at the upper right of the base island region; a fourth pin 34 is arranged at the lower left, a fifth pin 35 is arranged in the middle of the lower part, and a sixth pin 36 is arranged at the lower right; the second pin 32 is integrally connected with the second base island 1-2, and the fifth pin 35 is integrally connected with the first base island 1-1;
on the left side of the first base island 1-1 are provided:
a first wire bonding area 41 positioned at the upper left side, a second wire bonding area 42 positioned at the middle left side, and a third wire bonding area 43 positioned at the lower left side, wherein the first wire bonding area 41 is integrally connected with the first pin 31, the second wire bonding area 42 is integrally connected with the first base island 1-1, and the third wire bonding area 43 is integrally connected with the fourth pin 34;
on the right side of the second base island 1-2 are provided:
a fourth wire bonding area 44 located above the right side, a fifth wire bonding area 45 located in the middle of the right side, and a sixth wire bonding area 46 located below the right side, wherein the fourth wire bonding area 44 is integrally connected with the third pin 33, the fifth wire bonding area 45 is integrally connected with the second base island 1-2, and the sixth wire bonding area 46 is integrally connected with the sixth pin 36.
The material of each base island, each pin and each wire bonding area can be a copper sheet. Wherein,
the first wire bonding area 41 and the first lead 31 are integrated into a copper sheet;
the third wire bonding area 43 and the fourth pin 34 are integrated into a copper sheet;
the fourth wire bonding area 44 and the third pin 33 are integrated into a copper sheet;
the sixth wire bonding area 46 and the sixth pin 36 are integrated into a copper sheet;
the first base island 1-1, the second wire bonding area 42 and the fifth pin 35 are integrated into a copper sheet;
the second base island 1-2, the fifth wire bonding area 45 and the second pin 32 are integrated into a copper sheet;
as shown in fig. 4, when the chip is mounted, the back surface of the chip 100 is attached to the base island region, and straddles over the first base island 1-1 and the second base island 1-2, the pads 101 on the front surface face upward, and each pad 101 is connected to six different wire bonding regions by a bonding wire 6.
Since the second wire bonding area 42 and the fifth pin 35 are located on an integrated copper sheet, the pad electrically connected to the second wire bonding area 42 can be electrically led out from the fifth pin 35. Similarly, the pad electrically connected to the fifth bonding area 45 can be electrically led out from the second lead 32.
Comparing fig. 4 and fig. 3, it can be found that, with the improved lead frame, the routing area in the middle above the base island is transferred to the middle on the right side through the second pin 32 and the second base island 1-2 integrally connected (that is, the routing area function in the middle above the base island is transferred to the fifth routing area 45 in the middle on the right side), so that the base island area is no longer affected by the routing area in the middle above the base island in the Y direction, and the area for placing the chip in the Y direction can be enlarged. At the same time, by dividing the base island into two, two wiring areas (the second wiring area 42 and the fifth wiring area 45) are prevented from being short-circuited, and two different electrical connections are obtained.
Therefore, in fig. 1, a wire bonding area which is wasted on one side is utilized, and the area for placing the chip in the Y direction is increased, so that the circuit area which can be packaged by the whole lead frame is increased, and the requirements of some large chips are met.
Claims (3)
1. A kind of multi-pin encapsulated lead frame, characterized by:
the chip packaging structure comprises a base island region and a plurality of pins, wherein the base island region is used for placing a chip and comprises a first base island (1-1) and a second base island (1-2) which are close to each other but isolated;
a plurality of wire bonding areas are arranged on the left side and the right side of the base island area, but only pins respectively connected with the first base island (1-1) and the second base island (1-2) are arranged below and above the base island area, and the wire bonding areas are not arranged;
the first base island (1-1) and the second base island (1-2) are respectively positioned at the left part and the right part of the base island region and are isolated by an oblique isolation belt (5);
a first pin (31) is arranged at the upper left of the base island region, a second pin (32) is arranged in the middle of the upper side of the base island region, and a third pin (33) is arranged at the upper right of the base island region; a fourth pin (34) is arranged at the lower left, a fifth pin (35) is arranged in the middle of the lower part, and a sixth pin (36) is arranged at the lower right; the second pin (32) is integrally connected with the second base island (1-2), and the fifth pin (35) is integrally connected with the first base island (1-1);
the left side of the first base island (1-1) is provided with:
a first wire bonding area (41) positioned at the upper left side, a second wire bonding area (42) positioned at the middle of the left side, and a third wire bonding area (43) positioned at the lower left side, wherein the first wire bonding area (41) is integrally connected with the first pin (31), the second wire bonding area (42) is integrally connected with the first base island (1-1), and the third wire bonding area (43) is integrally connected with the fourth pin (34);
the right side of the second base island (1-2) is provided with:
the fourth wire bonding area (44) is located on the upper portion of the right side, the fifth wire bonding area (45) is located in the middle of the right side, and the sixth wire bonding area (46) is located on the lower portion of the right side, wherein the fourth wire bonding area (44) is integrally connected with the third pin (33), the fifth wire bonding area (45) is integrally connected with the second base island (1-2), and the sixth wire bonding area (46) is integrally connected with the sixth pin (36).
2. The multi-pin packaged lead frame of claim 1, wherein:
the first base island (1-1), the second wire bonding area (42) and the fifth pin (35) are made of integrated copper sheets.
3. The multi-pin packaged lead frame of claim 1, wherein:
the second base island (1-2), the fifth wire bonding area (45) and the second pin (32) are made of integrated copper sheets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410410154.8A CN104167403B (en) | 2014-08-19 | 2014-08-19 | Lead frame for multi-pin encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410410154.8A CN104167403B (en) | 2014-08-19 | 2014-08-19 | Lead frame for multi-pin encapsulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104167403A CN104167403A (en) | 2014-11-26 |
| CN104167403B true CN104167403B (en) | 2017-02-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410410154.8A Active CN104167403B (en) | 2014-08-19 | 2014-08-19 | Lead frame for multi-pin encapsulation |
Country Status (1)
| Country | Link |
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| CN (1) | CN104167403B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010901A (en) * | 2017-12-20 | 2018-05-08 | 无锡红光微电子股份有限公司 | A kind of HZIP25 encapsulating leads |
| CN110265379B (en) * | 2019-06-26 | 2024-07-16 | 富满微电子集团股份有限公司 | IC lead support with inclined base island and packaged IC |
| CN110246824B (en) * | 2019-06-26 | 2024-06-18 | 富满微电子集团股份有限公司 | Double-base-island IC lead bracket with obliquely-arranged base islands and packaged IC |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359658A (en) * | 2008-09-04 | 2009-02-04 | 浙江华越芯装电子股份有限公司 | Multi-chip encapsulation construction of large power |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5291381B2 (en) * | 2008-05-19 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | Semiconductor package |
| US20130249071A1 (en) * | 2010-09-07 | 2013-09-26 | Jinzhong Yao | Semiconductor device and method of assembling same |
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2014
- 2014-08-19 CN CN201410410154.8A patent/CN104167403B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359658A (en) * | 2008-09-04 | 2009-02-04 | 浙江华越芯装电子股份有限公司 | Multi-chip encapsulation construction of large power |
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| Publication number | Publication date |
|---|---|
| CN104167403A (en) | 2014-11-26 |
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