CN210516706U - Novel packaging structure of power device - Google Patents
Novel packaging structure of power device Download PDFInfo
- Publication number
- CN210516706U CN210516706U CN201921707566.2U CN201921707566U CN210516706U CN 210516706 U CN210516706 U CN 210516706U CN 201921707566 U CN201921707566 U CN 201921707566U CN 210516706 U CN210516706 U CN 210516706U
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- CN
- China
- Prior art keywords
- substrate
- pins
- lead
- pin
- power device
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000004033 plastic Substances 0.000 claims abstract description 15
- 230000017525 heat dissipation Effects 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000003466 welding Methods 0.000 abstract description 10
- 238000009434 installation Methods 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract description 4
- 238000003780 insertion Methods 0.000 abstract description 3
- 230000037431 insertion Effects 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a novel packaging structure of power device, include: the circuit board comprises a substrate, wherein one side of the substrate is provided with a plurality of first pins connected with the substrate, and the other side of the substrate is provided with second pins, third pins and a plurality of fourth pins which are arranged at intervals with the substrate; the lead frame is jointed with the first lead, the second lead, the third lead and the fourth lead correspondingly; the plastic package body integrally packages the substrate, the metal heat sink, the chip and the lead frame. The utility model has the advantages that: 1. the packaging form is changed from a direct insertion type to a surface mounting form through the lead frame, and the automatic requirement of automatic surface mounting of the PCB is met. 2. Meanwhile, the installation space of the radiating fin is saved, and the area of the pin welding line area can be made to be different according to the current. 3. The adoption of the non-porous chip substrate provides possibility of space position for the welding of a large chip. 4. The appearance and the radiating fin are combined in a laminating mode, the surface of a device is not stressed greatly and is uniform, and no influence is caused on an internal chip.
Description
Technical Field
The utility model relates to a semiconductor power device technical field, in particular to novel packaging structure of power device.
Background
The current development of PCBs is that a circuit board of a direct-insert device is gradually replaced by a circuit board of a chip device, and a corresponding conventional packaging device needs to be changed. The traditional encapsulation pin form of arranging has limited the differentiation of different electric currents, and pin structure has also restricted the interior lead wire welding space of heavy current polarity in the frame, and the existence of traditional encapsulation frame Pad fin fixed orifices has restricted the welding dress space and the position of big chip, and during traditional installation fin, the screw dynamics is too big, and the device atress inequality can cause the deformation of inner frame Pad, and then leads to the chip damage inefficacy.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a novel packaging structure of power device to the technical defect who proposes in solving the aforesaid.
In order to realize the purpose, the technical scheme of the utility model is that:
a novel packaging structure of a power device comprises: the LED chip comprises a substrate, wherein a metal heat dissipation plate is arranged on the upper end face of the substrate, a chip is arranged on the lower end face of the substrate, a plurality of first pins connected with the substrate are arranged on one side of the substrate, second pins, third pins and a plurality of fourth pins which are arranged at intervals with the substrate are arranged on the other side of the substrate, and the second pins, the third pins and the fourth pins are connected with the chip through inner leads; the lead frame is attached and connected with the first lead, the second lead, the third lead and the fourth lead correspondingly; and the plastic package body is used for packaging and integrally forming the substrate, the metal radiating fin, the chip, the first pin, the second pin, the third pin, the fourth pin and the pin frame, wherein the upper end surface of the metal radiating fin and the upper end surface of the plastic package body are positioned on the same end surface.
Further, the substrate is a silicon wafer substrate.
Further, the metal heat dissipation plate is a copper heat dissipation plate.
Furthermore, the number of the first pins is not less than three, and the first pins are drain electrodes.
Further, the second pin is a gate.
Further, the third pin is a source test terminal.
Furthermore, the fourth pin is an integrated pin, and at least three fourth pins are arranged.
Further, the plastic package body is made of epoxy resin materials.
Further, the lead frames may be arranged in series along the length direction thereof.
The utility model has the advantages that: 1. the packaging form is changed from a direct insertion type to a surface mounting form through the lead frame, and the automatic requirement of automatic surface mounting of the PCB is met. 2. Meanwhile, the installation space of the radiating fin is saved, and the area of the pin welding line area can be made to be different according to the current. 3. The adoption of the non-porous chip substrate provides possibility of space position for the welding of a large chip. 4. The appearance and the radiating fin are combined in a laminating mode, the surface of a device is not stressed greatly and is uniform, and no influence is caused on an internal chip.
Drawings
Fig. 1 is a schematic front view of the present invention;
FIG. 2 is a schematic side view of the present invention;
fig. 3 is a schematic front view of the middle lead frame according to the present invention.
In the figure, 1-substrate; 2-a metal heat sink; 3-chip; 4-a first pin; 5-a second pin; 6-a third pin; 7-a fourth pin; 8-inner lead; 9-a lead frame; 10-plastic package body.
Detailed Description
The following describes the present invention with reference to the accompanying drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features related to the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1 to 3, a novel package structure of a power device includes: a substrate 1, a lead frame 9, and a plastic package body 10. The heat dissipation structure comprises a substrate 1, a metal heat dissipation plate 2, a chip 3, a plurality of first pins 4 connected with the substrate 1, a plurality of second pins 5, third pins 6 and a plurality of fourth pins 7, wherein the metal heat dissipation plate 2 is arranged on the upper end face of the substrate 1, the metal heat dissipation plate 2 and the upper end face of the substrate 1 are of an integral structure, the chip 3 is arranged on the lower end face of the substrate 1, the first pins 4 connected with the substrate 1 are arranged on one side of the substrate 1, the second pins 5, the third pins 6 and the fourth pins 7 are arranged on the other side of the substrate 1 at intervals with; the lead frame 9 is attached to the first lead 4, the second lead 5, the third lead 6 and the fourth lead 7.
The plastic package body 10 packages and integrates the substrate 1, the metal radiating fin 2, the chip 3, the first pin 4, the second pin 5, the third pin 6, the fourth pin 7 and the pin frame 9, the upper end face of the metal radiating fin 2 and the upper end face of the plastic package body 10 are located on the same end face, the plastic package body 10 and the metal radiating fin 2 are combined in a laminating mode, the stress on the surface of a device is small and uniform, no influence is caused on the internal chip, and the radiating effect is good.
Specifically, the substrate 1 is a non-porous silicon wafer substrate, which provides space position possibility for the soldering of a large chip.
Specifically, the metal heat sink 2 is a copper heat sink, and is exposed on an end surface of the plastic package body 10 after being packaged by the plastic package body 10, so that the heat dissipation effect on the chip 3 is good.
Specifically, the number of the first pins 4 is not less than three, the first pins 4 are drain electrodes and are connecting pieces between each device unit, the connecting pieces need to be cut off when finished products are manufactured, the requirement of large current can be met, and unequal areas can be made in the pin welding wire areas according to the size of the current.
Specifically, the second lead 5 is a gate. The area of the pin welding wire area can be made to be unequal according to the current.
Specifically, the third pin 6 is a source test terminal, and the chip 3 is conveniently detected through the source test terminal.
Specifically, the fourth pin 7 is an integrated pin, and at least five fourth pins 7 are provided. Chips of different areas can be soldered on the substrate according to the magnitude of the current.
Specifically, the plastic package body 10 is made of an epoxy resin material.
Specifically, the lead frame 9 can be sequentially arranged and connected along the length direction thereof, so that convenience is provided for the integrated packaging of the functional power device with multiple chips, and multiple pins are optionally arranged and combined for a packaging factory.
The utility model has the advantages that: 1. the packaging form is changed from a direct insertion type to a surface mounting form through the lead frame, and the automatic requirement of automatic surface mounting of the PCB is met. 2. Meanwhile, the installation space of the radiating fin is saved, and the area of the pin welding line area can be made to be different according to the current. 3. The adoption of the non-porous chip substrate provides possibility of space position for the welding of a large chip. 4. The appearance and the radiating fin are combined in a laminating mode, the surface of a device is not stressed greatly and is uniform, and no influence is caused on an internal chip. Meanwhile, a grid test end is added, so that the detection is convenient.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in the embodiments without departing from the principles and spirit of the invention, and the scope of the invention is to be accorded the full scope of the claims.
Claims (9)
1. A novel packaging structure of a power device is characterized by comprising:
the LED chip comprises a substrate, wherein a metal heat dissipation plate is arranged on the upper end face of the substrate, a chip is arranged on the lower end face of the substrate, a plurality of first pins connected with the substrate are arranged on one side of the substrate, second pins, third pins and a plurality of fourth pins which are arranged at intervals with the substrate are arranged on the other side of the substrate, and the second pins, the third pins and the fourth pins are connected with the chip through inner leads;
the lead frame is attached and connected with the first lead, the second lead, the third lead and the fourth lead correspondingly;
and the plastic package body is used for packaging and integrally forming the substrate, the metal radiating fin, the chip, the first pin, the second pin, the third pin, the fourth pin and the pin frame, wherein the upper end surface of the metal radiating fin and the upper end surface of the plastic package body are positioned on the same end surface.
2. The packaging structure of the novel power device as claimed in claim 1, wherein the substrate is a silicon substrate.
3. The package structure of a novel power device according to claim 1, wherein the metal heat dissipation plate is a copper heat dissipation plate.
4. The package structure of the novel power device as claimed in claim 1, wherein the number of the first leads is not less than three, and the first leads are drains.
5. The packaging structure of the novel power device as claimed in claim 4, wherein the second lead is a gate.
6. The package structure of the novel power device as claimed in claim 5, wherein the third pin is a source test terminal.
7. The package structure of the novel power device as claimed in claim 6, wherein the fourth pin is an integral pin, and the number of the fourth pin is not less than three.
8. The packaging structure of the novel power device as claimed in claim 1, wherein the plastic package body is made of an epoxy resin material.
9. The package structure of a novel power device as claimed in claim 1, wherein the lead frames are sequentially connected along their length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921707566.2U CN210516706U (en) | 2019-10-12 | 2019-10-12 | Novel packaging structure of power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921707566.2U CN210516706U (en) | 2019-10-12 | 2019-10-12 | Novel packaging structure of power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210516706U true CN210516706U (en) | 2020-05-12 |
Family
ID=70573025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921707566.2U Active CN210516706U (en) | 2019-10-12 | 2019-10-12 | Novel packaging structure of power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210516706U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112235935A (en) * | 2020-10-28 | 2021-01-15 | 江苏贺鸿智能科技有限公司 | PCB component and manufacturing method thereof |
| CN118053822A (en) * | 2024-04-16 | 2024-05-17 | 四川职业技术学院 | Packaging structure and packaging method of power management chip |
-
2019
- 2019-10-12 CN CN201921707566.2U patent/CN210516706U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112235935A (en) * | 2020-10-28 | 2021-01-15 | 江苏贺鸿智能科技有限公司 | PCB component and manufacturing method thereof |
| CN112235935B (en) * | 2020-10-28 | 2023-07-21 | 江苏贺鸿智能科技有限公司 | PCB component and manufacturing method thereof |
| CN118053822A (en) * | 2024-04-16 | 2024-05-17 | 四川职业技术学院 | Packaging structure and packaging method of power management chip |
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| GR01 | Patent grant |