CN217718469U - JTAG communication circuit, board card and electronic equipment - Google Patents

Abstract

The disclosure relates to the technical field of computer communication, and particularly provides a JTAG communication circuit, a board card and electronic equipment. A JTAG communications circuit, comprising: a JTAG terminal; the JTAG terminal is sequentially connected with each component to be tested in series to form a JTAG communication link; each component to be tested comprises a device to be tested and a channel switching circuit, the channel switching circuit comprises a first input end, a second input end and a first output end, the first input end is connected with the input end of the device to be tested, the second input end is connected with the output end of the device to be tested, and the first input end and the second input end are switched and communicated with the first output end in a controlled manner. According to the embodiment of the disclosure, JTAG communication of all devices to be tested on the board card is realized, and testability and diagnosability of the board card are improved.

Description

JTAG communication circuit, board card and electronic equipment

Technical Field

The disclosure relates to the technical field of computer communication, in particular to a JTAG communication circuit, a board card and electronic equipment.

Background

JTAG (Joint Test Action Group) is a common name of standard 1149.1 of IEEE, which is a standard Test protocol, i.e. a standard access port and a boundary scan structure, and is a high-level Test technology developed recently. Through the JTAG signal, a plurality of functional tests and diagnoses such as interconnection test, program loading, online debugging, circuit sampling and the like of the device can be realized.

In the related art, part of the board cards do not support the JTAG function, and part of the board cards support the JTAG function, but only can perform JTAG connection on a single device on the board card, and if the board cards include a plurality of chips and other devices, the JTAG connection on the plurality of devices cannot be supported, so that the testability and diagnosability of the board card devices are greatly reduced.

Disclosure of Invention

In order to improve the JTAG communication capability of each device on the board card, the embodiments of the present disclosure provide a JTAG communication circuit and a board card having the circuit.

In a first aspect, an embodiment of the present disclosure provides a JTAG communication circuit, including:

a JTAG terminal; and

the JTAG terminal is sequentially connected with each component to be tested in series to form a JTAG communication link;

wherein, every subassembly that awaits measuring includes device and the channel switching circuit that awaits measuring, and the channel switching circuit includes first input, second input and first output, first input with the input of device that awaits measuring is connected, the second input with the output of device that awaits measuring is connected, and, first input with the second input control ground with first output switches the intercommunication.

In some embodiments, the JTAG terminal includes a TDI terminal and a TDO terminal, and the TDI terminal is connected to the TDO terminal after being connected in series with each component to be tested in sequence, so as to form the JTAG communication link.

In some embodiments, the control circuit further includes a plurality of second output terminals, each second output terminal is connected to the control terminal of one of the channel switching circuits, the control circuit is configured to output a control signal, and the channel switching circuit controls the first input terminal and the second input terminal to be in switching communication with the first output terminal according to the control signal.

In some embodiments, the system bus terminal is connected to an input end of the control circuit, and the control circuit generates the control signal corresponding to each second output end according to an input signal sent by the system bus terminal.

In some embodiments, the JTAG terminal includes a TMS terminal, a TCK terminal, and a TRST terminal, the TMS terminal is connected to each device under test, the TCK terminal is connected to each device under test, and the TRST terminal is connected to each device under test.

In some embodiments, the TMS terminal is connected to each device under test through a first buffer circuit, the TCK terminal is connected to each device under test through a second buffer circuit, and the TRST terminal is connected to each device under test through a third buffer circuit.

In some embodiments, the device under test comprises at least one of:

CPU chip, MCU chip, BMC chip, SWITCH chip.

In some embodiments, the channel switching circuit includes a switch chip circuit or a programmable control chip circuit.

In a second aspect, an embodiment of the present disclosure provides a board card, including:

the golden finger is used for being connected with an external card slot in a pluggable mode, and comprises a plurality of connecting terminals, and the plurality of connecting terminals comprise JTAG terminals; and

the JTAG communication circuit comprises at least two assemblies to be tested, and the at least two assemblies to be tested and the JTAG terminal are in communication connection through the JTAG communication circuit in any implementation mode of the first aspect.

In some embodiments, the board comprises a PCIe board.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: the board card according to the second aspect and any embodiment thereof.

The JTAG communication circuit of the embodiment of the disclosure comprises a JTAG terminal and at least two assemblies to be tested, wherein the JTAG terminal is sequentially connected with each assembly to be tested in series to form a JTAG communication link, each assembly to be tested comprises a device to be tested and a channel switching circuit, the channel switching circuit comprises a first input end, a second input end and a first output end, the first output end is connected with the input end of the device to be tested, the second input end is connected with the output end of the device to be tested, and the first input end and the second input end are switched and communicated with the first output end in a controlled manner. According to the embodiment of the disclosure, JTAG communication of all devices to be tested on the board card can be realized without changing the existing golden finger structure, and the testability and diagnosability of the board card are improved. In addition, any one or more devices to be tested can be mounted on the JTAG link by utilizing the channel switching circuit, so that the devices to be tested can be detected in a targeted manner, and the online analysis capability of the board card is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a JTAG communication circuit and a board card according to some embodiments of the present disclosure.

Fig. 2 is a schematic diagram of a JTAG communication circuit and board card structure according to some embodiments of the present disclosure.

Fig. 3 is a schematic diagram of a JTAG communication circuit and a board card according to some embodiments of the present disclosure.

Fig. 4 is a schematic diagram of a JTAG communication circuit and a board card according to some embodiments of the present disclosure.

Fig. 5 is a schematic diagram of a JTAG communication circuit and a board card according to some embodiments of the present disclosure.

FIG. 6 is a schematic diagram of JTAG communication circuits and board structures according to some embodiments of the present disclosure.

Detailed Description

The technical solutions of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. In addition, technical features involved in different embodiments of the present disclosure described below may be combined with each other as long as they do not conflict with each other.

JTAG (Joint Test Action Group) is a common name of standard 1149.1 of IEEE, which is a standard Test protocol, i.e. a standard access port and a boundary scan structure, and is a high-level Test technology developed recently.

In the field of hardware communication, the JTAG signal has the following applications: 1) Interconnection test, judging whether the interconnection line of the device has open circuit, short circuit or logic fault, etc.; 2) Program loading of the programmable device; 3) Online debugging of the programmable device; 4) And (4) circuit sampling, namely sampling the pin state of the chip. Therefore, the JTAG signal can realize a plurality of functional tests and diagnoses of devices on the board cards such as the chip.

However, at present, JTAG signals are optional signals and are not mandatory signals, so most cards do not support JTAG interface circuits. Although some boards have JTAG interfaces, they can only be connected to one board device, and if the board includes multiple chip devices, they can only be JTAG connected to one of the chips.

For example, taking a PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) board as an example, the server may insert the PCIe board into a PCIe card slot of the server through a PCIe bus interface to perform data interaction, so as to implement function expansion of the server.

In the related technology, part of the PCIe boards do not support the JTAG interface, and the other part of the PCIe boards support the JTAG interface, but only one JTAG interface is provided on the gold finger of the PCIe board, so that only one device of the PCIe board can be provided with a JTAG communication function, and the other devices still cannot implement JTAG test and debugging, which greatly reduces testability and diagnosability of the PCIe board.

Based on the above defects, the embodiments of the present disclosure provide a JTAG communication circuit and a board card having the communication circuit, which are intended to implement JTAG functions of multiple devices on the board card, and implement JTAG signal gating on any one or multiple devices, thereby improving testability and diagnosability of the board card.

In a first aspect, the embodiments of the present disclosure provide a JTAG communication circuit, which may be used in a board, and through the JTAG communication circuit of the embodiments of the present disclosure, a JTAG communication function of each device on the board may be implemented.

In some embodiments, the JTAG communication circuit of examples of the present disclosure includes a JTAG terminal and at least two components under test.

The JTAG terminal refers to a port of the card for JTAG communication with an external card. For example, in an example, the PCIe board is taken as an example, the PCIe board has a PCIe gold finger, a plurality of communication ports are soldered on the gold finger, and the PCIe gold finger is connected to a PCIe slot reserved on the server motherboard in a pluggable manner, so that communication between the PCIe board and the server motherboard is implemented. The plurality of communication ports in the PCIe fingers include a part of JTAG related ports, which are the JTAG terminals in the present disclosure.

The JTAG lines mainly include TDI, TDO, TMS, TCK, and TRST signal lines, and thus, the JTAG terminals may also include a TDI terminal, a TDO terminal TMS terminal, a TCK terminal, and a TRST terminal. That is, in the above example, of the gold fingers of the PCIe card, the JTAG-related communication ports may include a TDI terminal, a TDO terminal, a TMS terminal, a TCK terminal, and a TRST terminal.

It is understood that in the JTAG communication line, TDI (Test Data Input) is a Data Input signal line, all Data to be Input to a specific register is Input in series by one bit through the TDI interface, and TDI is mandatory in the IEEE1149.1 standard. TDO (Test Data Output) is a Data Output signal line, and all Data Output from a specific register is Output in series one bit by one bit through a TDO interface, which is mandatory in the IEEE1149.1 standard. TMS (Test Mode Selection Input) is a signal line used to control the transitions of the TAP state machine, the TMS signal is valid on the rising edge of TCK, which is mandatory in the IEEE1149.1 standard. The TCK (Test Clock Input) provides an independent, basic Clock signal by which all operations of the TAP are driven for operation of the TAP state machine, which is mandatory in the IEEE1149.1 standard. TRST (Test Reset Input) can be used to Reset (initialize) the TAP Controller, which is optional in the IEEE1149.1 standard, since the TAP Controller can also be Reset (initialized) by TMS.

In the embodiment of the disclosure, the JTAG communication circuit comprises at least two components to be tested, and the JTAG terminals are sequentially connected in series with the components to be tested to form a JTAG communication link. For example, in one example, the board card is provided with 3 components to be tested, a TDI terminal of the JTAG terminal is connected to an input terminal of a first component to be tested, an output terminal of the first component to be tested is connected to an input terminal of a second component to be tested, an output terminal of the second component to be tested is connected to an input terminal of a third component to be tested, and an output terminal of the third component to be tested is connected to a TDO terminal of the JTAG terminal, so that a complete JTAG communication link is formed.

In the embodiment of the disclosure, each component to be tested comprises a device to be tested and a channel switching circuit. Still taking the PCIe board as an example, as the integrated functions of the PCIe board are more and more, the devices such as chips on the PCIe board are more and more, and these devices that need to perform JTAG communication are the devices to be tested in the present disclosure.

In the embodiment of the disclosure, a channel switching circuit is correspondingly arranged for each device to be tested, and the channel switching circuit includes a first input end, a second input end and a first output end. The first input end and the second input end can be controlled to be in switching connection with the first output end, namely, when the first input end is communicated with the first output end, the second input end is disconnected with the first output end; on the contrary, when the second input end is communicated with the first output end, the first input end is disconnected with the first output end.

The first input end of the channel switching circuit is connected with the input end of the device to be tested corresponding to the channel switching circuit, and the second input end of the channel switching circuit is connected with the output end of the device to be tested corresponding to the channel switching circuit. Therefore, when a certain device to be tested needs to be mounted on the JTAG communication link, only the second input end of the control channel switching circuit needs to be communicated with the first output end, and JTAG signals can flow through the device to be tested. On the contrary, when the device to be tested needs to be isolated outside the JTAG communication link, only the first input end and the first output end of the channel switching circuit need to be controlled to be communicated, JTAG signals can directly flow from the channel switching circuit and do not flow through the device to be tested any more.

Based on the principle, for a plurality of devices to be tested included on the board card, JTAG signal communication of all the devices to be tested can be realized by using one JTAG terminal, that is, JTAG functions of the devices to be tested on the board card can be realized without changing the existing physical interface of the board card. In addition, the channel switching circuit can be used for controlling the required device to be tested to be mounted on the JTAG communication link, so that the test and diagnosis of one or more devices to be tested are pertinently realized, and the testability and the diagnosability of the board card are greatly improved.

In order to make the JTAG communication circuit structure and principle of the present disclosure more clearly understood, the circuit structure shown in fig. 1 is taken as an example for the following description.

As shown in fig. 1, in this example, the board 100 includes 4 devices under test, which are the device under test 210, the device under test 310, the device under test 410, and the device under test 510.

The board card 100 includes a gold finger 110, the gold finger 110 is used for being connected with a response card slot on an external board card in a plugging manner, and a plurality of connection terminals are soldered on the gold finger 110. When the gold finger 110 is inserted into the card slot, each connection terminal on the gold finger 110 can establish communication connection with an external board.

For example, in an example, the board 100 is an PCIe board, a PCIe slot is reserved on the server motherboard, and a gold finger of the PCIe board can be inserted into the PCIe slot on the server motherboard, so that the PCIe board is used to expand the server function.

In the embodiment of the present disclosure, since only JTAG communication of a device to be tested is involved, only a TDI terminal and a TDO terminal related to JTAG are shown in the gold finger 110 in fig. 1, and for other connection terminals included on the gold finger, a person skilled in the art can understand and implement the connection terminals according to related technologies, and details of the present disclosure are omitted.

With continued reference to fig. 1, in the disclosed example, one channel switching circuit is provided for each device under test. Specifically, the device under test 210 is connected to the channel switching circuit 220, the device under test 310 is connected to the channel switching circuit 320, the device under test 410 is connected to the channel switching circuit 420, and the device under test 510 is connected to the channel switching circuit 520. The device under test described in this disclosure includes a device under test and a channel switching circuit corresponding thereto, for example, the device under test 210 and the channel switching circuit 220 are a device under test.

In the embodiment shown in fig. 1, the input terminals of the devices under test are denoted by TDI, and the output terminals of the devices under test are denoted by TDO. The circuit structure and the principle of the embodiments of the present disclosure will be described below by taking the device under test 210 and the channel switching circuit 220 as examples.

As shown in fig. 1, an input end of the device under test 210 is connected to the TDI terminal on the gold finger 110, meanwhile, a first input end a of the channel switching circuit 220 is also connected to the TDI terminal on the gold finger 110, an output end of the device under test 210 is connected to a second input end B of the channel switching circuit 220, and a first output end C of the channel switching circuit 220 is connected to a next component under test.

For the channel switching circuit 220, the first input terminal a and the second input terminal B thereof can be controllably switched to communicate with the first output terminal C. Referring to the circuit shown in fig. 1, when the first input terminal a is connected to the first output terminal C, the TDI terminal on the gold finger 110 will be directly connected to the first input terminal a and the first output terminal C, that is, the device under test 210 will be isolated outside the JTAG link due to the disconnection of the second input terminal B from the first output terminal C. On the contrary, when the second input terminal B is connected to the first output terminal C, due to the disconnection between the first input terminal a and the first output terminal C, the JTAG signal on the gold finger 110 will flow through the device under test 210, and then flow out from the first output terminal C through the second input terminal B, that is, the device under test 210 will be mounted on the JTAG link.

The above description only takes the device under test 210 and the channel switching circuit 220 as examples, and the same principle applies to other components under test, for example, by controlling the switching conduction of the channel switching circuit 320, the device under test 310 can be isolated outside the JTAG link or mounted on the JTAG link, and details of the disclosure are not repeated.

Therefore, in the embodiment of the present disclosure, JTAG signal communication of all devices to be tested can be realized by using the JTAG terminals on the gold fingers 110 of the board card 100, so that JTAG communication of multiple devices to be tested on the board card can be realized without changing the existing gold finger structure, and testability and diagnosability of the board card are improved. In addition, any one or more devices to be tested can be mounted on the JTAG link by utilizing the channel switching circuit, so that the devices to be tested can be detected in a targeted manner, and the online analysis capability of the board card is further improved.

In some embodiments of the present disclosure, the control circuit may be utilized to control the switching on of each channel switching circuit, which is described below in conjunction with the embodiment of fig. 2.

As shown in fig. 2, in some embodiments, the board 100 further includes a control circuit 600, and an input terminal of the control circuit 600 is connected to a system bus terminal (SMBUS) on the gold finger 110. The SMBUS (System Management Bus) is a control Bus provided by the System and the power Management task, and in the embodiment of the present disclosure, the control circuit 600 may receive an input signal of the System through the SMBUS Bus and generate a control signal according to the input signal.

The control circuit 600 includes a plurality of second output terminals, and the number of the second output terminals may be the same as the number of the channel switching circuits in the board, so that each second output terminal is connected to the control terminal of one channel switching circuit.

For example, as shown in fig. 2, the board 100 includes 4 channel switching circuits, so that the control circuit 600 also includes 4 second output terminals, i.e., a second output terminal E1, a second output terminal E2, a second output terminal E3, and a second output terminal E4. Specifically, the second output terminal E1 is connected to the control terminal D of the channel switching circuit 220, the second output terminal E2 is connected to the control terminal D of the channel switching circuit 320, the second output terminal E3 is connected to the control terminal D of the channel switching circuit 420, and the second output terminal E4 is connected to the control terminal D of the channel switching circuit 520.

In the embodiment of the present disclosure, the control circuit 600 receives an input signal sent by the system through the SMBUS bus, and sends a control signal to the control terminal D of each channel switching circuit based on the input signal, so as to control the switching of each channel switching circuit.

In some embodiments, the control signal sent by the control circuit 600 to the control terminal D of the channel switching circuit is a high-low level signal, and when the channel switching circuit receives a high level, the second input terminal B is conducted with the first output terminal C; when the channel switching circuit receives a low level, the first input terminal a is conducted with the first output terminal C. The following table shows the corresponding JTAG link conditions for different control signals in the example of fig. 2.

Watch 1

In table one, "mount" means that the device under test is mounted in the JTAG communication link, and "isolate" means that the device under test is isolated outside the JTAG communication link.

Fig. 3 shows a signal flow diagram in which the control circuit 600 controls the device under test 210, 420 to be mounted on the JTAG communication link, while the device under test 310, 510 is isolated outside the JTAG communication link.

As shown in fig. 3, the second input terminal B of the channel switching circuit 220 is conducted with the first output terminal C, so that the device under test 210 is mounted on the JTAG communication link. The first input terminal a of the channel switching circuit 320 is conducted with the first output terminal C, so that the device under test 310 is isolated outside the JTAG communication link. The second input terminal B of the channel switching circuit 420 is conducted with the first output terminal C, so that the device under test 410 is mounted on the JTAG communication link. The first input terminal a of the channel switching circuit 520 is conducted with the first output terminal C, so that the device under test 510 is isolated outside the JTAG communication link.

As can be seen from the above, in the embodiment of the present disclosure, the control circuit 600 can be used to control any one or more devices to be tested in a targeted manner to implement the JTAG function, so as to implement the testing, optimization and online analysis of the devices to be tested, and improve the testability and diagnosability of the board card.

As can be seen from the foregoing, with regard to the JTAG communication protocol, it includes not only TDI and TDO lines but also lines such as TMS, TCK, and TRST, and therefore, the JTAG terminal on the gold finger 110 also includes a TMS terminal, a TCK terminal, and a TRST terminal.

In some embodiments, it is sufficient for the TMS terminal, the TCK terminal, and the TRST terminal to be respectively connected to each device under test, and this disclosure does not unduly limit this.

In other embodiments, in consideration of the one-to-many relationship of the terminals, that is, one connection terminal drives a plurality of lines, signal transmission may be performed through a buffer circuit in order to ensure signal stability and reliability.

The Buffer, also called a Buffer register (Buffer), is used on the bus and can perform a function of isolating the front stage from the rear stage, so that in some embodiments of the present disclosure, the communication between the connection terminal and the device under test can be realized by using a Buffer circuit (Buffer), which will be described below.

For example, as shown in fig. 4, the TMS terminal of the gold finger 110 is connected to each device under test through a first buffer circuit 710. For example, as shown in fig. 5, the TCK terminals of the gold fingers 110 are connected to each device under test through the second buffer circuit 720. For example, as shown in fig. 6, the TRST terminal of the gold finger 110 is connected to each dut through a third buffer circuit 730.

For the above examples, it is needless to say that the JTAG protocol and the buffer principle in the related art are referred to by those skilled in the art and can be understood and fully implemented, and the details of the present disclosure are not repeated.

Therefore, in the embodiment of the disclosure, the JTAG function of each device to be tested can be independently controlled through the control circuit and the channel switching circuit, so that JTAG communication of any one or more devices to be tested is realized, functions of testing, program debugging, prior analysis and the like of the device to be tested in a targeted manner are realized, and testability and diagnosability of the board card are improved.

In the embodiment of the present disclosure, the device under test may be any device suitable for implementation, for example, but not limited to, a Central Processing Unit (CPU) chip, a Micro Controller Unit (MCU) chip, a Baseboard Management Controller (BMC) chip, a SWITCH chip, and the like, and the disclosure is not limited thereto.

The control circuit 600 may be, for example, an I2C expander chip, such as a PCA9555, an MCU chip or a CPLD (Complex Programmable Logic Device) chip, and the like, which is not limited in this disclosure.

The channel switching circuit may be a single-pole double-throw or double-pole double-throw switch chip, for example, 74LVC1G3157GW, SN74LVC1G3157, or may be a switching circuit composed of two buffers and an inverter, or may be, for example, an MCU chip or a CPLD chip, and the like, which is not limited in this disclosure.

Therefore, in the embodiment of the disclosure, JTAG signal communication to all devices to be tested on the board card can be realized by using one JTAG terminal, so that JTAG communication of multiple devices to be tested on the board card can be realized without changing the existing gold finger structure, and testability and diagnosability of the board card are improved. In addition, any one or more devices to be tested can be mounted on the JTAG link by utilizing the channel switching circuit, so that the devices to be tested can be detected in a targeted manner, and the online analysis capability of the board card is further improved.

In a second aspect, the present disclosure provides a board card, where the board card includes a gold finger, the gold finger is used for being connected to an external card slot in a pluggable manner, the gold finger includes a plurality of connection terminals, and the plurality of connection terminals include a JTAG terminal.

The board card of the embodiment of the present disclosure further includes a plurality of components to be tested, and the plurality of components to be tested establish communication connection with the JTAG terminal through the communication circuit of any of the above embodiments.

For example, in some embodiments, the card in the example of the present disclosure may include a PCIe card, and of course, the card in the example of the present disclosure may also be any other card suitable for implementing JTAG functions, and is not limited to PCIe cards. For the specific circuit structure of the board card, the implementation can be realized by referring to any of the above embodiments, and this disclosure is not repeated herein.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: the board card according to the second aspect and any embodiment thereof.

Therefore, in the embodiment of the disclosure, JTAG signal communication to all devices to be tested on the board card can be realized by using one JTAG terminal, so that JTAG communication of multiple devices to be tested on the board card can be realized without changing the existing gold finger structure, and testability and diagnosability of the board card are improved. In addition, any one or more devices to be tested can be mounted on the JTAG link by utilizing the channel switching circuit, so that the devices to be tested can be detected in a targeted manner, and the online analysis capability of the board card is further improved.

It should be understood that the above embodiments are only examples for clarity of description, and are not limiting. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the present disclosure may be made without departing from the scope of the present disclosure.

Claims (10)

1. A JTAG communication circuit, comprising:

a JTAG terminal; and

the JTAG terminal is sequentially connected with each component to be tested in series to form a JTAG communication link;

each component to be tested comprises a device to be tested and a channel switching circuit, the channel switching circuit comprises a first input end, a second input end and a first output end, the first input end is connected with the input end of the device to be tested, the second input end is connected with the output end of the device to be tested, and the first input end and the second input end are controlled to be communicated with the first output end in a switching mode.

2. The JTAG communication circuit of claim 1,

the JTAG terminal comprises a TDI terminal and a TDO terminal, and the TDI terminal is connected with the TDO terminal after being sequentially connected with each component to be tested in series to form the JTAG communication link.

3. The JTAG communication circuit of claim 1,

the control circuit comprises a plurality of second output ends, each second output end is connected with the control end of one channel switching circuit, the control circuit is used for outputting a control signal, and the channel switching circuits control the first input ends and the second input ends to be communicated with the first output ends in a switching mode according to the control signal.

4. The JTAG communication circuit of claim 3,

the system bus terminal is connected with the input end of the control circuit, and the control circuit generates the control signal corresponding to each second output end according to the input signal sent by the system bus terminal.

5. The JTAG communication circuit of claim 1,

the JTAG terminal comprises a TMS terminal, a TCK terminal and a TRST terminal, the TMS terminal is connected with each device to be tested respectively, the TCK terminal is connected with each device to be tested respectively, and the TRST terminal is connected with each device to be tested respectively.

6. The JTAG communication circuit of claim 5,

the TMS terminal is connected with each device to be tested through a first buffer circuit, the TCK terminal is connected with each device to be tested through a second buffer circuit, and the TRST terminal is connected with each device to be tested through a third buffer circuit.

7. The JTAG communication circuit of claim 1,

the channel switching circuit comprises a switch chip circuit or a programmable control chip circuit.

8. A board card, comprising:

the golden finger is used for being connected with an external card slot in a pluggable mode, and comprises a plurality of connecting terminals, and the plurality of connecting terminals comprise JTAG terminals; and

at least two components under test, which establish communication connection with the JTAG terminals through the JTAG communication circuit of any one of claims 1 to 7.

9. The board card of claim 8,

the board card comprises a PCIe board card.

10. An electronic device, comprising: the board card of claim 9.

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