CN116741751A

CN116741751A - Integrated circuit unit, integrated circuit and die testing method

Info

Publication number: CN116741751A
Application number: CN202310410791.4A
Authority: CN
Inventors: 安苏曼·钱德拉; 桑迪·库马·戈埃尔
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-16
Filing date: 2023-04-17
Publication date: 2023-09-12

Abstract

Systems, methods, and apparatus for performing intra-die and inter-die testing on one or more chips of an integrated circuit are described herein. The cells of the integrated circuit include a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer signals. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output a buffered signal or signals based on whether a scan mode or a functional mode is enabled. The embodiment of the application also discloses a unit of the integrated circuit, the integrated circuit and a test method of the die.

Description

Integrated circuit unit, integrated circuit and die testing method

Technical Field

Embodiments of the application relate to a unit of an integrated circuit, and a method of testing a die.

Background

Three-dimensional (3D) stacking of semiconductor chips is becoming increasingly popular because they provide a way to package more functionality on a chip while reducing manufacturing costs. 3D Integrated Circuits (ICs) achieve this by packaging smaller heterogeneous designs in dies that are stacked together and connected by thousands of orders of magnitude of interconnects. However, the fabrication of these stacked circuits (e.g., ED-SIC) is prone to defects. Testing the integrated circuit to identify manufacturing defects and ensure proper functioning can help determine if the semiconductor chip is free of faults. While the integrity of these interconnects is important for proper chip operation, 3D IC architectures may not include a way to directly probe the internal structures.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a cell of an integrated circuit, the cell comprising: a data register configured to output a signal; an I/O pad coupled to the data register, wherein the I/O pad is configured to receive a signal and buffer the signal; and a first multiplexer coupled to the I/O pad and the data register, the first multiplexer configured to selectively output the buffered signal or the selectively output signal based on enabling the scan mode or the functional mode.

According to another aspect of an embodiment of the present application, there is provided an integrated circuit having a built-in self test (BIST) function, the integrated circuit comprising: a first die including a first unit including a first multiplexer, a first data register, and a first input/output (I/O) pad; and a second die comprising a second unit comprising a second multiplexer, a second data register, and a second I/O pad, wherein the first die is coupled to the second die via an inter-die interconnect, and wherein the first unit is configured to perform a first intra-die test in an intra-die test mode, the first intra-die test testing functions of the first multiplexer, the first data register, or the first I/O pad, and the second unit is configured to perform a second intra-die test in the intra-die test mode, the second intra-die test testing functions of the second multiplexer, the second data register, or the second I/O pad.

According to yet another aspect of an embodiment of the present application, there is provided a method of testing one or more dies using built-in self-test (BIST) functionality, the method comprising: receiving data including a predetermined test case through a data register of the die; providing a predetermined test case to the I/O pads and the multiplexer through the data register; buffering a predetermined test case through the I/O pads; and providing the buffered predetermined test case back to the data register via a loop-back path formed through the I/O pad and the multiplexer.

Drawings

The various aspects of the disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings:

FIG. 1 is a block diagram illustrating an example built-in self test (BIST) circuit with interconnected die, according to various embodiments of the present disclosure.

Fig. 2 is a block diagram of an example die in accordance with various embodiments of the present disclosure.

Fig. 3 is a block diagram of an example packaging unit with an intra-die loopback path according to various embodiments of the present disclosure.

Fig. 4 is a process flow diagram illustrating enabling a scan mode and an intra-die loopback path of the packaging unit of fig. 3, according to various embodiments of the present disclosure.

Fig. 5 is a block diagram illustrating an example intra-die loopback path within two packaging units according to various embodiments of the present disclosure.

Fig. 6 is a block diagram illustrating an example die interconnect subsystem with a packaging unit of chips and an inter-die interconnect between packaging units according to various embodiments of the present disclosure.

Fig. 7 is a block diagram illustrating an interconnect die system of two dies with inter-die interconnects according to various embodiments of the present disclosure.

Fig. 8A is a block diagram illustrating an example 3D die stack with horizontally integrated dies in accordance with various embodiments of the present disclosure.

Fig. 8B is a block diagram illustrating another example 3D die stack with vertically integrated dies, according to various embodiments of the disclosure.

Fig. 9A is a block diagram illustrating an interconnect die system having two dies according to various embodiments of the present disclosure.

Fig. 9B is a block diagram illustrating a test area of an interconnect die system in accordance with various embodiments of the present disclosure.

Fig. 10A is a table illustrating region 1 testing (including internal scan testing to test internal die logic) in accordance with various embodiments of the present disclosure.

Fig. 10B is a table of zone 2 tests according to various embodiments of the present disclosure.

Fig. 10C is a table of zone 3 tests according to various embodiments of the present disclosure.

Fig. 10D is a table illustrating area tests applied to each die in accordance with various embodiments of the present disclosure.

Fig. 11 is a table showing a test example of each of the area tests described in fig. 10A-10B according to various embodiments of the present disclosure.

Fig. 12 is a block diagram illustrating functional components of a die with BIST functionality according to various embodiments of the present disclosure.

FIG. 13 is a block diagram of an example 3D BIST controller, according to various embodiments of the present disclosure.

FIG. 14 is a block diagram illustrating an example generator in accordance with various embodiments of the disclosure.

FIG. 15 is a block diagram illustrating another example generator in accordance with various embodiments of the disclosure.

Fig. 16 is a block diagram of an example response comparator in accordance with various embodiments of the disclosure.

Fig. 17 is a block diagram illustrating an interconnected die system having two dies that undergo zone 1 testing in a scan mode, in accordance with various embodiments of the present disclosure.

Fig. 18 is a block diagram illustrating an interconnect die system having two dies undergoing zone 2 testing in accordance with various embodiments of the present disclosure.

Fig. 19 is a process flow diagram illustrating testing and debugging a 3D IC according to various embodiments of the present disclosure.

Fig. 20 is a flow chart illustrating a method of testing die functionality using a loopback path in accordance with various embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

Semiconductor wafers are manufactured with a large number of Integrated Circuits (ICs). Semiconductor wafers are diced or cut into smaller chips, called die. Each die is a small module containing an Integrated Circuit (IC). Each IC performs a specific electrical function. Multiple dies may be interconnected together by a stack to produce a semiconductor chip that can perform multiple functions. This is referred to as a 3D chip stack or a 3D stack of ICs (e.g., 3D-SIC).

In a 3D chip stack, two or more dies may be interconnected to facilitate the transmission of electrical signals. These are referred to as inter-die interconnects. In other words, the inter-die interconnect carries interconnect signals between two or more dies. A 3D SIC may contain thousands of interconnects. The inter-die interconnect fabrication process, as well as the die bonding process, are complex and prone to defects that affect the electrical operation of the IC, such as electrical opens, shorts, delay defects, or resistance problems. Common static fault models for interconnects are hard opens and shorts. The tests can be performed by static Direct Current (DC) using a wrapper.

The devices and methods described herein relate to built-in self test (BIST) architecture using a packaging unit input/output (I/O) loop-back path that can quickly and reliably test, troubleshoot, and diagnose chip interface problems, as well as inter-die interconnect problems in 3D ICs. The BIST engine described herein provides a mechanism for obtaining local and/or global fault data using a local counter. The predefined sequence and on-chip feature comparators are used to detect faults and identify various types of defects or faults. More specifically, the BIST architecture described herein provides a mechanism to test each of thousands of interconnects individually. Different pattern types may be run to help isolate the root cause of a fault within an IC.

FIG. 1 is a block diagram of an example built-in self test (BIST) circuit 100 with interconnect dies 110, 120 in accordance with various embodiments of the present disclosure. Built-in self-test circuit 100 includes dies 110, 120 interconnected together by inter-die interconnects 132, 134, respectively. For example, the inter-die interconnects 132, 134 may represent logic-to-logic, logic-to-memory, or memory-to-memory inter-die interconnects. More specifically, each die includes any number of unidirectional Transmit (TX) packaging units, unidirectional Receive (RX) packaging units, bidirectional (TX/RX) packaging units, and integrated circuits in a core including, for example, functional logic or memory. For example, die 110 includes TX packaging unit 112 (unidirectional), RX packaging unit 114 (unidirectional), TX/RX packaging unit 116 (bidirectional), and core 118.TX wrapper unit 112, RX wrapper unit 114, and TX/RX wrapper unit 116 are referred to as chains 130. Similarly, die 120 includes RX packaging unit 122 (unidirectional), TX packaging unit 124 (unidirectional), TX/RX packaging unit 126 (bidirectional), and core 128.RX packaging unit 122, TX packaging unit 124, and TX/RX packaging unit 126 are referred to as chains 140. TX wrapper unit 112 of die 110 is interconnected with RX wrapper unit 122 of die 120 by functional routing (e.g., inter-die interconnect 132). Likewise, RX packaging unit 114 of die 110 is interconnected with TX packaging unit 124 of die 120 by functional wiring (e.g., inter-die interconnect 134). Each packaging unit 112, 114, 122, 124 facilitates testing, troubleshooting, and diagnostics of unidirectional pads within each unit on the path from the unit to the die interface as part of the on-die testing. Further, the bidirectional pads of the bidirectional packaging unit may be tested at the die level itself using a loopback test.

Fig. 2 is a block diagram of an example die 200, according to various embodiments of the disclosure. Die 200 includes unidirectional TX packaging units 202, 204, unidirectional RX packaging units 206, 208, functional logic 210, and bidirectional packaging unit 220. The bi-directional wrapper unit 220 includes a TX wrapper unit 222 and an RX wrapper unit 224. Unidirectional pads on the path from the cell to the die interface may be tested as part of an intra-die test.

Fig. 3 is a block diagram of an example packaging unit 300 having an intra-die loopback path according to various embodiments of the present disclosure. For example, packaging unit 300 is a TX packaging unit of a die (e.g., die 110, die 120, or die 200). The packaging unit 300 includes logic gates 302, multiplexers 304, 306, 308, a data register 310, and input/output (I/O) PADs (PADs) 312. The packaging unit 300 provides hold, switch, and I/O packaging functions. For example, the logic gate 302 receives a switching (TG) signal and a Loopback (LB) signal output by the multiplexer 308. The switching signal TG determines whether to switch or maintain the data in the packing unit 300. When the switching signal TG is logic high (e.g., "1"), the packing unit 300 is in a data maintaining state. When the switching (TG) signal is logic low (e.g., "0"), the packing unit 300 is in a data switching state. When the switch (TG) signal and the loop-back (LB) signal are opposite to each other (e.g., one is a logic high "1" and the other is a logic low "0"), the output of the logic gate 302 is a logic high (e.g., "1"). When the switch (TG) signal and the loop-back (LB) signal are the same (e.g., both logic high "1" or both logic low "0"), the output of logic gate 302 is logic low (e.g., "0"). For example, logic gate 302 is described as an XOR (exclusive or) gate, but it is understood that logic gate 302 may be any combination of logic gates that implement the same logic function.

The output of logic gate 302 is coupled to the input of multiplexer 304. Multiplexer 304 also receives an input (TI) signal. The multiplexer 304 is controlled by a control (c 1) signal. When the control (c 1) signal is logic low (e.g., "0"), the multiplexer 304 scans for signals (e.g., a switching (TG) signal) received by the packing unit 300. In other words, the multiplexer 304 outputs a switching (TG) signal. When the control (c 1) signal is a logic high (e.g., "1"), multiplexer 304 loops back the signal output by data register 310 or I/O pad 312. In other words, multiplexer 304 outputs the output of logic gate 302.

The output of multiplexer 304 is coupled to the input of multiplexer 306. Multiplexer 306 also receives a Functional Input (FI) signal. The multiplexer 306 determines whether the packaging unit 300 is in functional mode or scan mode. Multiplexer 306 is controlled by a control (c 0) signal. When the control (c 0) signal is logic low (e.g., "0"), the multiplexer 306 is in the functional mode and outputs a Functional Input (FI) signal. When the select signal is a logic high (e.g., "1"), multiplexer 306 is in scan mode and outputs the output of multiplexer 304.

The output of multiplexer 306 is coupled to a data register 310, which data register 310 may be, for example, a flip-flop. The data register 310 also receives a Clock (CLK) signal. The function or switch output (FO/TO) signal of the data register 310 is looped back as an input TO the multiplexer 308. A function or switch output (FO/TO) signal is also provided TO I/O pad 312 in response TO packaging unit 300 being in scan mode. The I/O pad 312 is a bi-directional pad cell that includes buffers 314, 316. The logic symbol buffer 314 based on the input enable (ie) signal facilitates signal flow from the input. The output enable (oe) signal based logic symbol buffer 316 facilitates signal stream output. I/O pads 312 are intermediate structures that connect signals from cores (e.g., cores 118, 128, functional logic 210) to external pins (not shown in fig. 3) of the die. The output of buffer 314 is coupled to the input of multiplexer 308. Multiplexer 308 provides a Loop Back (LB) signal to logic gate 302 based on the control (c 2) signal. When the control (c 2) signal is a logic low (e.g., "0"), the Loopback (LB) signal output by multiplexer 308 is a functional or switch output (FO/TO) signal from data register 310. When the control (c 2) signal is logic high (e.g., "1"). The Loopback (LB) signal output by multiplexer 308 is the input (I) signal provided by buffer 314 of I/O pad 312.

Packaging unit 300 includes an on-die loopback path through I/O pad 312 and multiplexer 308. The on-die loopback path directs a test case (e.g., a function or switch output (FO/TO) signal) back TO the data register 310 through multiplexer 318.

Fig. 4 is a process flow diagram 400 illustrating the scan mode and the enabling of the on-die loopback path of packaging unit 300 in fig. 3, according to various embodiments of the present disclosure. At step 402, the packaging unit 300 is brought into a scanning mode by setting the control (c 0) signal to a logic high (e.g., "1") and by setting the control signal (c 1) to a logic low (e.g., "0"). At step 404, with the control (c 1) signal at a logic low (e.g., "0"), the multiplexer 304 outputs an input (TI) signal. With control (c 0) set to a logic high (e.g., "1"), the Input (TI) signal is then output by multiplexer 306. Then, at step 406, the input (T1) signal is loaded into the data register 310. At step 408, the switch (TG) signal is set to a logic low (e.g., "0") and the control (c 2) signal is set to a logic high (e.g., "1"). At step 410, based on the control (c 2) signal set to logic high (e.g., "1"), multiplexer 308 outputs a Loopback (LB) signal that is an input (I) signal from buffer 314 of I/O pad 312. At step 412, the input (I) signal is enabled by setting the input enable (ie) signal of buffer 314 and the output enable (oe) signal of buffer 316 to logic high (e.g., "1"). This allows signals to flow through the I/O pads 312. At step 414, data from the data register 310 may be captured because the loopback path is enabled. In other words, the signal flow is as follows: q from the output of data register 310 is provided to the O input of buffer 316, P from the output of buffer 316 is provided to buffer 314, buffer 314 outputs I to multiplexer 308, multiplexer 3008 outputs I to logic gate 302, logic gate 302 outputs a logic low (e.g., "0") to multiplexer 304 as the switch (TG) signal is different from I, multiplexer 304 outputs an input (TI) signal based on the control (c 1) signal set to logic low (e.g., "0") and multiplexer 306 outputs The Input (TI) signal to data pin (D) of data register 310.

Fig. 5 is a block diagram illustrating an example on-die loopback path within two packaging units 300, 500 according to various embodiments of the present disclosure. As shown, each packaging unit 300, 500 has its own on-die return path. For example, packaging unit 300 is a TX packaging unit and packaging unit 500 is an RX packaging unit. Packaging unit 500 contains the same components and functions for its on-die return path as packaging unit 300 described in fig. 3-4. Packaging units 300, 500 may be the same die (e.g., die 110, die 120, or die 200), such as TX packaging unit 202 and RX packaging unit 206, respectively, or TX packaging unit 222 and RX packaging unit 224, respectively, of bi-directional packaging unit 220. Alternatively, the packaging units 300, 500 may be different dies (e.g., one of die 110, die 120, or die 200, and another of die 110, die 120, or die 200).

Fig. 6 is a block diagram illustrating an example die interconnect subsystem 600 between a packaging unit 300 of a die 610 and a packaging unit 500 of a die 620, according to various embodiments of the disclosure. For example, packaging unit 300 of die 610 and packaging unit 500 of die 620 may correspond to TX packaging unit 112 of die 110 and RX packaging unit 122 of die 120, respectively. The packaging units 300, 500 are interconnected by inter-die interconnects 630 (e.g., inter-die interconnects 132, 134). The components and functions of the return path of each of the packaging units 300, 500 are shown in fig. 3-4. The difference between the die interconnect subsystem 600 and the intra-die loopback path described in fig. 3-4 is that the output (P) signal from buffer 316 of die 610 is provided to input (I) of buffer 314 of die 620. The output of buffer 314 of die 620 is then provided as the input (FI) signal of multiplexer 306.

Fig. 7 is a block diagram of an interconnect die system 700 having two dies 740, 750 and an inter-die interconnect according to various embodiments of the present disclosure. The interconnect die system 700 includes die interconnect subsystems 600, 710. The die interconnect subsystem 710 is similar in function and assembly to the die interconnect subsystem 600 except that each I/O pad has a single buffer instead of two. For example, the I/O pads 720 of the die 740 include buffers 722. Similarly, the I/O pads 730 of the die 750 include buffers 732. Buffer 720 provides an output (I) signal that is provided to multiplexer 308 of die 740. The same output (I) signal is coupled to the output (I) of buffer 732. The output (I) is provided to the multiplexer 308 of the die 750.

Fig. 8A is a block diagram of an example 3D die stack 800 with horizontally integrated dies in accordance with various embodiments of the present disclosure. The 3D die stack 800 includes a plurality of dies (e.g., chips or ICs) 802, 804, 806 coupled to a substrate 810, which are electrically interconnected by I/O pads (not shown), as shown in fig. 6-7 and operating as shown in fig. 3-4 and 6-8B. For example, interposer 808 may serve as an electrical interface between dies 802, 804, 806 through, for example, functional routing in interposer 808. In another example, fig. 8B is a block diagram of another example 3D die stack 850 with vertically integrated dies, according to various embodiments of the disclosure. For example, the 3D die stack 850 includes a plurality of chips (e.g., dies or ICs) 852, 854, 856 coupled to a substrate 858, the dies being electrically interconnected by I/O pads (not shown), as shown in fig. 6-7 and operating as shown in fig. 3-4 and 6-8B. In the context of the present disclosure, functional wiring is wiring, such as metal interconnects, which are part of the stacked functional design and are not added specifically for testing purposes.

Using the structures described in fig. 1-8B, the die may be scanned and tested. Fig. 9A-9B are block diagrams illustrating areas of a die undergoing testing according to various embodiments of the present disclosure. More specifically, fig. 9A is a block diagram illustrating an interconnect die system 900 having two dies 910, 920 according to various embodiments of the disclosure. Die 910 includes TX packaging units 912, 914 and RX packaging unit 916. Die 920 includes TX packaging unit 922 and RX packaging units 924, 926.TX wrapper unit 912 is interconnected with RX wrapper unit 922. TX wrapper unit 914 is interconnected with RX wrapper unit 924. RX packaging unit 916 is interconnected with TX packaging unit 926. Fig. 9B is a block diagram illustrating a test area of an interconnected die system 900 according to various embodiments of the present disclosure. Region 1 represents an internal die test that tests the die internal logic of dies 910 of TX packaging units 912, 914 and RX packaging units. Region 2 represents die-level testing of the interface between die 910 and die 920. Although region 1 is shown with respect to die 910, it is understood that the region may be internal to any die, including die 920. The I/O pads associated with TX wrapper unit 912 are used for the test interface. Region 3 represents stack level testing of the interconnect between die 910 and die 920 using the loop-back path depicted in fig. 6. The region 1 and region 2 tests may be used to confirm a Known Good Die (KGD) signal flow. The zone 3 test may be used to confirm Known Good Stack (KGS) signal flow.

Fig. 10A-10D are a series of tables showing various tests for each of the regions depicted in fig. 9B. For example, fig. 10A illustrates a table 1000 of region 1 tests performed in accordance with various embodiments of the present disclosure, including an internal scan test 1002 that tests internal die logic. FIG. 11 details a particular test case sequence for each test in the region.

Fig. 10B illustrates a table 1010 of zone 2 tests performed in accordance with various embodiments of the present disclosure. Zone 2 tests include a chain test 1012, a Direct Current (DC) test 1014, an Alternating Current (AC) test 1016, and a leakage test 1018. Chain test 1012 tests the chain shifting of the circuits within the die. DC test 1014 tests for shorts and/or opens of circuitry within the die. AC test 1016 tests for timing failures of the circuits within the die. Leakage test 1018 tests for unit leakage faults within the die.

Fig. 10C illustrates a table 1020 of zone 3 tests performed in accordance with various embodiments of the present disclosure. Zone 3 tests include chain test 1022, dc test 1024, ac test 1026, bridge test 1028, and burn-in test 1029. Chain test 1022 tests the chain shifting of the circuit between the two dies. DC test 1024 tests the chain shift of the circuit between the two dies. AC test 1026 tests for timing failures of the circuit between the two dies. The bridge test 1028 tests the inter-wire bridge between the two dies. Burn-in test 1029 tests for stack-level burn-in failures.

Fig. 10D illustrates a table 1030 of zone tests applied to each die 910, 920 in accordance with various embodiments of the disclosure. For example, the tests of region 1, region 2, and region 3 are applied to die 910 (e.g., all tests 1032 of die 910). The tests of region 1 and region 2 are applied to die 920 (e.g., all tests 1034 of die 920).

Fig. 11 illustrates a table 1100 of test examples for each of the region tests described in fig. 10A-10B, according to various embodiments of the present disclosure. The internal scan test 1102 uses an Automatic Test Pattern Generation (ATPG) mode to test the internal logic of the die. An internal scan test 1102 is applied to region 1. Chain test 1104 uses a chain paradigm to test the wrapping chain shift function. The chain paradigm shifts a sequence (e.g., "00110011") throughout the scan chain without running functional circuitry. Chain test 1104 is applied to region 2.DC test 1106 uses an example of all logic low (e.g., "000000 …") or all logic high (e.g., "111111 …") to test a logic signal cartridge (stuck) under short (shown by a cartridge's logic high "1") and open (shown by a cartridge's logic low "0"). DC test 1106 is applied to region 1 and region 2.AC test 1108 uses the paradigm of all logic low (e.g., "000000 …") or all logic high (e.g., "111111 …") to test transitions from logic low (e.g., "0") to logic high (e.g., "1") or from logic high (e.g., "1") to logic low (e.g., "0"). AC test 1108 uses logic gate 302 and is applied to region 1 and region 2. The leak test 1110 uses an example of alternating logic values (e.g., 0101010 … 01 or 1010101 …) to test for cell value changes due to leaks. Leak test 1110 is applied to region 1. The bridge test 1112 uses any of the following examples: 11110000, 11100001, …, 00001111 to test inter-wire bridging. Bridging test 1112 is applied to region 2. The burn-in test 1114 uses an example of alternating logic signals (e.g., 0101 … 010) to test for faults during burn-in. Burn-in test 1114 is applied to region 2. Burn-in test 1114 is run for an extended period of time to ensure die durability.

Fig. 12 is a block diagram of functional components of a die 1200 with BIST functionality according to various embodiments of the present disclosure. Die 1200 includes BIST controller 1210, example generator 1220, response compactor (compacter) 1230, chain of packaging units 1240, and core 1250 (e.g., functional logic). Each of these components is described in detail in fig. 13-16. BIST controller 1210 controls the overall test session for inter-die and/or intra-die testing. The example generator 1220 generates a predetermined sequence of test examples, such as open, short, bridge, and timing faults associated with the DC tests 1106 (e.g., DC tests 1014, 1024), AC tests 1108 (e.g., AC tests 1016, 1026), and bridge tests 1112 (e.g., bridge test 1028). The response compactor 1230 receives responses to the test cases from the packaging unit and generates data for analysis of yield and fault diagnosis. The chain 1240 of tested packaging units (e.g., the packaging units described in fig. 1-3, 5-7, and 9A) receives the test cases generated by the case generator 1220 and generates responses to the various tests described in fig. 10A-11.

FIG. 13 is an example block diagram of a 3D BIST controller 1300 (e.g., 3D BIST controller 1210) according to various embodiments of the present disclosure. The BIST controller 1300 uses initialization data (e.g., signal Enable (SE) and 3DIC_BIST_EN signals) and assists in testing the clock of an on-chip clock controller (OCC), providing scan enable for the OCC, and generating control signals for multiplexers within the packaging unit. In addition, the 3D BIST controller 1300 has scan-in and scan-out signals for testing the 3D BIST controller 1300 logic itself.

The 3D BIST controller 1300 includes multiplexers 1302, 1304, 1306, a scan enable signal generator 1310, a Finite State Machine (FSM) 1320, a clock controller 1330, a shift counter 1340, and a TX/RX enable register 1350. The multiplexers 1302, 1304, 1306 each receive a scan enable signal generated by a scan enable generator 1310, and a Scan Enable (SE) signal input to the 3D BIST controller 1300. Each multiplexer 1302, 1304, 1306 is also controlled by a 3DIC BIST enable signal (e.g., 3 dic_bist_en). Based on the logic symbols of the 3D IC BIST enable signals, the multiplexers 1302, 1304, 1036 output control signals (e.g., c0_tx, c0_rx, c1, and c 2) for multiplexers (e.g., multiplexers 304, 306, 308) of the packaging unit (e.g., packaging unit 300) and scan enable signals (e.g., se_occ) for OCC. The control signal is provided to a chain 1240 (e.g., chains 130, 140) of packaging units. The chain 1240 of packing units also receives the switching (TG) signal generated by the FSM 1320 of the 3D BIST controller 1300.

The clock controller 1330 includes a data register 1332 and a logic gate 1334. The clock controller 1330 receives an input clock (TCK/DFTClk) signal from the IC clock and a 3D IC BIST enable signal (e.g., 3dic_bist_en). The data register receives both signals and outputs data to logic gate 1334. For example, logic gate 1334 is shown as an AND gate, but any combination of logic functions that provides a similar logic function as an AND gate may be used. The clock controller 1330 generates a BIST clock signal (e.g., bist_clk) that is provided to the example generator 1220 and the response compactor 1230.

The shift counter 1340 and TX/RX enable register 1350 generate various input and output enable signals (e.g., TX only oe (single transmit output enable), TX bidi oe (dual transmit output enable), RX only ie (single receive input enable), RX bidi ie (dual receive input enable)) for I/O pads (e.g., I/O pads 312, 720, 730). These input and output enable signals are provided by the 3D BIST controller 1300 to a chain 1240 of packaging units. The 3D BIST controller 1300 also receives scan input (e.g., 3d_bist_si) and scan output (e.g., 3D-bist_so) signals for testing logic within the 3D BIST controller 1300.

FIG. 14 is a block diagram of an example generator 1400 (e.g., example generator 1220) in accordance with various embodiments of the disclosure. The example generator 1400 uses initialization data (e.g., BIST_initialization) and inputs from the BIST controller 1300 (e.g., fast_clk, shift_en) to perform its functions. These functions include setting inter-die or intra-die test modes, setting correct test communication periods, generating predefined sequences (e.g., si_occ, si_tx, si_rx) for corresponding test communication periods, and/or providing examples to data registers (e.g., data registers 310, 1332). More specifically, the example generator 1400 includes a test pattern register 1402, a test communication period Identification (ID) 1404, and an example counter 1406. The example generator generates the various examples described in table 1100 of fig. 11, such as for dc test 1106, ac test 1108, bridge test 1112, and leak test 1110. These examples are provided to chain 1240 of packaging units. The example generator 1400 also receives scan in (e.g., 3d_bist_si) and scan out (e.g., 3d_bist_so) signals for testing logic within the example generator 1400.

FIG. 15 is a block diagram of another example generator 1500 (e.g., example generators 1220, 1400) in accordance with various embodiments of the disclosure. The example generator performs the same functions, receives the same input signals, and generates the same output signals as previously described with respect to the example generator 1400 of fig. 14. The example generator 1500 includes a fault bit register 1508, a group enable register 1510, and an expected signature register 1512. Together, the fail bit register 1508, the group enable register 1510, and the expected signature register 1512 constitute the test mode register 1402 of fig. 14. The example generator 1500 also includes an error accumulator 1502 and a series of group counters 1504, 1506 that together form an example counter 1406. If the case creator 1500 fails to create a test case for any reason, a fault signal is output.

FIG. 16 is a block diagram of an example responsive compactor 1600 (e.g., responsive compactor 1330) according to various embodiments of the disclosure. Responsive compactor 1600 includes expected signature register 1602, adders 1608, 1616, logic gates 1610, 1618, 1620, counters 1606, 1614, data register 1612, and error accumulator 1604. The response compactor 1600 uses data and inputs from the BIST controller 1300 to perform its functions. These functions include collecting the failure count for each TX/RX group register in counters 1606, 1614, calculating error signatures for all TX/RX groups using error accumulator 1604, and providing failure status, and debugging each TX/RX group individually in the case of complete diagnostics. The response compactor 1600 also receives scan in (e.g., 3D_BIST_SI) and scan out (e.g., 3D-BIST_SO) signals for testing logic within the response compactor 160.

The expected signature register 1602 contains an expected signature for comparison with the response of the wrapper unit. Error accumulator 1604 counts the total number of failures for each group and collects the error signatures for all groups. This is accomplished using a combination of logic gates 1610, 1618, 1620, 1622 and adders 1608, 1616. More specifically, the adder 1608 receives a group response signal (e.g., grp_resp [0 ] provided by the group counter 1504 of the example generator 1500]). The output of adder 1608 is provided to logic gate 1610, 1610 also receives a first enable signal (e.g., en ₁ ). For example, logic gate 1610 is shown as an AND gate, but it may be any combination of logic gates that perform the same function (e.g., output a logic high when two inputs match). The output of logic gate 1610 is provided to counter 1606 (and thus to increment count) and logic gate 1618. Similarly, adder 1616 receives a group response signal (e.g., grp_resp [1 ] provided by group counter 1506 of example generator 1500]). The output of adder 1616 is provided to logic gate 1620, which logic gate 1620 also receives an enable signal (e.g., en ₂ ). For example, logic gate 1620 is shown as an AND gate, but it may be any combination of logic gates that perform the same function (e.g., output a logic high when two inputs match). The output of logic gate 1620 is provided to counter 1614 (and thereby increment count) and logic gate 1618. The logic gate 1618 compares the outputs of the logic gates 1610, 1620. For example, logic gate 1618 is shown as an OR gate, but it may be performing the same function (e.g., when the two inputs are different OR both With inputs all logic high "1" and outputs logic high). The output of logic gate 1618 is provided to error accumulator 1604.

The data register 1612 reports a test failure on the first mismatch. The data register 1612 does this based on the output of the logic gate 1622. The logic gate 1622 takes into account the output of the data register 1612 (looped back via feedback) and the output of the logic gate 1618.

Fig. 17 is a block diagram illustrating an interconnect die system 1700 having two dies 1710, 1720 for region 1 testing in a scan mode, according to various embodiments of the present disclosure. The components and functions of each die 1710, 1720 are identical to the die 1200 shown in fig. 12. With area 1 testing, the Scan In (SI) signal is provided by external Automatic Test Equipment (ATE). In the interconnect die system 1700, all TX and RX registers are stitched into a scan chain. All flip-flops in the self-test logic, signature register, counter and error accumulator are also stitched in the scan chain. Each die 1710, 1720 has its own set of scan chains and tests on its own. If the scan pattern fails, a defective chain stage can be detected. Scan tests may run in parallel or in series depending on the available scan-in and scan-out ports. The BIST controller 1210 of each die 1710, 1720 is coupled together.

Fig. 18 is a block diagram illustrating an interconnect die system 1800 having two dies 1810, 1820 undergoing region 2 testing, according to various embodiments of the present disclosure. TX/RX packaging unit interfaces 1802, 1804, 1806, 1808, 1810, 1812, 1814, 1816, 1818, 1822, 1824, 1826 of each die 1810, 1820, respectively, are tested. For region 2 testing of die 1810, 1820, the inputs of the TX and RX packaging units come from the example generator in each die. In other words, the inputs of the TX and RX packaging units of die 1810 are generated by example generator 1830. The inputs to the TX and RX packaging unit of die 1820 are generated by an example generator 1840. During the zone 2 test, the I/O pads of the packaging unit are disabled during shifting and put in loopback during capture. TX and RX scan chains receive test cases from BIST engines in the respective die. The responses captured from each TX and RX packaging unit are processed by a response compactor in each respective die.

Fig. 19 is a process flow diagram 1900 illustrating testing and debugging of a 3D IC according to various embodiments of the present disclosure. At step 1902, the BIST circuit is enabled for testing (e.g., through SE and 3DIC_BIST_EN). At step 1904, data registers 310 in each TX and RX packaging unit are configured for intra-die and/or inter-die testing based on control signals (c 0, c1, c 2). At step 1906, each TX and RX packaging unit is enabled for testing. At step 1908, one or more tests are selected from table 1100 to run on the 3D IC. At step 1910, a determination is made as to whether the test passed. If the test passes, then the test and debug ends at step 1912. However, if one or more of the tests fail, 3D IC debug begins. In one variation of debugging, at step 1914, the error signature is compared to the expected signature stored in expected signature register 1602. At step 1916, the select TX or RX wrapper unit may be identified from the error signature that does not match the expected error signature for further debugging. At step 1918, the failed TX or RX packaging unit is isolated. At step 1920, any faulty interconnects associated with those faulty TX or RX wrapper units are identified. Steps 1914, 196, 1918 and 1920 may occur simultaneously or sequentially with steps 1922, 1924. At step 1922, the group counters (e.g., group counters 1504, 1506) are analyzed. At step 1924, a chip-level interconnect fault report for yield learning is generated.

Fig. 20 is a process flow diagram 2000 illustrating a method of testing die functionality using a loopback path according to various embodiments of the present disclosure. Although fig. 20 is described herein with reference to the previously described structures for ease of understanding, it will be appreciated that the method is also applicable to many other structures. At step 2010, a data register (e.g., data register 310) of the die receives data (e.g., data D) including a predetermined test case. At step 2020, a data register (e.g., data register 310) provides a predetermined test case (e.g., FO/TO) TO the I/O pad (e.g., I/O pad 312) and the multiplexer (e.g., multiplexer 308). At step 2030, the I/O pads (e.g., I/O pads 312) buffer a predetermined test case. At step 2040, the buffered predetermined test pattern is provided back to a data register (e.g., data register 310) via a loop-back path formed by the I/O pads (e.g., I/O pad 312) and the multiplexer (e.g., multiplexer 308).

Numerous advantages may be provided using the various systems, circuits, and methods described herein. For example, the systems, circuits, and methods described herein provide the ability of 3D IC designs to be tested in a modular fashion with die interfaces and inter-die interconnects. Further, using the systems, circuits, and methods described herein, a BIST engine may be used to detect any failed transmit/receive (TX/RX) pair.

In a first embodiment, a packaging unit of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pads are coupled with the data registers. The I/O pads are configured to receive signals and buffer signals. A first multiplexer coupled to the I/O pad and the data register, the first multiplexer configured to selectively output either the buffered signal or the selectively output signal based on enabling the scan mode or the functional mode.

In some embodiments, the loopback path includes an I/O pad and a first multiplexer, the loopback path configured to direct the buffered signal back to the data register through the first multiplexer.

In some embodiments, the unit of integrated circuit further comprises: a second multiplexer coupled to an input of the data register, the second multiplexer configured to enable either the scan mode or the functional mode based on a control signal driving the second multiplexer; a third multiplexer coupled to an input of the second multiplexer, the third multiplexer configured to enable a scan-in signal or a loop-back signal to be provided to the second multiplexer; and a logic gate coupled to an input of the third multiplexer, the logic gate configured to switch or hold data provided to the data register via the second multiplexer and the third multiplexer.

In some embodiments, the control signals are generated by a plurality of multiplexers of the BIST controller.

In some embodiments, when the scan mode is enabled, the buffered signal is directed back to the data register and the signal output by the data register is a test case signal.

In some embodiments, the test case signals are provided by a case generator configured to generate the test case signals based on a particular test performed by the integrated circuit.

In some embodiments, the I/O pad includes a first buffer and a second buffer that are commonly configured to buffer signals.

In some embodiments, the I/O pad includes a buffer configured to buffer signals.

In another embodiment, an integrated circuit with BIST functionality comprises a first chip and a second chip. The first die is coupled to the second die via an inter-die interconnect, and wherein the first unit is configured to perform a first intra-die test in an intra-die test mode that tests a function of the first multiplexer, the first data register, or the first I/O pad, and the second unit is configured to perform a second intra-die test in an intra-die test mode that tests a function of the second multiplexer, the second data register, or the second I/O pad.

In some embodiments, in an inter-die test mode, the first data register outputs the test case to the first I/O pad, and the first I/O pad forwards the test case to the second I/O pad, wherein the second I/O pad directs the test case to the second data register through a scan-in path of the second die.

In some embodiments, the first loopback path includes a first I/O pad and a first multiplexer, and the second loopback path includes a second I/O pad and a second multiplexer, and wherein in the scan mode, a buffered test case is provided to the first data register and the second data register via the first multiplexer and the second multiplexer.

In some embodiments, the first die further comprises: a first BIST controller configured to initiate an intra-die test of logic functions of the first die, an inter-die test of logic functions of an interface between the first die and the second die, or a stack-level test of logic functions of both the first die and the second die; a first instance generator configured to generate a predetermined test instance of the first data register; and a first response compactor configured to receive responses to the predetermined test case from the first unit and generate data for analyzing yield and fault diagnosis of the first die or the second die.

In some embodiments, the first BIST controller comprises a plurality of multiplexers that generate control signals that control the first multiplexers.

In some embodiments, the second die further comprises: a second BIST controller configured to enable intra-die testing of logic functions of a second chip, inter-die testing of logic functions of an interface between a first chip and a second die, or stack-level testing of logic functions of both the first die and the second die; a second instance generator configured to generate a predetermined test instance of the second data register; a second response compactor configured to receive responses to the predetermined test case from the second unit and generate data for analyzing yield and fault diagnosis of the first chip or the second chip.

In some embodiments, the second BIST controller comprises a plurality of multiplexers that generate control signals that control the second multiplexers.

In some embodiments, the first unit is further configured to perform an inter-die test, the inter-die test comprising at least one of: a chain test to test a chain shift of the first and third units of the first die, a Direct Current (DC) test to test whether at least one of the first multiplexer, the second multiplexer, the first I/O pad, the second I/O pad, the first data register, or the second data register is shorted or opened, an Alternating Current (AC) test to test whether at least one of the first multiplexer, the second multiplexer, the first I/O pad, the second I/O pad, the first data register, or the second data register is time-series failed, a leakage test to test a unit leakage failure within the first die, a bridge test to test a wire-to-wire bridge between the first die and the second die, or a burn-in test to test a burn-in failure of the first die or the second die.

In some embodiments, the first I/O pad includes a first buffer and a second buffer that are collectively configured to buffer a predetermined test signal, and wherein the second I/O pad includes a third buffer and a fourth buffer that are collectively configured to buffer the predetermined test signal.

In some embodiments, the first I/O pad comprises a first buffer configured to buffer a predetermined test signal, and wherein the second I/O pad comprises a second buffer configured to buffer the predetermined test signal.

In some embodiments, the inter-die interconnect is a physical wire between the first die and the second die.

In another embodiment, a method of testing one or more dies using built-in self-test (BIST) functionality, the method comprising: data including a predetermined test case is received through a data register of the die. The I/O pads and multiplexers are provided with predetermined test cases by the data registers. The predetermined test case is buffered through the I/O pads. The buffered predetermined test pattern is provided back to the data register via a loop-back path formed through the I/O pads and the multiplexer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A cell of an integrated circuit, the cell comprising:

a data register configured to output a signal;

an input/output pad coupled to the data register, wherein the input/output pad is configured to receive the signal and buffer the signal; and

a first multiplexer coupled to the input/output pad and the data register, the first multiplexer configured to selectively output the buffered signal or selectively output the signal based on enabling a scan mode or a functional mode.

2. The unit of integrated circuit of claim 1, wherein a loopback path comprises the input/output pad and the first multiplexer, the loopback path configured to direct the buffered signal back to the data register through the first multiplexer.

3. The unit of integrated circuit of claim 1, further comprising:

a second multiplexer coupled to an input of the data register, the second multiplexer configured to enable the scan mode or the functional mode based on a control signal driving the second multiplexer;

a third multiplexer coupled to an input of the second multiplexer, the third multiplexer configured to enable a scan-in signal or a loop-back signal to be provided to the second multiplexer; and

A logic gate coupled to an input of the third multiplexer, the logic gate configured to switch or hold data provided to the data register via the second multiplexer and the third multiplexer.

4. A unit of integrated circuit according to claim 3, wherein the control signals are generated by a plurality of multiplexers built-in to a self-test controller.

5. The unit of integrated circuit of claim 2, wherein the buffered signal is directed back to the data register when scan mode is enabled, and the signal output by the data register is a test case signal.

6. The unit of integrated circuit of claim 5, wherein the test case signal is provided by a case generator configured to generate a test case signal based on a particular test performed by the integrated circuit.

7. The integrated circuit unit of claim 1, wherein the input/output pad comprises a first buffer and a second buffer that are commonly configured to buffer the signal.

8. The unit of integrated circuit of claim 1, wherein the input/output pad comprises a buffer configured to buffer the signal.

9. An integrated circuit with built-in self-test functionality, the integrated circuit comprising:

a first die comprising a first unit including a first multiplexer, a first data register, and a first input/output pad; and

a second die comprising a second unit including a second multiplexer, a second data register, and a second input/output pad,

wherein the first die is coupled to the second die via an inter-die interconnect, and wherein the first unit is configured to perform a first intra-die test in an intra-die test mode, the first intra-die test testing a function of the first multiplexer, the first data register, or the first input/output pad, and the second unit is configured to perform a second intra-die test in the intra-die test mode, the second intra-die test testing a function of the second multiplexer, the second data register, or the second input/output pad.

10. A method of testing one or more dies using built-in self-test functionality, the method comprising:

receiving data including a predetermined test case through a data register of the die;

Providing the predetermined test case to an input/output pad and a multiplexer through the data register;

buffering the predetermined test case through the input/output pad; and

the buffered predetermined test case is provided back to the data register via a loop-back path formed through the input/output pads and the multiplexer.