JPS63177081A - Large-scale integrated circuit apparatus having testing circuit - Google Patents

Abstract

PURPOSE:To make it possible to execute a test of an apparatus with ease and without fail, by providing a testing circuit for each module on a printed circuit board and by setting arbitrary data thereon from outside. CONSTITUTION:A terminal DIN receives an output of a module in the preceding stage, and a terminal DOUT is connected to an input to a module in the following stage. A signal in a normal time is sent from the terminal DIN to the terminal DOUT through gates G2 and G3. In the abnormal time, on the other hand, the gate G2 is turned off and thereby a flow from the terminal DIN is intercepted. Now, when a clock signal CK is inputted to FF1 after a clear signal Cr is supplied to a clear signal line CR to reset a testing circuit, an H level is delivered from an output FF1 when input data Si are at an H level. This H level is inputted to a gate G1 and FF2 in the following stage. As for an output of FF2, moreover, a Q output is turned to be H and a Q' output L by the clock signal CK, and the Q output is inputted to the gate G1, while the Q' output is inputted to the gate G2. In this way, a test can be executed with ease and without fail.

Description

[Detailed Description of the Invention] [Summary] In a large-scale integrated circuit device, a test circuit is provided between each module constituting a logic circuit, etc., and conduction between the previous module and the next module is established by inputting data to the test circuit. /Large-scale integrated circuit device that controls shutdown and tests subsequent modules.

[Industrial application field]

The present invention relates to a large-scale integrated circuit device (hereinafter referred to as L) having a test circuit.
SI).

[Problems to be solved by conventional technology and invention] LS
In recent years, the degree of integration of I has been increasing more and more, and as the degree of integration increases, the number of internal gates that are not directly connected to external pins increases, making it increasingly difficult to test the operation of these internal gates. Under these circumstances, methods for designing circuit structures that are easy to test have been developed as one direction. In other words, it is a scan path method, and the basis of this method is to develop a sequential circuit into a combinational circuit. A switch means is added to a logic circuit separated into a combinational circuit and a flip-flop, and the switch means is switched between shift mode and normal mode. Accordingly, the test is performed by applying a scan input in the shift mode. A typical method similar to this method is LSSD (Level 5 sensitive 5c) by 18M Company in the United States.
There is a design method.

The LSSD method uses scan logic to observe the operational status of internal gates. Specifically, the above-mentioned method is constructed by connecting flip-flops in a chip in order to form a shift register, and inputting data from the outside to this shift register. is given to each flip-flop to take the value "l" or "0", and in this state, the shift register is released and each flip-flop returns to its original circuit to operate the LSI, and each flip-flop is given its value. The current state of each flip-flop is assumed (this becomes output data), the shift register is configured again, and the state of each flip-flop, that is, the internal state, is taken out to the outside by a shift operation.

However, although these methods are effective for verifying the internal circuit of each block, it is necessary to operate the system in normal mode to check for problems such as timing. When a problem with timing or the like occurs, in a conventional SSI system, the problem can be repaired by cutting a pattern on the printed circuit board, adding a circuit, or the like. However, if there is a defect inside the LSI, the same method is not possible and the LSI must be rebuilt to obtain the desired function.
There was a problem in that it was not possible to evaluate the parts after the defective circuit until the SI was obtained.

[Means and effects for solving the problems] The present invention provides a large-scale integrated circuit having a test circuit that solves the above-mentioned problems. In large-scale integrated circuit devices,
A test circuit installed between each module that controls conduction/cutoff of the output of the previous module to the next stage and supplies predetermined data to the next module, and a clear circuit that supplies a signal to reset the test circuit before testing. A signal line, a data line that supplies the test circuit with the data for testing the next-stage module and subsequent modules, and a clock signal line that supplies the signal that determines the transfer timing of the data. A feature is that the module can be separated to perform testing.

〔Example〕

FIG. 1 is a partial block diagram of a large-scale integrated circuit device having a test circuit according to the present invention. 2 is a circuit diagram of one embodiment of the test circuit, and FIG. 3 is a circuit diagram of another embodiment of the test circuit.

In FIG. 1, block B++ + Bl! LB! l
+822, . . . are modules constituting the LSI, and each module is a logic circuit composed of, for example, a NAND gate or a NOR gate. On the other hand, block T++ * Ttt + Ttt + Ttt・
. . . are test circuits according to the present invention, which are provided between each module. In addition, the distribution AD is a signal line that connects each module on a large-scale integrated circuit device, and as described later, the CK, CR, SL, SO, etc. that connect the next module through the test circuit are tested. Wiring on a large scale integrated circuit device for the circuit, CK is for the clock signal, CR is for the clear signal, SL is for the test circuit input, and SO is for the test circuit output.

As shown in FIG. 4, all test circuits are connected in series. That is, the output line SO of the last test circuit Tin in the - column is connected to the first test circuit T2 . is connected to the input line SI of.

FIG. 2 is a circuit diagram of an embodiment of the test circuit of FIG. 1. Second
In the figure, FFI and FF2 are flip-flop circuits, G1 and G2 are AND gates, and G3 is an OR gate.

In such a configuration, for example, when a failure is discovered in the module Bll, the output of the module Bll is cut off and the input is supplied from the test circuit T11. In FIG. 2, the terminal DIN is a terminal that receives the output of the module at the previous stage, and the terminal DOUT is connected to the input to the module at the next stage.

A normal signal is sent from terminal DIN to DOUT via gates G2 and G3. Furthermore, in the event of an abnormality, the gate G2 is turned off to cut off the flow of data Din. Now, after resetting the test circuit by supplying the clear signal Ck to the clear signal line CR, when the clock signal Ck is input to the flip-flop FFI, the input data Si goes high (
When the signal is at the H) level, a ``H'' level is output from the output of the FFI, and this "H" level is input to the Gl) and the next stage flip-flop FF2. The output of FF2 is the clock signal input in parallel, so the Q output becomes 'H' level and the FF2 output becomes 'L' level, and the Q output becomes gate G.
The inverted output 100 is input to gate G2. Since gate G2 needs to be turned off when the previous module is abnormal, one input of gate G2, that is, the inverted output i
side must be kept at “L” level.

In this way, the data to be sent to the flip-flops FFI and FF2 is arbitrarily determined, and by shifting it using the clock signal, the DOUT terminal is set to H" or "L".
A level signal can be obtained and supplied to the next module. In this case, as described above, it is necessary to consider one input of the gate G2 so that the gate G2 is cut off in the event of an abnormality, and this is determined by the data array stored in the flip-flop.

FIG. 3 is a circuit diagram of another embodiment of the test circuit.

In this case one flip-flop FF and N-channel MO3I-transistor Trl and P-channel MOS)
It is composed of a transistor Trt. As is clear, the circuit configuration is simplified compared to the first embodiment. However, in this case, the output data Dout cannot be obtained arbitrarily. That is, when the front module is normal, the bases of the transistors T, . In case of abnormality, turn off T□ and Tr! Turn on. Since T is turned on by setting the gate to the "L" level, the output of the flip-flop FF is restricted to the "L" level. Therefore, when the clock signal Ck causes the FF to output the "L"" level, T turns on and obtains the "H" level output from the power supply +. That is, in this embodiment, the output during abnormality is always only at the 'H' level.

This "H" level is input to the next stage block.

FIG. 4 is a diagram showing the mounting state of the test circuit and LSI device according to the present invention. Module BI on printed circuit board PB
I+81g... and test circuit Tll I T'+t...
・A signal line and test circuit wiring C are placed between them.
R, CK, Sl, etc. are provided, and terminals CR, CK, Sl are provided for these wirings.

〔Effect of the invention〕

As explained above, according to the present invention, a test circuit is provided for each module on the printed circuit board of an LSI device, and arbitrary data is set from the outside, thereby making it possible to easily and reliably test the LSI device. .

[Brief explanation of the drawing]

FIG. 1 is a partial block diagram of a large-scale integrated circuit device having a test circuit according to the present invention, FIG. 2 is a circuit diagram of one embodiment of the test circuit of FIG. The embodiment circuit diagram and FIG. 4 are plan views of a large-scale integrated circuit device having a test circuit according to the present invention. (Explanation of symbols) Blt * Blt + Bt+ + Big... module, T++ + T+z + Tit + Tz
t...'Test circuit, FF, FF1. FF2...Flip-flop, Gl, G2...AND gate, G3...OR gate, T,,,T,,...MOS) transistor.

Claims (1)

[Claims] 1. In a large-scale integrated circuit device in which multiple modules are arranged on a board, a circuit is provided between each module to control conduction/cutoff of the output of the previous module to the next stage, and to send predetermined data to the next module. A test circuit to be supplied, a clear signal line to supply a signal to reset the test circuit before testing, a data line to supply the test circuit with the data for testing the next module onward, and a transfer of the data. 1. A large-scale integrated circuit device, comprising a clock signal line for supplying a timing signal, and is capable of testing by making it possible to separate any module using the test circuit.