JPH07294606A - Self inspecting circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a self inspecting circuit for LSIs which incurs a small overhead when mounted., without damaging an inspecting quality. CONSTITUTION:The circuit is constituted of a to-be-inspected circuit 1 originally to be equipped in an LSI, an inspecting circuit 2 for taking output data from the to-be-inspected circuit 1 and outputting inspecting data to the circuit 1, a selector 5 for selecting a signal at a normal using time or a signal at an inspecting time, a judging circuit 4 for judging an inspecting result, and a controlling circuit 3 for controlling the inspecting circuit 2, selector 5 and judging circuit 4 at an inspecting time. An output of the to-be-inspected circuit l is input to the inspecting circuit 2, and fresh inspecting data to be input to the to-be-inspected circuit 1 are generated based on an output from the inspecting circuit 2. The inspecting data generated in the inspecting circuit 2 is input to tone to-be-inspected circuit l, based on which the to-be-inspect,ed circuit 1 is inspected. Accordingly, a necessary amount of data for the inspection is reduced large and the inspection is carried out quickly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-inspection circuit of a semiconductor integrated circuit (hereinafter referred to as LSI) which is a semiconductor device. This self-inspection circuit may be built in an LSI chip or connected to an LSI chip. It can also be used as an external inspection.

[0002]

2. Description of the Related Art In recent LSIs, the scale and density have been increased, the amount of inspection data for inspecting the LSI has become huge, and the time and cost tend to increase. As means for solving this problem, there is an LSI self-inspection circuit disclosed in Japanese Patent Laid-Open No. 62-150874, which discloses a circuit as shown in FIG. This self-inspection circuit stores data for inspecting the circuit in the memory. Therefore, as the circuit to be inspected becomes large in scale, the inspection data becomes huge and the memory capacity and the like increase. .

[0003]

The conventional LS described above is also used.
The self-inspection circuit of I can perform self-inspection using a large amount of inspection data at high speed, but it has a test control circuit, a test control memory, a test pattern memory, a test operation circuit, and a pattern comparison circuit. Since it is necessary to incorporate the selector and the selector, the area overhead of the entire inspection circuit becomes large, and the area of the LSI increases. Therefore, it is an object of the present invention to provide an LSI self-test circuit that has a small overhead during mounting without impairing the quality of the test.

[0004]

In order to achieve the above object, the present invention is a self-inspection circuit for self-inspecting a semiconductor device, especially a semiconductor integrated circuit (LSI), which is an inspected circuit to be inspected. 1, and a data output function for outputting inspection data to the circuit under inspection 1, a data generation function for automatically generating new inspection data based on output data output from the circuit under inspection 1, and An inspection circuit 2 including an initial value input means for accepting and confirming only the first inspection data at the start of a series of inspections,
Further, a selection means for selecting either an input signal at the time of normal use or the inspection data of the inspection circuit 2 at the time of inspection, and further, the inspection data output by the inspection circuit 2 at the end of inspection after repeating inspection a predetermined number of times. On the basis of this, there is provided a judgment circuit 4 for judging whether the circuit under test 1 is normal or abnormal, and a control circuit 3 for controlling the inspection circuit 2, the initial value input means, the selection means and the judgment circuit 4 at the time of inspection. ,
The inspection circuit 2 is composed of a linear feedback shift register and an inspection data generation means for automatically generating new inspection data from the output data of the circuit under inspection 1 and the linear feedback shift register. And

[0005]

The first inspection data (inspection data initial value) is set in the inspection circuit 2 by the inspection start signal from the initial value input means and is given to the inspected circuit 1, and the initial value input means is disconnected. After that, the inspection data is calculated in the circuit under test 1 and the calculation result is output. The inspection circuit 2 is composed of a linear feedback shift register, and thereafter, by simply applying a clock (CLK) signal, the operation result is data-compressed, and the data-compressed value is used as the next inspection data to be inspected again. 1 and perform the following inspections.
By using the calculation result calculated by the circuit under test 1 in this way,
The inspection circuit 2 automatically generates the next inspection data again. When the required number of times required in advance is inspected,
The final calculation result of the circuit under test 1 is compared with the expected value, and the judgment circuit 4 judges whether the circuit under test 1 is normal or abnormal.

[0006]

According to the LSI self-check circuit of the present invention,
The output of the circuit under test is input to the circuit under test, new test data to be input to the circuit under test is generated based on the output of this circuit, and the test data generated by the circuit under test is input to the circuit under test. By inspecting the circuit to be inspected based on this inspection data, the amount of data required for the inspection can be greatly reduced. In addition, the inspection data, which has been conventionally processed by different configurations, is generated and compressed by one inspection circuit, and a quick inspection is performed. Therefore, there is an effect that the self-inspection circuit can be easily configured without impairing the quality of the inspection, and at the same time, the circuit area for that can be reduced. Furthermore, by configuring the inspection circuit with the linear feedback shift register, there is an effect that the self-inspection circuit can be easily configured regardless of the number of input signal lines and the number of output signal lines of the circuit under test. Further, even when the inspection circuit is provided outside, the inspection can be completed quickly and automatically.

[0007]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a self-inspection circuit of an LSI that handles digital signals as a first embodiment. Figure 1
As shown in FIG. 1, the LSI self-test circuit fetches a logic circuit that the LSI should originally have, for example, a circuit under test 1 (or an internal circuit) such as a multiplier or a ROM, and output data of the circuit under test 1. An inspection circuit 2 that outputs inspection data to the circuit under inspection 1; a selector 5 that is a switching circuit that is a selection unit that selects an input signal during normal use and inspection data that is an input signal during inspection; From a judgment circuit 4 which is a test result judging means for judging an inspection result outputted from the inspection circuit 2 at the time of inspection by a comparison circuit and the like, and a control circuit 3 which controls the inspection circuit 2, the selector 5 and the judgment circuit 4 at the time of inspection. Composed.

FIG. 3 is a block diagram showing an example of the inspection circuit 2 shown in FIG. In this inspection circuit 2, the signal lines 101 to 13
2 is connected to the output signal line of the circuit under test 1. The signal lines 201 to 232 are connected to the inputs of the selector 5.
The signal lines 101 to 132 are connected to one of the inputs of the inspection data generating circuits 401 to 432 which are the inspection data generating means, and the inspection data generating circuits 401 to 432 are connected to the flip-flops (hereinafter referred to as F / F and Note) is connected to. Also the first stage
The output of F / F1 is connected to the input signal line 201 and
It is connected to the other input of the inspection data generation circuit 402 and F / F2
Up to F / F31 are connected in the same way.

Some of the outputs of F / F1 to F / F32 are connected to the inspection data generating means 401 through exclusive OR (hereinafter referred to as EXOR) of the logic circuit. In FIG. 3, input signal lines 229 and 232 (outputs of F / F29 and F / F32, respectively) are connected to EXO so that F / F1 to F / F32, which form a linear feedback shift register (LFSR), form a primitive polynomial.
A feedback (FB) connection is made to the inspection data generation circuit 401 via R300. Of course, it is needless to say that the FB connection of other F / F may be selected so that necessary inspection data for inspecting the circuit under inspection 1 can be obtained.

The construction of a primitive polynomial means that in FIG.
In the LFSR in which the F / Fs are connected in series as shown in, realize a circuit configured to have a relationship in which the most data patterns output to the input signal lines 201 to 232 of the circuit under test 1 appear. Which means that this is mathematically proven. Conversely, if the circuit is configured in this way, the output of the circuit represents a primitive polynomial. Then, other F / F connections may be selected, which means that the primitive polynomial is always realized when the required number of checks is smaller than the number of data patterns indicated by the primitive polynomial. This means that the inspection circuit 2 is not necessary. In such a case, it is also included as another option that the number of F / F stages may be changed.

F / F1 to F / F32 shown in FIG. 3 are 32-bit shift registers driven by the external clock CLK by SEL2, and desired 32-bit "0""1" data is used as the first inspection data. Of the LFSR to operate as an initial value input means for serially inputting into the inspection circuit 2 and confirming it, or to generate new inspection data based on the signals of the signal lines 101 to 132 from the circuit under inspection 1. Works as either or can be switched to either.

FIG. 4 shows the inspection data generating circuit in FIG. 3 as an example of the inspection data generating means. Figure 4
In the inspection data generation circuit 401 in (a), the signal line 101 and the signal line FB are connected to one input of the selector 460 via the EXOR 450, and a value determined by the states of the signal line 101 and the signal line FB is input. . In addition, the signal line SIN is
Connected to the other input of 0. The selector 460 selects one of these inputs by the signal line SEL2 and outputs it to the input of F / F1 (O in FIG. 4 (a)).

FIG. 4 (b) for the second stage F / F2 of FIG.
In the inspection data generating circuit 402, the signal line 102 (I in FIG. 4) is connected to one input of the EXOR 451. EX
The other input of OR451 is connected to the output of F / F1 (S in FIG. 4 (b)). The output of this EXOR451 is the selector 46
1 is connected to one input, and the other input of the selector 461 is connected to S (the output of the previous stage F / F1). The selector 461 selects one of these inputs by the signal line SEL2 and outputs it to the input of F / F2 (O in FIG. 4 (b)).

Then, like the inspection data generation circuit 402,
The inspection data generation circuits 403 to 432 are connected. The inspection data generation circuits 402 to 432 may have the configuration shown in FIG. That is, the EXOR 452 comes after the selector 461.

In the self-inspection circuit having the above structure,
A series of inspection operations from the start of inspection will be described. Shown in Figure 1
When the circuit under test 1 enters the test mode by the TEST signal,
The selector 5 is switched from the input signal line NIN in the normal state to the input signal lines 201 to 232 in the test by the control circuit 3 and SEL1.

Next, from the control circuit 3 by SEL2, as shown in FIG.
The inspection data generation circuit 401 is switched to SIN, and the other inspection data generation circuits 402 to 432 are switched to signal line SIN (S side input, see FIG. 4). As a result, F / F1 to F / F32 in FIG.
However, it will be in the state of operating as a 32-bit shift register. Next, from control circuit 3 through SIN, 32-bit "0"
"1" data is serially output from F / F1 to F / F32 by CLK.
Enter and confirm. The data of "0" and "1" becomes the first inspection data in the series of operations for inspecting the circuit under inspection 1. In addition, since the configuration of the circuit under test 1 is originally known, the "0" and "1" data input at this time is
The data can be determined in advance so that the expected failure of the circuit under test 1 can be identified, and therefore the data can be held in the control circuit 3 in advance.

After the first inspection data is taken into the F / F1 to F / F32 through the signal line SIN and confirmed, the inspection data generation circuit 401 is connected to the 101 / FB side and the other inspection data generation circuits 402 to 432 are connected. Switch to the signal lines 102 to 132 (I side in FIG. 4B). That is, the SIN of the F / F1 is disconnected, and the control circuit 3 and the inspection circuit 2 are disconnected until a series of inspection operations are completed thereafter. As a result, the F / F1 to F / F32 are brought into a state where they operate as a linear feedback shift register, and the circuit under test 1 and the circuit under test 2 are connected to carry out the inspection.

In this state, the first inspection is started. (1) When the CLK signal is input to F / F1 to F / F32, the first inspection data, which has been confirmed and held in F / F1 to F / F32, is sent through signal lines 201 to 232. It is input to the circuit under test 1 in parallel. The circuit 1 to be inspected outputs the first inspection result (output data) according to the inspection data, and the signals are input to the inspection circuit 2 in parallel through the signal lines 101 to 132. The process up to this point is called the first inspection.

(2) Subsequently, the second inspection is started.
When CLK is input to F / F1 to F / F32, the inspection data generation circuits 401 to 43 are generated from the first inspection result and F / F1 to F / F32.
The second inspection data newly generated in 2 is input to the circuit under test 1 in parallel through the signal lines 201 to 232. The inspected circuit 1 outputs the second inspection result (output data) in accordance with the inspection data, and inputs the inspection result to the inspection circuit 2 through the signal lines 101 to 132. The process up to this point is called the second inspection.

(3) In the same manner, the third and fourth inspections are automatically performed only by applying the CLK signal.

This process is repeatedly executed a sufficient number of times to inspect all the faults in the circuit under test 1, up to n times. The final value of the number of times of inspection n, the value taken into F / F1 to F / F32 as the first inspection data, and the expected value when the circuit under test 1 is normal are the configuration of the circuit under test 1. Since it is known, it can be calculated in advance in consideration of the failure detection of the circuit under test 1.

After the nth inspection is completed, the control circuit 3 causes the input of the inspection data generation circuit 401 to SIN by SEL2.
Input the inspection data generation circuits 402 to 432 to the signal line SIN
(And S in Fig. 4 (b)). By this, F / F
1 to F / F32 are ready to operate as 32-bit shift register again. The final output data of the circuit under test 1 is held in the F / F1 to F / F32. Next, by CLK, F /
The "0" and "1" data held in F1 to F / F32 are serially output to the determination circuit 4 through SOUT. This "0""1"
The data is called the final inspection result.

The final inspection result is a pattern reflecting normality / abnormality of the circuit under test 1. That is, when the circuit under test 1 is a normal product, the final inspection result is exactly the same as the expected value obtained in advance. If there is a defect inside the circuit under test 1, the final inspection result will be any data different from the expected value. The determination circuit 4 compares the expected value held in advance with the output from SOUT in response to the determination execution signal from the control circuit 3, outputs normal 0 if they match, and outputs abnormal 1 if they do not match, and Circuit 1
Ends the inspection.

The circuit under test 1 may have a register inside, and in that case, the external clock CLK is also input into the circuit under test 1 at the time of the test to carry out the test while operating the register. You can also Further, in the inspection circuit 2, the number of the signal lines 101 to 132 is equal to the number of the signal lines 201 to 232, but it can be applied even when the number of the signal lines is different. In such a case, for example, FIG.
When the signal lines are 101 to 131,
132 may be deleted and EXOR332 connected to the signal line 132 may be deleted.

Similarly, when the signal lines are from 201 to 231, the signal line 232 is deleted and the output of the F / F32 is set to EXOR300.
You only need to leave the part connected to. Furthermore, the number of input signal lines and output signal lines of the circuit under test 1 may vary, but the number of F / Fs that make up the test circuit 2 also varies depending on the number of signal lines. Can be considered. In any case, it is possible to cope with the configuration so that a sufficient number of test data for testing the circuit under test 1 can be output.

Although the final inspection result is output through SOUT in FIG. 1, the same effect can be obtained even if the values of the signal lines 101 to 132 at the end of the inspection are directly addressed to the determination circuit 4 in parallel. Needless to say, it can be obtained.

(Second Embodiment) The inspection circuit 2 is used in the first embodiment.
To enter and confirm the first inspection data in
However, the present invention can be similarly applied even if the F / F with a set or reset is used as the initial value input means. A configuration diagram of the inspection circuit 2 in this case is shown in FIG.

In the second embodiment shown in FIG. 6, the F / F1 to F / F32, which are the constituent elements of the inspection circuit 2, are F / Fs with either a set or a reset function. Each F / F is set and reset by the SR signal from the control circuit 3, and at the time of inspection, the control circuit 3
The SR signal directly determines the first inspection data for each F / F. For the F / F with set / reset, select either one in advance and fix it in hardware. This is because the data to be set in advance is determined similarly to the first embodiment. In this case, the inspection data of the first time cannot be changed at the time of inspection, but the configuration of the initial value input means becomes simpler, and the selector in the inspection data generating circuit shown in FIGS. Be converted.

(Third Embodiment) As a third embodiment, a self-inspection circuit 1000 for specifically implementing the second embodiment is shown. Figure 7
As shown in FIG. 8, the circuit to be inspected 1001, the circuit to be inspected 1002, etc., and the LFSR shown in FIG.
A case of inspecting the circuit under test 1001 of FIG. 9 will be described. The circuit under test 1001 is a logical operation circuit, is composed of an AND circuit and an OR circuit, and has a configuration of 15 bits for input and 7 bits for output. The inspection circuit 1002 in FIG. 8 has F / 15 with a set.
It consists of F, and the circuit under test 1001 is placed in front of the input of F / F1 to F / F7.
An EXOR is provided between the output signal lines 1010 to 1016 from the F / F1 to F / F7 and the feedback lines from the F / F15 to the F / F10, F / F12, and F / F14. In this configuration, EXOR is inserted between the output and F / F1. In this case, the primitive polynomial is x ¹⁴ + x ⁵ + x
³ + x + 1. The circuit 1 to be inspected is inspected as follows.

First, when the test enable signal TE becomes Hi, the normal input signal line NIN to the circuit under test 1001 is disconnected by the switch circuit 1005 (15 sets are provided for each of the signal lines 1020 to 1034). At the same time, the inspection circuit 1002 is connected to enter the inspection mode. And in that state, FIG.
One pulse of the SET signal is output from the control circuit 3 (not shown), and data is set in each F / F with set / reset of the inspection circuit 1002. Since all of them are set F / F here, 15-bit "1 ... 1" (7fff in hexadecimal notation) is set. When the first clock signal (CLK) first enters one pulse as a signal, the data (7fff) set in the inspection circuit 1002 is output from the state to the inspected circuit 1001 as the first inspection data. . This is shown in FIG. 10 as the first vector. The circuit under test 1001 is operated immediately after the signal is set, and the first output data is output to the output signal lines 1010 to 1016. Then, at the next clock signal, this output data value is held as new inspection data (7f82) (second vector) by the inspection data generation circuit of the inspection circuit 1002.

Each time a clock signal is input, inspection data is supplied to the circuit under inspection 1001 to perform inspection, and the inspection data is updated one after another. It is known in advance that the inspection is completed with the output data of the 107th vector if there is no abnormality in the logical operation circuit (circuit 1001 to be inspected) of FIG. 9, so when the clock is input 107 times, That is, the final inspection result (5858) is output to the determination circuit at the 108th clock and thereafter.

The output of the final inspection result is SOUT of the inspection circuit 1002.
Is output as serial data from. That is, since the data held in F / F15 is output for each subsequent clock,
As in the SOUT chart shown in FIG. 11E, the inspection result (5858) after completion of the 107th vector is output as serial data. Then, when all the bits of the inspection result are output, the test enable signal is set to Lo to complete the inspection. The inspection circuit 1002 simply outputs the inspection result (5858).
Is not output from SOUT. The operation of the circuit under test 1001 is output every clock and the signal line 10 of the circuit under test 1002 is output.
It is input to 10 to 1016 and keeps changing with EXOR,
The serial data output from SOUT and stored in the determination circuit does not always hold the inspection result value (5858) of the circuit under test 1001. However, since the value finally held in the judgment circuit is known beforehand as the expected value, there is no problem in the judgment of the inspection. The serial data of SOUT in Fig. 11 (e) is
The same as (5858) of the inspection result by the inspection circuit 1002 of FIG.
(5858) is output only by accident.

The behavior when there is a defect will now be described. For example, assuming that the circuit under test 1001 has a defect, as shown in the signal line data of FIG. 10 (a '), if data indicating an abnormality appears in the inspection result at the time when the 97th vector is given, the case is normal. If the inspection result is supposed to be (0e0d), but it becomes (0e06) due to a defect, this changed inspection result will be the next inspection data as the circuit under test.
Since it is given to 1001, the changed influence remains as it is up to the final 107th vector, and the final inspection result is a result different from that at the normal time (2839 in FIG. 10). Therefore, the abnormality of the circuit under test 1001 is determined. The probability that this inspection result value will return to a normal value on the way is extremely small, and since such an inconvenience can be estimated to some extent in advance, it can be avoided by setting the initial value appropriately, It does not affect the inspection.

In addition to the above, as the judgment of the inspection result, since the inspection result is held in F / F, it is also output as a value to the output NOUT of the circuit under inspection 1001 as shown in FIG. The inspection result value (5858) can be read, and this value may be used for the determination.

(Fourth Embodiment) In the fourth embodiment, as shown in FIG. 12, the circuit under test 71 has a scan path function, and the registers 76, 77 of the circuit under test 71 (for simplicity) are shown.
The signal line is connected so that the TEST signal and the SCAN-IN signal are input to the F / F) and the SCAN-OUT signal is output. In this case, the TEST signal
When the circuit under test 71 enters the test mode, predetermined data is input from the external scan-in input SCAN-IN to register 7
6 and 77 are operated as a shift register, and the values of the registers 76 and 77 are taken out from the external scan-out output SCAN-OUT, so that the circuit under test 71 can be easily inspected. As described above, even in the circuit under test 71 which is difficult to be inspected by the signal from the inspection circuit 72, by providing a small number of signal lines in advance so as to facilitate the inspection, the LS
Inspection of I is performed. The operation of the inspection itself is the same as that of the embodiment described above. The signal during normal use is shown in Fig. 1.
It flows through NIN and NOUT shown in 2.

(Fifth Embodiment) In the fifth embodiment, as in the fourth embodiment, as shown in FIG. 13, one of the signal lines 101 to 132 inside the circuit under test 81 can be tested. The signal line 132 having low observability can be directly connected to the inspection circuit 82 (for example, before the multi-input AND gate) to easily perform the inspection. Furthermore, the circuit under test 81
Among the signal lines inside the, for the signal lines with low test controllability, the input signal line 232 can be directly input to the inspection circuit during inspection (for example, after the multi-input AND gate),
The inspection can be performed easily. In this case, a switching means (FIG. 8) is added so that the signal line 232 is selected by the TEST signal in the inspection mode, and the inspection is performed by switching from the signal line for normal use. Therefore, even a circuit to be inspected having such an element with low observability can be sufficiently inspected and the efficiency of inspection can be improved.

(Sixth Embodiment) In this embodiment, as shown in FIG. 14, at the time of inspection, the internal bus 9 originally included in the LSI is provided.
7, the inspection circuit 94 is connected via signal lines 601 to 632 and signal lines 501 to 532. At the time of inspection, the control circuit 95 controls a connection circuit originally included in the LSI included in one or more circuits to be inspected included in the LSI to connect, for example, the first circuit 91 to be inspected and the internal bus 97. .
Next, from the inspection circuit 94, in the same manner as in the first embodiment,
The circuit under test 91 is inspected. Similarly, the circuit under test 92 and the circuit under test 93 are sequentially tested. In this embodiment, the connection circuits used in the circuits under test 91 to 93 operate as a selection unit that selects a signal of the inspection data at the time of inspection. With such a configuration, it is possible to separate the connection to the internal bus 97 and the control line 98 from the control circuit 95 to each circuit to be inspected. It is easy to form the circuit 96 into an external configuration (for example, an LSI inspection probe), and the inspection can be performed quickly.

As shown in each of the above embodiments, according to the self-inspection circuit of the LSI having the configuration of the present invention, that is, the output of the circuit to be inspected is input to the inspection circuit, and the output of the inspected circuit is used for the inspection. Necessary for inspection by generating new inspection data to be input to the inspection circuit, inputting the inspection data generated by this inspection circuit to the inspected circuit, and inspecting the inspected circuit based on the generated inspection data. Since it is possible to significantly reduce the amount of required data, it is possible to easily configure the self-test circuit without deteriorating the quality of the test, and at the same time, it is possible to reduce the circuit area for that purpose. The inspection can also be easily performed by connecting such a self-inspection circuit from the outside.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional technique.

FIG. 3 is a configuration diagram showing an example of a circuit under test.

FIG. 4 is a configuration diagram showing an example of inspection data generating means of the present invention.

FIG. 5 is a configuration diagram showing an example of inspection data generating means of the present invention.

FIG. 6 is a configuration diagram showing a second embodiment of the present invention.

FIG. 7 is a configuration diagram showing a third embodiment of the present invention.

FIG. 8 is a configuration diagram showing an inspection circuit 1002 of a third embodiment.

FIG. 9 is a configuration diagram showing a circuit under test 1001 of a third embodiment.

FIG. 10 is an operation chart diagram at the time of inspection of the third embodiment.

FIG. 11 is an operation chart diagram after the inspection of the third embodiment.

FIG. 12 is a configuration diagram showing a fourth embodiment of the present invention.

FIG. 13 is a configuration diagram showing a fifth embodiment of the present invention.

FIG. 14 is a configuration diagram showing a sixth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 inspected circuit 2 inspecting circuit 3 control circuit 4 determination circuit 5 selectors 101 to 132 output signal lines 201 to 232 inspected circuit inspected data output line of inspected circuit (input signal line of inspected circuit) 300 exclusive OR ( EXOR) 401 to 432 Inspection data generating circuit (inspection data generating means) F / F1 to F / F32 Flip-flops 450, 451, 452 Exclusive OR (EXO)
R) 71, 81 Tested circuit 72, 82 Tested circuit 73, 83 Control circuit 74, 84 Judgment circuit 75, 85 Selector 76, 77 Register 91, 92, 93 Tested circuit 94 Test circuit 95 Control circuit 96 Judgment circuit 97 Internal Bus 98 Control line 501 to 532 Input signal line 601 to 632 Output signal line 1000 Self-test circuit 1001 Tested circuit 1002 Test circuit 1010 to 1016 Tested circuit output signal line 1020 to 1034 Tested circuit input signal line 1005, 1006 Switch circuit

Claims (7)

[Claims] 1. A data output function for outputting inspection data for inspecting a circuit under test 1 which is a semiconductor integrated circuit to the circuit under test 1, and a new data output function based on the output data output from the circuit under test 1. Data generating function for automatically generating various inspection data, and an inspection circuit 2 including an initial value input means for accepting and confirming only the first inspection data at the start of a series of inspections, and an input for normal use The inspection circuit 2 at the time of signal or inspection
Of the inspection data, and a determination circuit 4 for determining whether the circuit under test 1 is normal or abnormal based on the inspection data output by the inspection circuit 2 at the end of the inspection after repeating the inspection a predetermined number of times. During the inspection, the inspection circuit 2, the initial value input means,
The inspection circuit 2 includes: a selection circuit; and a control circuit 3 that controls the determination circuit 4. The inspection circuit 2 includes a linear feedback shift register, output data of the circuit under test 1 and the linear feedback shift register. Self-inspection circuit for a semiconductor integrated circuit, comprising: inspection data generating means for automatically generating various inspection data. 2. The test data generating means is configured to input the output data of the circuit under test 1 using an exclusive OR to the input of each flip-flop of the linear feedback shift register. The self-inspection circuit for a semiconductor integrated circuit according to claim 1. 3. The inspection data generating means receives the first inspection data or the output data of the circuit to be inspected 1 into a first stage flip-flop of the linear feedback shift register. Ruka,
The self-inspection circuit for a semiconductor integrated circuit according to claim 3, wherein the self-inspection circuit comprises a selector for selecting. 4. The selector, after the first inspection data is fetched and confirmed,
5. The self-inspection circuit for a semiconductor integrated circuit according to claim 4, wherein the self-inspection circuit has a function of disconnecting a connection of a line for inputting the first inspection data. 5. The self-inspection circuit for a semiconductor integrated circuit according to claim 1, wherein the initial value input means uses a shift register to serially take in and determine only the first-time inspection data. 6. The judgment circuit 4 is a test result to be output from the inspection circuit 2 to the normal circuit 1 to be inspected, an expected value obtained in advance, and an actually performed inspection. 2. The self-inspection circuit for a semiconductor integrated circuit according to claim 1, further comprising: a comparison circuit that compares a result with the expected value to determine whether the circuit under test 1 is normal or abnormal. 7. The semiconductor integrated circuit according to claim 1, wherein the circuit to be inspected 1, the inspection circuit 2, the control circuit 3, and the determination circuit 4 are formed on one chip. Inspection circuit.