JPH11271401A - Scan test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a fault a detection percentage and defective design detection percentage at test of a sequential circuit, while increase of area due to increase of test circuits is suppressed. SOLUTION: In order to utilize flip flops FF2-FF4 used as a shift resistor in a sequential circuit for scan test as well, scan mode signal SM representing effectiveness of supplemental observation operation which takes in logical state in a combination circuit to be observed at test is newly provided. When a scan selective signal SE is '0' (not effective) while the scan mode signal SM is '1' (effective), multiplexers M1-M4 are switched for actual stated supplemental observation operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flip-flop of a sequential circuit to be tested which is connected in sequence to its inputs and outputs, operated as a shift register, and sets the logic state of each flip-flop. The present invention relates to a scan test circuit that tests the operation of a combinational circuit portion of a sequential circuit. In particular, it is possible to improve a failure detection rate and a design failure detection rate of a sequential circuit test while suppressing an increase in area due to an increase in test circuits. The present invention relates to a scan test circuit.

[0002]

2. Description of the Related Art There is a scan test method for testing the operation of a sequential circuit. This scan test method is
For example, as shown by a dashed line in FIG. 1, when the scan selection signal is valid, the input and output of the flip-flop FF of the sequential circuit to be tested are sequentially connected to form a scan circuit. Further, the flip-flops FF are operated as shift registers, and the operation of the combinational circuit 1 of the sequential circuit is tested while setting the logic state of each flip-flop FF. Testing.

[0003] Such a shift register composed of flip-flops is hereinafter referred to as a scan circuit shift register.

In this scan test method, the scan circuit of the flip-flop FF is configured as shown in FIG. 2, for example.

In FIG. 2, a scan selection signal SE is
It becomes invalid when “0 (L state)” and valid when “1 (H state)”.

The scan selection signal SE is "0 (L state)"
, The multiplexer Mi (i is 1 to 5 in this figure)
Captures the signal DIi from the combinational circuit to be tested. Therefore, the flip-flop FFi is connected to the combinational circuit 1 by the signal DIi and the signal DOi, respectively, and becomes a part of the sequential circuit and operates. Hereinafter, this operation is referred to as a capture operation state.

The scan selection signal SE is "1 (H state)"
, The multiplexer Mi (i is 1 to 5 in this figure)
Selects the output of the flip-flop FF which is the preceding stage in the scan circuit. Therefore, the inputs and outputs of the plurality of flip-flops FFi are sequentially connected to form a scan circuit. In addition, the flip-flops FF are operated as scan circuit shift registers, and the operation of the combinational circuit 1 of the sequential circuit is tested while setting the logic state of each flip-flop FF. Test operation. Or later,
This operation is called a scan operation state.

In the scan test method, first, a scan operation state is set, and an initial state of a flip-flop of a sequential circuit to be tested is set (hereinafter, referred to as a scan-in operation). After that, the sequential circuit is operated in the fetch operation state. Subsequently, the scanning operation state is set again,
The operation state is observed while reading the result of the operation in the capture state to the outside (hereinafter, referred to as a scan-out operation). In the scan test method, the operation of the sequential circuit is tested while performing the above operation.

Here, there is a case where a plurality of flip-flops originally constitute a shift register in a sequential circuit (user circuit) to be tested. In such a case, the scan circuit is configured, for example, as shown in FIG. Alternatively, circuits having the same function are configured as shown in FIG. 3 and 4, the flip-flops FF2
Reference numeral 4 thus originally constitutes a shift register by the user circuit. These differences between FIG. 3 and FIG. 4 are due to differences in CAD (computer aided design) tools used for logic circuit design. Alternatively, after designing as shown in FIG. 3, the circuit of FIG. 4 may be obtained by removing the redundant multiplexer Mi and optimizing the circuit.

Note that the shift register constituted by the flip-flop in the user circuit is hereinafter referred to as a user circuit shift register.

[0011]

Generally, a scan circuit includes:
Data observation is performed in both the capture operation and the scan operation. However, in the case of the user circuit shift register circuit, there is a problem in that, due to the circuit configuration, these are combined, only the scan operation is performed, and the scan circuit is not effectively utilized. is there. That is, it is required to further improve the failure detection rate and the design failure detection rate of the test of the sequential circuit with a decrease in the number of nodes that can be used as observation points and / or control points of the combinational circuit. For example, ATPG (automatic test pattern gen
eration) It is desired to improve efficiency. This ATP
G is a CAD for automatically generating test patterns.
One of the tools. At this time, it is also desired to suppress an increase in area due to an increase in test circuits.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a scan test circuit capable of improving a failure detection rate and a design failure detection rate of a sequential circuit test while suppressing an increase in area due to an increase in test circuits.

[0013]

A scan test circuit according to the present invention constitutes a scan circuit by sequentially connecting inputs and outputs of flip-flops of a sequential circuit to be tested, and forms a scan circuit. In a scan test circuit that tests the operation of the combinational circuit portion of the sequential circuit while setting the logic state of each flip-flop, the flip-flop is used as a shift register in the sequential circuit. A scan mode signal for supplementary observation operation, which captures the logic state in the combinational circuit to be observed at the time of the test, is provided on the input side of the flip-flop for the shift register. Logic state output from the flip-flop A multiplexer for selecting a logic state in the combinational circuit, and a multiplexer for selecting a logic state in the combinational circuit to be observed when the scan selection signal is invalid and the scan mode signal is valid. The above-mentioned problem is solved by providing an operation mode control circuit for generating a signal instructing the operation mode.

In the above-described scan test circuit,
By configuring the operation mode control circuit with an exclusive OR circuit that calculates an exclusive OR of the scan selection signal and the scan mode signal, the operation mode control circuit can be relatively easily and with a small number of elements. Can be configured.

Hereinafter, the operation of the present invention will be briefly described.

Normally, in the scan test method, the flip-flops are independently operated or configured as a scan circuit according to either the fetch operation state or the scan operation state. What can be externally observed in the scan test method is the logic state of the flip-flop immediately before switching to the scan operation state.

On the other hand, in order to improve the failure detection rate and the design failure detection rate of the sequential circuit test, it is necessary to be able to control and observe the logical states of more circuit portions in the sequential circuit to be tested. desirable. That is, it is desirable to be able to control and observe the logic state of any circuit part other than the logic state of the flip-flop immediately before switching to the scan operation state.

Here, as shown in FIG. 3 and FIG. 4, in the case of a flip-flop for forming a user circuit shift register, the above-described fetch operation state or the state between the flip-flops forming the user circuit shift register is described. It is always connected regardless of the scan operation state. Therefore, it cannot be said that the scan circuit is effectively used. In the present invention, by utilizing such a flip-flop, a failure detection rate and a design failure detection rate of a sequential circuit test can be easily improved while suppressing an increase in area due to an increase in test circuits.

That is, in the present invention, the logic state of the combinational circuit in the sequential circuit which is desired to be observed at the time of the test is taken into the flip-flop for forming the user circuit shift register. In the present invention, a scan mode signal for a supplementary observation operation for capturing a logic state is newly provided. When the conventional scan selection signal is invalid and the scan mode signal is valid, the above supplementary observation operation is actually performed.

As described above, according to the present invention, it is possible to control and observe the logic states of more circuit portions in the sequential circuit to be tested. Therefore, the failure detection rate and the design failure detection rate of the test of the sequential circuit can be improved. In addition, since the flip-flop of the sequential circuit to be tested is used for controlling and observing the logical state, an increase in the number of elements due to an increase in the number of test circuits can be suppressed, and an increase in area can be suppressed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 5 is a circuit diagram of a scan circuit to which the present invention is applied.

In FIG. 5, scan select signal SE
Is invalid when "0" and valid when "1", as in the conventional FIGS. In the present embodiment,
Applying the present invention, a scan mode signal SM indicating the validity of a supplementary observation operation, which captures a logic state in the combinational circuit to be observed at the time of testing, is newly added to a flip-flop for constituting a user circuit shift register. To be provided. The scan mode signal SM is invalid when "0" and valid when "1".

In the present embodiment, on the input side of the flip-flop FFi, including the one for forming the user circuit shift register, the logic state output from the flip-flop preceding in the scan circuit or the combinational circuit to be observed A multiplexer Mi for selecting an inside logic state is provided.

Further, the operation mode control circuit of the present invention is constituted by an exclusive OR logic circuit G in this embodiment. The exclusive OR logic circuit G captures a logic state in the combinational circuit to be observed when the scan selection signal SE is “0” (invalid) and the scan mode signal SM is “1” (valid). Signal DIi
Is generated by the multiplexer Mi.

In the scan selection signal SE and the scan mode signal SM, three types of operation states are set as in the following states A1 to A3.

A1. Normal operation state: scan selection signal S
When E is “0” and the scan mode signal SM is “0”, the multiplexer Mi (i is 1 and 5 in FIG. 5) takes in the signal DIi from the combinational circuit to be tested. On the other hand, among the flip-flops FFi, those that originally constitute the user circuit shift register in the sequential circuit to be tested are configured so that the user circuit shift register actually operates as a register. or,
The output of each flip-flop FFi is connected to the combinational circuit 1 by a signal DOi and becomes a part of the sequential circuit, respectively.
Operate.

A2. Capture operation state: scan selection signal SE is "0" and scan mode signal SM is "1". Multiplexer Mi (i is 1 to 5 in this figure)
Captures the signal DIi from the combinational circuit to be tested. Therefore, the flip-flop FFi, whether or not the flip-flop is a user circuit shift register, is connected to the combinational circuit 1 by the signal DIi and the signal DOi, respectively, and operates as a part of the sequential circuit. As described above, when the scan selection signal SE is invalid and the scan mode signal SM is valid, an operation corresponding to the supplementary observation operation in the present invention is performed.

A3. Scan operation state: the scan selection signal SE is "1" and the scan mode signal SM is "1". Multiplexer Mi (i is 1 to 5 in this figure)
Selects an output of a flip-flop FF which is a preceding stage in the scan circuit so as to constitute a scan circuit. Therefore, the input and output of the plurality of flip-flops FFi, whether or not of a user circuit shift register or not, are sequentially connected to form a scan circuit. The flip-flops FF including those of the user circuit shift registers are operated as scan circuit shift registers, and the operation of the combinational circuit 1 of the sequential circuit is tested while setting the logic state of each flip-flop FF. Then, the operation of the sequential circuit is tested.

In the present embodiment, the fetch operation state in FIGS. 2 to 4 according to the present embodiment depends on the operation state set in the flip-flop FFi of the user circuit shift register.
It is divided into a normal operation state and a capture operation state. In other words, the user circuit shift register is divided into two depending on whether it functions as a user circuit shift register (normal operation state) or functions as a scan circuit shift register (capture operation state).

As described above, in the present embodiment, the present invention can be effectively applied. By switching the scan mode signal SM, at the time of testing, it is possible to operate a flip-flop configured as a user circuit shift register as a scan circuit shift register in the same manner as a flip-flop that is not a user circuit shift register. The flip-flop of the user circuit shift register does not affect the normal operation even in this case.

As described above, in this embodiment, the flip-flop configured as the user circuit shift register can be used for setting and observing the logic state of a node in the user circuit at the time of testing. Therefore, the number of nodes for which the logical state can be set and observed increases, and the fault detection rate and the design fault detection rate of the sequential circuit test can be improved.

For example, in this embodiment, in FIG.
The logic state can be observed with the signals DI2 to DI4. Further, the logic state can be set by the signals DO2 to DO4. On the other hand, conventionally, in FIGS. 3 and 4, these observations and settings cannot be made with the flip-flop of the user circuit shift register.

In the present embodiment, at least a part of the flip-flop configured as the user circuit shift register is used for the test circuit. Therefore, an increase in area due to an increase in test circuits can be suppressed.

In this embodiment, the scan selection signal SE is the same as the conventional one shown in FIGS. Therefore, when applying various existing design tools and test tools, it is not necessary to take special consideration.

[0036]

According to the present invention, it is possible to improve the failure detection rate and the design failure detection rate of the sequential circuit test while suppressing an increase in area due to an increase in the number of test circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an example of a sequential circuit to be tested in a scan test method.

FIG. 2 is a circuit diagram of a circuit example of a conventional scan circuit.

FIG. 3 is a circuit diagram of a first example of a circuit example of a conventional scan circuit in a flip-flop of a user circuit shift register.

FIG. 4 is a circuit diagram of a second example of a conventional scan circuit using flip-flops of a user circuit shift register.

FIG. 5 is a circuit diagram of an embodiment to which the present invention is applied;

[Description of Signs] 1 ... Combination circuit FF, FF1 to FF5 ... Flip-flop M1 to M5 ... Mux

Claims (2)

[Claims] An input and an output of a flip-flop of a sequential circuit to be tested are sequentially connected to form a scan circuit, the flip-flop is operated as a shift register, and a logic state of each flip-flop is set. Meanwhile, in the scan test circuit that tests the operation of the combinational circuit portion of the sequential circuit, the flip-flop used as a shift register in the sequential circuit may be used in the combinational circuit to be observed during the test. A scan mode signal for supplementary observation operation is newly provided to capture the logic state of the above. At the input side of the flip-flop for the shift register, the logic state output from the flip-flop which is the preceding stage in the scan circuit, or observation is desired. Multiplex for selecting a logic state in the combinational circuit An operation mode control circuit that generates a signal that instructs the multiplexer to select a logic state in the combinational circuit to be observed when the scan selection signal is invalid and the scan mode signal is valid; A scan test circuit, comprising: 2. The scan test circuit according to claim 1, wherein said operation mode control circuit is constituted by an exclusive OR circuit for calculating an exclusive OR of said scan selection signal and said scan mode signal. Scan test circuit characterized.