SU1718367A1 - Pulse sequencer - Google Patents

Abstract

The invention relates to a pulse technique and can be used in discrete automation, remote control and measurement technology. The aim of the invention is to expand the functionality of the device by controlling the parameters of the pulse sequence at arbitrary points in time and simplifying the device. The goal is achieved by introducing into the device a second O-flip-flop 5. a third 9 and fourth 10 memory registers and blocks of n unequivalence elements 11 and N-12 elements each. In addition, the device includes a pulse generator 1, a pulse counter 2, the first 6 and second 7 memory registers, the first D-flip-flop 4, the inverter 3, the AND 13 and OR-NOT 14 elements. At the same time, on the input bus 8 of the device A signal is set up and a 15-signal is written to the bus. Writing information from the code input buses .16 and 17. An output pulse sequence is formed at the forward output of the second D-flip-flop 5. When operating, the pulse shaper ensures that output signals are generated without distortion with writing new sequence control code at arbitrary moments of time. This is achieved by writing to registers 6 and 7, as well as information registers 9 and 10 on different fronts of pulses from generator 1. At the same time, control of such parameters of pulses as duration, phase, period, as well as formation of bursts of pulses. 2 Il. (Ls

Description

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FIG. 2

Claims (1)

Claim A pulse sequence generator containing the first and second memory registers, the information inputs of which are connected to the corresponding information buses of the device, a generator, a pulse counter, a trigger, an AND element, an inverter and an OR-NOT element, for t and h βίο щ с I mean that, in order to expand functionality by controlling the parameters of the generated pulse sequence at arbitrary points in time, as well as simplification, it is additionally equipped with a second trigger, a block of η elements is unequal a block of η AND-NOT elements, as well as the third and fourth memory registers, the information inputs of which are combined with the information outputs of the first and second memory registers, connected by zeroing inputs to the initial setup bus, zeroing the inputs of the third and fourth memory registers and the reset input a pulse counter, the clock input of which is connected to the output of the pulse generator and through the inverter to the clock inputs of the first and second triggers, zeroing the input of the second trigger through element 14 connected to the outputs of the fourth memory register and the first inputs of the corresponding elements of the AND block of η elements of NAND, the outputs of which through the AND element are combined with the control input of the second trigger, and the second inputs are connected to the outputs by the disambiguation element block of η disambiguation elements connected by their the first inputs to the corresponding outputs of the third memory register, and the second inputs to the corresponding bit outputs of the pulse counter. the overflow output of which is connected to the information recording inputs of the third and fourth memory registers, and the information recording inputs of the first and second memory registers are combined with the direct output of the first trigger, the control input of which is combined with the control bus of the device. a .lgshll ^^ Σ ......... g-L ______ — ______________________ A ____.________________ Π ________________________; Σ ________________ ΓΊ __, ___________ w-ι g fll-i _ train 3-1 _______________________________1 ________ | ---------—------------------------'------------- --------- 1---------------------------------- I-1 AND 2 I-3 Κ-1 Κ-2 ........... Π __- ... ΓΊ ____ Figure 2