SU1531202A1 - Digital phase-shifting device - Google Patents

Abstract

The invention relates to radio engineering and can be used to create radio receivers, modulators and signal demodulators. The aim of the invention is to enable the device to operate under various laws of phase change and to extend the range of phase change. The digital phase-shifting device contains a master 1 code, a reversible counter 2, a shaper 3 short pulses and a generator 4. Introduction to the device of the comparator 5, two R-flip-flops 6.7, two elements AND 8.9, element OR 10 and shift register 11 allows to generate on the unit 1 of the code from the analog signal a number written in the binary code, which determines the magnitude of the change in the phase of the information pulse for a given signal period. 2 Il.

Description

The invention relates to a pulsed equipment, as well as radio engineering, and can be used to create radio-receiving devices, modulators, signal demodulators.

The aim of the invention is to expand the field of application by allowing the device to operate under various laws of phase change and extending the range of the phase change.

FIG. 1 shows a block diagram of a digital phase shifter; in fig. 2 - in principle, 15 on the circuit of the driver short pulses.

The digital phase-shifting device (Fig. 1) contains a setting unit 1 of the code, a reversible counter 2, a shaper po 3 short pulses, a generator 4 pulses, a comparator 5, two RS-flip-flops 6 and 7, two elements AND 8 and 9, the element OR 10 and shift register 11.

The shaper of short pulses 25 (Fig. 2) contains three elements NOT 12-14 and two three-input elements I 15 and 16.

In digital phase shifting, the device input device is the first and second inputs of the comparator 5, connected respectively to the zero potential input and the signal input. The output of the comparator 5 is connected to the second input of the shaper 3 short pulses. The output of the generator 4 is connected to the first input of the shaper 3 short pulses, with the C-input of the second RS flip-flop 7, with the first input of the first element And 8 and with the first input of the second element And 9. The first output of the shaper 3 short pulses is connected to the first input element OR 10, the second input of which is connected to the output of the second element AND 9. The second input of element AND 9 with the V input of the shift register 11 is connected to the inverting output of the second RS flip-flop 7, the R input of which is connected to the bus of the first control signal.

Non-inverting output of the first RS-flip-flop 6 is connected to the second input of the element And 8, the output of which is connected to the C-input of the reversible counter 2. The output of the element OR 10 is connected to the C-input of the shift register 11, the address inputs of which are connected where N; with address outputs of the setpoint 1 co35

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Yes. Bus with an addressable busbar connection or with a lift at a version with an R-input

The fos fi (the input of the first c in the element are 15 and 16 the output of the pn with the output in the n of the c and c of the first and 16). In the connection of the element of the head of the first

Digitally Worked

There is a igraniousness in the meander input pulses from the impulse with the info pass synchronous resolution (the legal account from the account of the successful use of time is reduced

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where is N;

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Yes. The input of the setting device 1 code is connected to the bus of the second control signal. The address outputs of the shift register 11 are connected to the address inputs of the reversible counter 2, the P input of which is connected to a low or high logic level installation bus. The output of the device is the output of the reversible counter 2 connected to the R input of the first RS flip-flop 6.

In the short pulse shaper (Fig. 2), the first input is the input of the first element NO 12, connected to the second inputs of the three-input elements 15 and 16. The second input is the third inputs of elements 15 and 16 connected to each other. The output of the first element NOT 12 is connected to the input of the second element NOT 13, the output of the second element NOT 13 is connected to the input of the third element NOT 14 and to the first input of the second element I 16. The output of the third element NOT 14 is connected to the first input of the first element I 15. The first and the second outputs of the short pulse shaper are, respectively, the outputs of the first and second elements 15 and 16.

Digital phase-shifting device operates as follows.

A harmonic signal is fed to the second input of the comparator 5, which is converted into a sequence of square-wave Meander-type pulses, which is fed to the second input of the driver 3 short pulses. From the second output of the imaging unit 3 short pulses synchronously with the pulses of the generator 4, an information pulse is generated, which, passing through the OR 10 element to the synchronization input of the shift register 11, allows the transfer of the recorded number (phase change law) to the reversible counter 2, which counts with the frequency Ehkt The counting direction is determined by the control voltage potential at the P input of the reversible counter 2. At the overflow output of the reversible counter 2, an information pulse is formed through time

where is N;

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- the number recorded in shift register 11;

 takg clock frequency generator 4.

Thus, there is a phase shift of each pulse of the input signal by

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The trigger 6 and the AND element 8 serve to form a pulse allowing the counting only after the appearance of an information pulse at the output of the reversing counter 2. To this end, the S-input of the trigger 6 from the first output of the imaging unit 3 receives a sequence of information pulses shifted by 1 / 2Ttsm (p, -a R-input of the trigger 6 is connected to the switching output of the reversing counter 2, pulses, which passes to the C input of the reversible counter 2 only after the logical unit 1 is established at the second input of the element AND 8. The trigger 7 serves to form a strobe permitting the writing of a code with

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five

Claims (1)

Invention Formula A digital phase-shifting device containing a code setter, a reversible counter, a pulse shaper, whose input is connected to the input bus, and an output - to the input of a short-pulse shaper, a pulse generator, the output of which is connected to the first input of the first element I, characterized in that expanding the field of application by ensuring the device operates under various laws of phase change and extending the range of phase variation, two RS flip-flops are introduced into it, the second AND element, the OR element and the shift register, and m the second input of the short pulse generator is connected to the output of the pulse generator, and the first and second outputs are connected respectively to the S input of the first RS flip-flop and the first input of the OR element, the output of the generator is connected to the first input of the second And element and to the C input of the second RS -trigger, the R-input of which is the input of the first control signal, non-inverting output of the first RS-trig master code 1 to the register 11 shift. 30 hera and the inverting output of the second When applying Fynp to the R input of trigger 7, a positive strobe appears at the inverting output, allowing the code to be written. In turn, the positive potential from the output of the trigger 7, which arrives at the second input of the AND 9 element, allows the clock pulse to pass through the AND 9 element and through the OR 10 element to the synchronization input of the shift register 11, thereby rewriting the number recorded in the shift register 11 to the reverse output counter 2 o The code setting device 1 generates from the analog signal a number recorded in binary code, which determines the amount of change in the phase of the information pulse for a given signal period. RS-flip-flop is connected respectively with the second inputs of the first and second elements And, the output of the first element And is connected to the C-input of the reversible counter, the output of the second element And is connected to the second input of the OR element, the output of which is connected to the C-input of the shift register, whose address inputs connected to the outputs of the setpoint code, the input of which is the input of the second control signal, the inverting output of the second RS flip-flop connected to the V-input of the shift register, the outputs of which are connected to the address inputs of the reversible counter, the P-input which is the input of the setup signal, the output of the reversible counter is connected to the R input of the first RS flip-flop and the output of the device. f1 / e.1